JPS62274673A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62274673A JPS62274673A JP11953386A JP11953386A JPS62274673A JP S62274673 A JPS62274673 A JP S62274673A JP 11953386 A JP11953386 A JP 11953386A JP 11953386 A JP11953386 A JP 11953386A JP S62274673 A JPS62274673 A JP S62274673A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- conductive film
- gate
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims abstract description 29
- 229910052750 molybdenum Inorganic materials 0.000 claims abstract description 11
- 239000011733 molybdenum Substances 0.000 claims abstract description 11
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 9
- 239000004020 conductor Substances 0.000 claims abstract description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 15
- 238000002844 melting Methods 0.000 claims description 14
- 230000008018 melting Effects 0.000 claims description 12
- 238000007772 electroless plating Methods 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 24
- 238000007747 plating Methods 0.000 abstract description 8
- 102000004129 N-Type Calcium Channels Human genes 0.000 abstract description 6
- 108090000699 N-Type Calcium Channels Proteins 0.000 abstract description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052737 gold Inorganic materials 0.000 abstract description 6
- 239000010931 gold Substances 0.000 abstract description 6
- 229910052759 nickel Inorganic materials 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 36
- 238000000137 annealing Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003054 catalyst Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002751 molybdenum Chemical class 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000002574 poison Substances 0.000 description 1
- 231100000614 poison Toxicity 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Landscapes
- Chemically Coating (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
この発明は、半導体装置の製造方法に関し、特に、ガリ
ウム・砒素ショー２トキ接合型電界効果トランジスタ（
以下、 ＧａＡｓＭＥＳＦＥＴと呼ぶ）の製造方法の改
良に係るものである。Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly relates to a method for manufacturing a semiconductor device, and in particular a method for manufacturing a gallium-arsenic two-layer junction field effect transistor (
This invention relates to an improvement in the manufacturing method of GaAs MESFET (hereinafter referred to as GaAs MESFET).
従来例によるゲート・ｎ＋セルフアライメント技術を用
いて製造されたＧａＡｓＭＥＳＦＥＴの概要構成を第２
図に示す。The schematic configuration of a GaAs MESFET manufactured using the conventional gate/n+ self-alignment technology is shown in the second example.
As shown in the figure.
すなわち、この第２図従来例構成において、符号ｌは半
絶縁性ＧａＡｓ基板、２はこの基板１の主面上に形成さ
れたｎ型チャネル層、３はこのｎ型チャネル層２とショ
ット−１−接合させたゲート電極であって、高融点材料
１例えば高融点金属、高融点金属硅化物などからなって
おり、また、４．４はこのゲートをマスクにイオン注入
法お゛よσアニール法などにより、同ゲート電極３にそ
れぞれ隣接して形成される低抵抗ｎ＋層、５．６はこれ
らの各低抵抗ｎ１層４．４にオーム性接触されたソース
、およびドレインの各電極である。That is, in the conventional configuration shown in FIG. 2, reference numeral l denotes a semi-insulating GaAs substrate, 2 denotes an n-type channel layer formed on the main surface of this substrate 1, and 3 denotes a connection between this n-type channel layer 2 and shot -1. - The bonded gate electrode is made of a high melting point material 1, such as a high melting point metal, a high melting point metal silicide, etc., and 4.4 uses this gate as a mask to perform ion implantation, σ annealing, etc. The low-resistance n+ layers 5.6 formed adjacent to the gate electrode 3 are source and drain electrodes that are in ohmic contact with the low-resistance n1 layers 4.4.
こ＼で、この種のＧａＡｓＭＥＳＦＥＴ 、ないしは、
このＧａＡｓＭＥＳＦＥＴによって構成されるＧａＡｓ
集積回路での半導体装置においては、一般に、困難な超
高速動作素子を実現し得るものと期待され、より一層の
高性能化を図るために種々の改善が検討されている現況
にあるもので、この改善のための一つの大きなポイント
は、ＦＥＴの相互コンダクタンスｇ１１を大きくするこ
とであり、このためには、ゲート長Ｌｇの減少と、ゲー
ト・ソース間の直列抵抗Ｒｓの低減とが極めて重要にな
る。This kind of GaAs MESFET or
GaAs formed by this GaAs MESFET
In general, it is expected that it will be possible to realize ultra-high-speed operating elements in integrated circuit semiconductor devices, and various improvements are currently being considered to achieve even higher performance. One major point for this improvement is to increase the mutual conductance g11 of the FET, and for this purpose, it is extremely important to reduce the gate length Lg and the series resistance Rs between the gate and source. Become.
そして、前記ゲー）−ソース間の直列抵抗Ｒｓを低減す
るための手段としては、ゲート・ｎセルファライン（自
己整合）法が知られており、この手段によって製造され
たＧａＡｓＭＥＳＦＥＴが、前記第２図での装置構成で
ある。A gate/n self-alignment method is known as a means for reducing the series resistance Rs between the gate and source, and the GaAs MESFET manufactured by this method is as shown in FIG. This is the device configuration.
しかして、この場合、同装置構成を実現するのに重要な
ポイントは、低抵抗ｎ層の形成であり、そのためには、
前記したように、ゲート電極を形成させた状態で、注入
イオンを活性化するアニール工程が必要とされ１通常の
場合、８００℃程度まで加熱処理されるのが普通である
。However, in this case, the important point to realize the device configuration is the formation of a low resistance n-layer, and for that purpose,
As mentioned above, an annealing step is required to activate the implanted ions with the gate electrode formed, and in normal cases, heat treatment is usually performed to about 800.degree.
従って、このためにゲート電極としては、この加熱処理
によって溶融したり、あるいはＧａＡＳと反応したすせ
ずに、しかも良好なショットキ特性を示す材料を用いる
ようにしており、この電極材料にタングステンシリサイ
ド（ＷＳｉ）など１種々のものが検討されているところ
である。Therefore, for this reason, we use a material for the gate electrode that does not melt or react with GaAS during this heat treatment and exhibits good Schottky characteristics. Various methods are currently being considered, such as WSi).
前記構成による従来めゲート拳ｎ＋セルファラインＧａ
ＡｓＭＥＳＦＥＴにおいては、一方で、高い相互コンダ
クタンスｇｍを有していて、優れた特性が得られるので
あるが、一般にゲート電極としての耐熱性ゲート膜は、
例えば、前記タングステンシリサイド（ＷＳｉ）の場合
、１００ＩＬΩ拳Ｃ■程度と云うように、比較的抵抗率
が高く、かつ一層の高性能化のために、ゲート長の短縮
を図ると、よりゲート抵抗が増して高周波数動作を制限
することになり、殊にゲート幅を大きくとると共に、低
ゲート抵抗の必要なマイクロ波用リニアＦＥ↑などに適
用することが困難であると云う問題点があった。Conventional gate fist n + self-line Ga with the above configuration
AsMESFETs, on the other hand, have a high mutual conductance gm and can provide excellent characteristics, but generally the heat-resistant gate film used as the gate electrode is
For example, in the case of tungsten silicide (WSi), it has a relatively high resistivity of about 100 IL Ω, and if the gate length is shortened in order to further improve performance, the gate resistance will be lower. This further limits high-frequency operation, and there is a problem in that it is difficult to apply it to microwave linear FE↑, which requires a large gate width and low gate resistance.
この発明は従来のこのような問題点を解消するためにな
されたものであって、その目的とするところは、高い相
互コンダクタンスｇｍを有し、かつ低ゲート抵抗で、マ
イクロ波帯の高い周波数においても高性能動作する。こ
の種のＧａＡｓＭＥＳＦＥＴの製造方法を得ることであ
る。This invention was made to solve these conventional problems, and its purpose is to have high mutual conductance gm and low gate resistance, and to operate at high frequencies in the microwave band. Also works with high performance. The object of the present invention is to obtain a method for manufacturing this type of GaAs MESFET.
前記目的を達成するために、この発明に係る半導体装置
、こ−ではＧａＡｓＭＥＳＦＥＴの製造方法は、下層と
なる無電解メッキの困難な導電膜と、上層となる無電解
メッキの可能な導電膜とを、高融点材料により半絶縁性
ＧａＡｓ基板上に積層させて下地ゲート電極とし、ゲー
ト・ｎ＋セルファライン方式による高ｇｍＦＥＴを形成
させた上で、有機膜の被覆によって、上層の無電解メッ
キの可能な導電膜部分のみを露出させ、この露出された
導電膜部分に、低抵抗導電材料による無電解メッキを施
して、下地ゲート電極の上層に低抵抗上部ゲートを形成
することにより、所期のＧａＡｓＭＥＳＦＥＴを製造す
るものである。In order to achieve the above object, a method for manufacturing a semiconductor device, in particular a GaAs MESFET, according to the present invention includes a method for manufacturing a semiconductor device, in particular a GaAs MESFET, in which a lower conductive film that is difficult to be plated by electroless plating and an upper conductive film that can be plated by electroless plating are used. , a high-melting point material is laminated on a semi-insulating GaAs substrate as a base gate electrode to form a high-gm FET using a gate/n+ self-line method, and then covered with an organic film to enable electroless plating of the upper layer. By exposing only the conductive film portion and applying electroless plating with a low-resistance conductive material to the exposed conductive film portion to form a low-resistance upper gate on the upper layer of the underlying gate electrode, the desired GaAs MESFET is manufactured. It is manufactured.
すなわち、この発明方法においては、下地ゲート電極を
構成する上層の無電解メッキの可能な導電膜にのみ、低
抵抗導電材料による上部ゲートを形成でき、これにより
ゲート抵抗を充分に低減できて、高周波数域まで優れた
動作特性を示すＧａＡｓＭＥＳＦＥＴが得られる。That is, in the method of the present invention, the upper gate made of a low-resistance conductive material can be formed only on the upper conductive film that constitutes the base gate electrode and can be electrolessly plated. A GaAs MESFET exhibiting excellent operating characteristics up to the frequency range can be obtained.
以下、この発明に係るＧａＡｓＭＥＳＦＥＴの製造方法
の一実施例につき、第１図（ａ）ないしくｉ）を参照し
て詳細に説明する。Hereinafter, one embodiment of the method for manufacturing a GaAs MESFET according to the present invention will be described in detail with reference to FIGS. 1(a) to 1(i).
第１図（ａ）ないしくｉ）はこの実施例方法を工程順に
示したそれぞれ要部断面図であり、同第１図実施例にお
いて前記第６図従来例と同一符号は同一または相鳥部分
を示している。Figures 1 (a) to (i) are sectional views of main parts showing the method of this embodiment in the order of steps. It shows.
この実施例方法においては、まず、所定の半絶縁性Ｇａ
Ａｓ基板ｌの主面上にあって、イオン注入法およびアニ
ール法などにより、ｎ型チャネル層２を選択的に形成す
る。注入イオンとしてはドナーイオンとなるシリコンを
選択でき、その注入エネルギ、注入イオン量を制御して
所望のＦＥＴ特性を決定する（第１図（ａ））。In this embodiment method, first, a predetermined semi-insulating Ga
An n-type channel layer 2 is selectively formed on the main surface of the As substrate 1 by ion implantation, annealing, or the like. Silicon, which serves as a donor ion, can be selected as the implanted ion, and desired FET characteristics are determined by controlling the implantation energy and amount of implanted ions (FIG. 1(a)).
ついで、前記半絶縁性ＧａＡｓ基板】のｎ型チャネル層
２を含む全面に対して、無電解メッキの困難な高融点材
料による導電膜として、タングステンシリサイド膜１０
を３０００Ａ程度の厚さに、また、無電解メッキの可能
な高融点材料による導電膜として、モリブデン膜１１を
５００Ａ程度の厚さにそれぞれ順次に形成すると共に（
同図（ｂ））、これらの２層膜１０．１１を、写真製版
技術および異方性エツチング（例えばりアクティグ・イ
オン・エツチング）により選択的にパターン加工して、
下地ゲート電極（下地ゲート）３を形成する（同図（Ｃ
））。Next, a tungsten silicide film 10 is deposited on the entire surface of the semi-insulating GaAs substrate, including the n-type channel layer 2, as a conductive film made of a high melting point material that is difficult to electroless plate.
A molybdenum film 11 is sequentially formed to a thickness of about 3000A and a conductive film made of a high melting point material capable of electroless plating to a thickness of about 500A.
(b)), these two-layer films 10 and 11 are selectively patterned by photolithography and anisotropic etching (for example, active ion etching).
A base gate electrode (base gate) 3 is formed (see Figure (C)
)).
次に、前記下地ゲート電極３をマスクにして、イオン注
入法およびアニール法などにより、同ゲートＴＬ極３に
それぞれ隣接して低抵抗ｎ＋層４，４を形成しく同図（
ｄ））、かつ、これらの各低抵抗ｎ＋層４．４上に、オ
ーミック接触するソース電極５．およびドレイン電極６
を、それぞれに前記タングステンシリサイド膜１０より
も薄く、例えば２０００Ａ程度の厚さに形成する（同図
（ｅ））。Next, using the base gate electrode 3 as a mask, low resistance n+ layers 4, 4 are formed adjacent to the gate TL pole 3 by ion implantation, annealing, etc. (see FIG.
d)) and a source electrode 5.4 in ohmic contact on each of these low resistance n+ layers 4.4. and drain electrode 6
are each formed to be thinner than the tungsten silicide film 10, for example, to have a thickness of about 2000 Å (FIG. 4(e)).
その後、これらの全面に有機膜１例えばフォトレジス）
１９１２を２ル１程度の厚さに塗布形成し、適当な熱処
理を加えることによって全表面を平坦化しく同図（ｆ）
）、さらに、例えば酸素を用いたプラズマエツチングな
どにより、このフォトレジスト膜１２を所定の深さまで
エツチング除去し、前記ソース電極５．およびドレイン
電極８をそれぞれに被覆させたま覧の状態で、前記モリ
ブデン膜１１の周囲側面を含む表面を完全に露出させて
おく（同図（ｇ））。After that, an organic film 1 (e.g. photoresist) is applied to these entire surfaces.
1912 is applied to a thickness of about 2 ml, and the entire surface is flattened by applying appropriate heat treatment (Figure (f)).
), the photoresist film 12 is further etched away to a predetermined depth by, for example, plasma etching using oxygen, and the source electrode 5. The surface of the molybdenum film 11, including the surrounding side surfaces, is completely exposed while the molybdenum film 11 is covered with the drain electrode 8 and the drain electrode 8, respectively (FIG. 4(g)).
さらに続いて、このように前記下地ゲート電極３の上部
層、つまりモリブデン膜１１の周囲側面を含む表面を露
出させた状態で、同露出各面にパラジウムなどのメッキ
触媒を付着し、まずニッケル層を５００Ａ程度、ついで
金層を３ＱＯＯＡ程度の厚さにそれぞれ無電解メッキ成
長させることによって、このモリブデン膜１１の周囲側
面を含む表面部にのみ、ニッケル、金からなる上部ゲー
ト１３を付着形成でき（同図（ｈ））るもので、殊に下
地ゲート電極３の下部層であるタングステンシリサイド
Ｉｔ！１０には、触媒毒であるタングステンが含まれる
ことから、間膜１０に対してはメッキ成長がなされず、
このようにして、後に前記ソース電極５．およびドレイ
ン電極日に接触する慣れの全くない、安定した形状の上
部ゲート１３を形成できるのであり、その後、有機溶剤
処理などでフォトレジス）ＩＩ１１２を除去する（同図
（ｉ））ことにより、目的とするところの、 ＧａＡｓ
ＭＥＳＦＥＴを製造し得るのである。Subsequently, with the upper layer of the base gate electrode 3, that is, the surface including the peripheral side surfaces of the molybdenum film 11 exposed, a plating catalyst such as palladium is deposited on each exposed surface, and a nickel layer is first deposited on each exposed surface. By growing the gold layer by electroless plating to a thickness of about 500A and then a gold layer to a thickness of about 3QOOA, the upper gate 13 made of nickel and gold can be deposited and formed only on the surface area including the peripheral side surfaces of this molybdenum film 11 ( (h)) in the same figure, especially the tungsten silicide It! which is the lower layer of the base gate electrode 3! Since 10 contains tungsten, which is a catalyst poison, no plating is grown on the interlayer 10,
In this way, the source electrode 5. It is possible to form an upper gate 13 with a stable shape that does not come in contact with the drain electrode and the drain electrode. After that, by removing the photoresist II 112 by treatment with an organic solvent or the like (see (i) in the same figure), it is possible to form the upper gate 13 with a stable shape. GaAs
MESFETs can be manufactured.
従って、以上のように構成されたＧａＡｓＭＥＳＦＥＴ
においては、ゲート・ｎ會セルファライン技術による高
い相互コンダクタンスｇｍを維持した状態で、比較的高
抵抗（ＩＱＯＪＬΩ・ｃ１１程度）のタングステンシリ
サイドゲートの上部に、極めて低抵抗（数色Ω・ｃｍ程
度）の金メッキ層が被覆されるために、全体としてのゲ
ート抵抗が充分に低く抑制されることになり、このよう
にして得たＧａＡｓＭＥＳＦＥＴでは、高周波数域にお
いて良好な動作特性を示す。Therefore, the GaAs MESFET configured as above
In this case, while maintaining high mutual conductance gm by gate-n-cell line technology, extremely low resistance (about several Ωcm) is placed on top of a tungsten silicide gate with relatively high resistance (about IQOJLΩ・c11). Since the gold plating layer is coated, the overall gate resistance is suppressed to a sufficiently low level, and the GaAs MESFET thus obtained exhibits good operating characteristics in a high frequency range.
こ−で、この実施例方法は、無電解メッキ法によって高
融点ゲート上に低抵抗層を形成する点に特徴を有してお
り、下地ゲート電極３の上部層のみに安定した形状で低
抵抗メッキ層を形成させるのに重要な点は、高融点下地
ゲート電極３をして前記の如く２層構成にしたことであ
り、また金の無電解メッキは、化学反応を利用していて
、その成長膜厚が処理時間と共に飽和するため、使用す
るメッキ液を適当に選択することで、所望のメッキ厚さ
を均一に得るのが容易であり、以後の加工を全く必要と
しない。Thus, the method of this embodiment is characterized in that a low resistance layer is formed on the high melting point gate by electroless plating, and a stable shape and low resistance layer is formed only on the upper layer of the base gate electrode 3. The important point in forming the plating layer is that the high-melting point base gate electrode 3 has a two-layer structure as described above, and electroless gold plating uses a chemical reaction. Since the thickness of the grown film saturates with processing time, by appropriately selecting the plating solution used, it is easy to obtain a desired uniform plating thickness, and no further processing is required.
なお、前記実施例方法においては、高融点下地ゲート電
極を下層のタングステンシリサイドと、上層のモリブデ
ンとによって形成させたが、共に高融点材料であれば、
下層に無電解メッキの困難な材料、上層に無電解メッキ
の可能な材料を任意に選択して用いることができ、また
メッキ層形成に関与するのは、前記したようにゲート上
部のみであるから、下部をさらに他の材料で構成して、
２層以上の多層構造としてもよいことは勿論である。In the method of the above embodiment, the high melting point base gate electrode was formed of the lower layer tungsten silicide and the upper layer molybdenum, but if both are high melting point materials,
A material that is difficult to electroless plate for the lower layer and a material that can be plated electrolessly for the upper layer can be arbitrarily selected and used, and as mentioned above, only the upper part of the gate is involved in the formation of the plated layer. , further comprising the lower part with other materials,
Of course, a multilayer structure of two or more layers may also be used.
以上詳述したように、この発明方法によるときは、半絶
縁性ＧａＡｓ基板上にあって、下層となる無電解メッキ
の困難な導電膜と、上層となる無電解メッキの可能な導
電膜とを、高融点材料により積層させて下地ゲート電極
とし、ゲート・ｎ÷セルファライン方式による高ｇｍＦ
ＥＴを形成させた上で、有機膜の被覆によって、上層の
無電解メッキの可能な導電膜部分のみを露出させ、この
露出された導電膜部分に、低抵抗導電材料による無電解
メッキを施すようにしたから、上層の高融点材料を用い
た導電膜にのみ、低抵抗の上部ゲートを極めて簡単に、
しかも生産性よく低コストで形成し得るのであり、これ
によりゲート抵抗を充分に低減できて、高周波数域に至
るまで優れた動作特性を示すＧａＡｓＭＥＳＦＥＴを容
易に得られるものである。As described in detail above, when the method of the present invention is used, a conductive film as a lower layer, which is difficult to be plated by electroless plating, and a conductive film as an upper layer, which can be plated electrolessly, are formed on a semi-insulating GaAs substrate. , a high-gmF layer is formed using a high-melting-point material as a base gate electrode, and a gate-n÷self-line method is used.
After forming ET, only the upper conductive film part that can be electrolessly plated is exposed by coating with an organic film, and this exposed conductive film part is subjected to electroless plating with a low resistance conductive material. Therefore, it is extremely easy to form a low-resistance upper gate only on the conductive film using a high-melting-point material as the upper layer.
In addition, it can be formed with good productivity and at low cost, thereby making it possible to sufficiently reduce gate resistance and easily obtain a GaAs MESFET that exhibits excellent operating characteristics up to a high frequency range.
第１図（ａ）ないしくｉ）はこの発明に係る半導体装置
（ＧａＡＳＭＥＳＦＥＴ）の製造方法の一実施例を工程
順に示したそれぞれ要部断面図であり、また第２図は同
上従来例による半導体装置（ＧａＡＳＭＥＳＦＥＴ）の
要部構成を示す断面図である。
ｌ・・・・半絶縁性ＧａＡｓ基板、２・・・・ｎ型チャ
ネル層、３・・・・下地ゲート電極、４・・・・低抵抗
ｎ＋層、５・・・・ソース電極、６・・・・ドレイン電
極、１０・・・・無電解メッキの困難な高融点材料によ
る導電膜（タングステンシリサイドＭ） 、 １１・・
・・無電解メッキの可能な高融点材料による導電膜（モ
リブデン１り 、 １２・・・・フォトレジスト膜（有
＠［） 、 １３・・・・低抵抗の上部ゲート。
代理人 大 岩 増 雄
第１＠
４：イｅＸｔｆｓ、ＸＬｎ中４Ｉ
第１図
Ｉ
６：ドレイ）を１蛋
１２ニアｒ）レジ°Ｚト１１黄（ｉ＠Ｊｌｌ）第１図
１３： イＰ！、■内、ＪＬｈ奮不プ一ト第２図
手続補正書（自発）
２、発明の名称
半導体装置の製造方法
３、補正をする者
事件との関係 特許出願人
住 所 東京都千代田区丸の内二丁目２番３号名
称 （６０１）三菱電機株式会社代表者 志 岐
守 哉
４、代理人
住 所 東京都千代田区丸の内二丁目２番３号５
、補正の対象
明細書の発明の詳細な説明の欄FIGS. 1(a) to 1(i) are sectional views of essential parts showing an embodiment of the method for manufacturing a semiconductor device (GaASMESFET) according to the present invention in the order of steps, and FIG. FIG. 2 is a cross-sectional view showing the configuration of main parts of the device (GaASMESFET). l... Semi-insulating GaAs substrate, 2... n-type channel layer, 3... base gate electrode, 4... low resistance n+ layer, 5... source electrode, 6... ... Drain electrode, 10... Conductive film made of high melting point material that is difficult to electroless plate (tungsten silicide M), 11...
... Conductive film made of high melting point material that can be electroless plated (Molybdenum 1), 12... Photoresist film (with @[), 13... Low resistance upper gate. Agent: Masuo Oiwa 1st @ 4: Y e , ■, JLh Bokufutsu Figure 2 procedural amendment (voluntary) 2. Name of the invention Method for manufacturing semiconductor devices 3. Relationship to the case of the person making the amendment Patent applicant address 2 Marunouchi, Chiyoda-ku, Tokyo Chome 2-3 Name (601) Mitsubishi Electric Corporation Representative Shiki
Moriya 4, agent address 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo
, column for detailed description of the invention in the specification subject to amendment
Claims (4)
下層となる無電解メッキの困難な高融点材料を用いた導
電膜、ついで上層となる無電解メッキの可能な高融点材
料を用いた導電膜をそれぞれ順次に形成し、かつパター
ン加工して、下地ゲート電極を形成する工程と、これら
の全面を適宜、無電解メッキの困難な有機膜により被覆
させた後、少なくとも前記無電解メッキの可能な導電膜
を露出させる工程と、この無電解メッキの可能な導電膜
の露出面に、低抵抗導電材料による無電解メッキを施し
て、下地ゲート電極の上層に低抵抗上部ゲートを形成す
る工程とを含むことを特徴とする半導体装置の製造方法
。(1) On a semi-insulating gallium arsenide (GaAs) substrate,
A lower conductive film made of a high melting point material that is difficult to electroless plate, and then an upper conductive film made of a high melting point material that can be plated electrolessly, are formed in sequence, and patterned to form the base layer. a step of forming a gate electrode, a step of appropriately covering the entire surface thereof with an organic film that is difficult to electroless plating, and then a step of exposing at least the conductive film that can be electroless plated; 1. A method for manufacturing a semiconductor device, the method comprising the step of electroless plating with a low-resistance conductive material on an exposed surface of a conductive film to form a low-resistance upper gate on a layer above a base gate electrode.
リサイド膜である特許請求の範囲第１項に記載の半導体
装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the conductive film that is difficult to electroless plate is a tungsten silicide film.
ある特許請求の範囲第１項または第２項に記載の半導体
装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the conductive film that can be electrolessly plated is a molybdenum film.
膜である特許請求の範囲第１項、第２項または第３項に
記載の半導体装置の製造方法。(4) The method for manufacturing a semiconductor device according to claim 1, 2, or 3, wherein the organic film that is difficult to electroless plate is a photoresist film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11953386A JPS62274673A (en) | 1986-05-22 | 1986-05-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11953386A JPS62274673A (en) | 1986-05-22 | 1986-05-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62274673A true JPS62274673A (en) | 1987-11-28 |
Family
ID=14763638
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11953386A Pending JPS62274673A (en) | 1986-05-22 | 1986-05-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62274673A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63248178A (en) * | 1987-04-02 | 1988-10-14 | Nec Corp | Field-effect transistor |
| JPH01198079A (en) * | 1988-02-02 | 1989-08-09 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH02138750A (en) * | 1988-08-24 | 1990-05-28 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| US5272111A (en) * | 1991-02-05 | 1993-12-21 | Mitsubishi Denki Kabushiki Kaisha | Method for manufacturing semiconductor device contact |
-
1986
- 1986-05-22 JP JP11953386A patent/JPS62274673A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63248178A (en) * | 1987-04-02 | 1988-10-14 | Nec Corp | Field-effect transistor |
| JPH01198079A (en) * | 1988-02-02 | 1989-08-09 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH02138750A (en) * | 1988-08-24 | 1990-05-28 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| US5272111A (en) * | 1991-02-05 | 1993-12-21 | Mitsubishi Denki Kabushiki Kaisha | Method for manufacturing semiconductor device contact |
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