JPH05275457A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a Schottky gate FET having a T-shaped gate structure and its manufacturing method wherein source resistance or the like can be reduced, and a gate electrode can be easily connected with a source electrode or a drain electrode. CONSTITUTION:After a silicon oxide film 6 is formed on an N-GaAs layer 4 on a GaAs substrate 2, a contact hole is formed, and a tungsten silicide layer 7 of 200nm in thickness is formed as a gate electrode forming metal layer on the whole surface. An AuGe/Au layer 8b as a metal layer for working a gate electrode is formed on the tungsten silicide layer 7 above the contact hole. The whole surface is coated with resist 14, and patterning is performed by eliminating the resist 14 on the upper part of a region for forming a source/ drain electrode on the upper part of the AuGe/Au layer 8b and on both sides of the AuGe/Au layer 8b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a Schottky gate FET and its manufacturing method.

[0002]

2. Description of the Related Art In recent years, Schottky gate FETs have come to be used to realize ultra-high speed, low power consumption LSIs. As a semiconductor substrate used for the Schottky gate FET, a compound semiconductor substrate using a GaAs-based material, which generally has a higher electron mobility than silicon, is used. The gate structure of the Schottky gate FET includes an ion implantation type and a recess type. However, the recess type can reduce the short channel effect caused by the wraparound of the ions as compared with the ion implantation type, and the short gate element can be formed. Heterojunction FET because it is easy to make stably
It is used in etc.

This recess gate type gate electrode has a track record in LN (Low Noise) HEMT and the like as a T type gate electrode having a T-shaped cross section formed by etching. According to this T-type gate structure, a short gate is realized below the gate that makes a Schottky junction, and the cross-sectional area of the gate electrode is increased above the gate to improve electromigration resistance and increase the current density. It is possible to prevent it and improve the reliability of the device.

A conventional Schottky gate FET having a T-type gate electrode will be described with reference to FIG. An n-GaAs layer 4 which is an impurity diffusion layer is formed on the GaAs substrate 2, and a silicon oxide film 6 is formed on the n-GaAs layer 4.
The contact hole is opened to make a Schottky junction with the n-Ga1As layer 4, and the arm portion 8a is projected to form the T-type gate electrode 8 having a T-shaped cross section. A resist 14 is applied to the entire surface and patterned, and the silicon oxide film 6 in the regions B and C where the source electrode 10 and the drain electrode 12 are to be formed is removed by etching. The silicon oxide film 6 is slightly side-etched for later lift-off (FIG. 12).
(A)).

The T-type gate electrode 8 thus formed and the resist 14 used for patterning the silicon oxide film 6 are used as they are as a mask to form a metal layer of a source / drain electrode forming material on the entire surface. N on both sides of 8
The source electrode 10 and the drain electrode 12 that make ohmic contact with the GaAs layer 4 are formed in a self-aligned manner, and unnecessary metal layers are lifted off together with the resist 14. A metal layer 8b is formed on the T-shaped gate electrode 8 (FIG. 12).
(B)). In this way, the arm portion 8 of the T-shaped gate electrode 8 is
By forming the thickness of the source electrode 10 and the gate electrode 12 to be lower than the height of a, insulation between the electrodes is achieved,
Moreover, since the source electrode 10 and the drain electrode 12 can be formed in a self-aligned manner by the arm length of the T-shaped gate electrode 8, the distance between the source electrode 10 and the drain electrode 12 and the gate electrode 8 can be shortened. Therefore, a Schottky gate FET with reduced source resistance can be obtained.

[0006]

However, the Schottky gate FET having the conventional T-type gate electrode described above.
Has processing problems. In the GaAs FET, an Au-based material is used as the electrode material of the source / drain ohmic electrode. Since this Au-based material is difficult to etch, processing by lift-off is generally performed as described above. However, when the photoresist 14 for performing lift-off is applied, the resist 14a above the T-type gate electrode 8 is formed in a convex shape gentler than the surroundings by the thickness of the gate electrode as shown by the broken line in FIG. As a result, the resist 14 cannot be formed flat.

Generally, the exposure conditions of the resist must be sensitively changed according to the change in the thickness of the resist 14. When the source / drain ohmic electrode is formed in the sections B and C in FIG. 12A, if the thickness of the resist 14 changes in a concavo-convex shape, a predetermined depth of focus in exposure cannot be obtained. As a result, the patterning accuracy of the resist 14 decreases. In order to prevent this, if a flat portion of the resist 14 is patterned to form a gate / drain ohmic electrode, the distance between the gate and the source and between the gate and the drain is increased, and the source resistance and the like increase. There is a problem that the device characteristics deteriorate.

Further, when it is attempted to construct a digital circuit such as a ring oscillator by using the conventional method of manufacturing the Schottky gate FET having the T-type gate structure, the gate electrode and the source electrode or the drain electrode are connected in the element. Therefore, a plurality of wiring layers must be further stacked, which causes a problem that the number of manufacturing processes is increased. An object of the present invention is to reduce the source resistance and the like, and also, a Schottky gate FET having a T-type gate structure capable of easily connecting the gate electrode to the source electrode or the drain electrode.
And a method for manufacturing the same.

[0009]

The above object is to provide a semiconductor substrate, an impurity diffusion layer formed on the semiconductor substrate,
The insulating film formed on the impurity diffusion layer is Schottky-junctioned with the impurity diffusion layer through a contact hole opened in the insulating film to insulate the contact hole from the contact hole so as to have a T-shaped cross section. A T-shaped gate electrode having an arm extending over the film, a source electrode that opens the insulating film and makes an ohmic contact on the impurity diffusion layer, and the T-type gate electrode is provided on the opposite side of the source electrode. In a semiconductor device having an insulating film opening and a drain electrode which makes an ohmic junction on the impurity diffusion layer, an etching-resistant conductive material that extends over the T-shaped gate electrode and wider than the arm portion of the T-shaped gate electrode. It is achieved by a semiconductor device characterized in that a layer is formed.

Further, the above object is to form an impurity diffusion layer on a semiconductor substrate, form an insulating film on the impurity diffusion layer, open a contact hole, and form a metal layer for forming a gate electrode on the entire surface. On the metal layer for forming the gate electrode above the contact hole, a thin metal layer for gate electrode processing having a gate electrode pattern shape and having etching resistance serving as a mask for processing the gate electrode is formed, and a resist is formed on the entire surface. Coating, removing and patterning the resist on the gate electrode processing metal layer and on the source / drain electrode formation planned regions on both sides of the gate electrode processing metal layer, and patterning; Etching while side-etching the metal layer for forming the gate electrode and the silicon oxide film using the formed resist as a mask As a result, the first arm portion made of the metal layer for forming the gate electrode and protruding from the contact hole onto the insulating film and the upper portion of the first arm portion are wider than the first arm portion. Forming a T-shaped gate electrode having a second arm portion formed of the gate electrode processing metal layer and forming a Schottky junction with the impurity diffusion layer, and simultaneously forming source / drain electrodes on both sides of the T-shaped gate electrode. Exposing the impurity diffusion layer in the region to be formed,
A source electrode and a drain electrode forming metal layer are formed on the entire surface, and the resist is removed to lift off the source electrode and drain electrode forming metal layer on the resist and form an ohmic contact with the impurity diffusion layer. And a drain electrode are formed.

Further, the above object is to provide a semiconductor substrate, an impurity diffusion layer formed on the semiconductor substrate, an insulating film formed on the impurity diffusion layer, and a contact hole formed in the insulating film. And a Schottky junction with the impurity diffusion layer, and a T-shaped gate electrode having an arm protruding from the contact hole onto the insulating film so as to have a T-shaped cross section, and the impurity diffusion by opening the insulating film. A semiconductor device having a source electrode that makes ohmic contact on a layer, and a drain electrode that makes ohmic contact on the impurity diffusion layer by opening the insulating film on the side opposite to the source electrode with respect to the T-type gate electrode, The source electrode or the drain electrode extends to an upper portion of the T-shaped gate electrode, and an end portion of the source electrode or the drain electrode is formed to be wider than one end of the arm portion of the T-shaped gate electrode. It is achieved by a semiconductor device according to claim being.

Further, the above object is to form an impurity diffusion layer on a semiconductor substrate, form an insulating film on the impurity diffusion layer, open contact holes, and form a metal layer for forming a gate electrode on the entire surface. The gate electrode forming metal layer and the insulating film in one region of the source electrode or drain electrode formation planned region are opened, and ohmic contact is made to the impurity diffusion layer exposed in the opened one region, and the gate electrode One electrode of a source electrode or a drain electrode, on which a thin first metal layer extending to a gate electrode formation-scheduled region on the formation metal layer is deposited, is formed, a resist is applied on the entire surface, and the first metal layer is formed. The resist in the upper region and the other region of the source electrode or drain electrode formation planned region is removed and patterned to form the first metal layer and the patterned resist. The mask electrode is used as a mask to etch and remove the gate electrode forming metal layer and the insulating film while side etching, thereby forming an arm portion protruding from the contact hole onto the insulating film, and forming the impurity diffusion layer and the Schottky. A T-type gate electrode to be joined is formed, at the same time, the impurity diffusion layer in the other region is exposed, a second metal layer is formed on the entire surface, and the resist is removed to remove the second metal layer on the resist. This is achieved by a method for manufacturing a semiconductor device, characterized in that the metal layer is lifted off to form the other electrode of the drain electrode or the source electrode which makes ohmic contact with the impurity diffusion layer.

Further, the above object is to provide a semiconductor substrate, an impurity diffusion layer formed on the semiconductor substrate, an insulating film formed on the impurity diffusion layer, and first and first openings formed in the insulating film. Schottky junction with the impurity diffusion layer through the second contact hole, and first and second arm portions protruding from the first and second contact holes onto the insulating film so as to have a T-shaped cross section. Second T-type gate electrode, first and second source electrodes that open the insulating film and make ohmic contact on the impurity diffusion layer, and the first and second T-type gate electrodes with respect to the first and second T-type gate electrodes. In the semiconductor device having the first and second drain electrodes which open the insulating film on opposite sides of the first and second source electrodes and make ohmic contact on the impurity diffusion layer, the first T-type gate Electrode top An etching resistant conductive layer is formed that extends over the arm portion of the first T-shaped gate electrode, the second source electrode extends to an upper portion of the second T-shaped gate electrode, and an end portion is formed. Is formed so as to extend wider than one end of the arm portion of the second T-shaped gate electrode, and
And a drain electrode of the semiconductor device.

Further, the above object is to form an impurity diffusion layer on a semiconductor substrate, form an insulating film on the impurity diffusion layer, and open contact holes in the first and second gate electrode formation planned regions. A metal layer for forming a gate electrode is formed on the entire surface, and the metal layer for forming a gate electrode in one region of the first source electrode or drain electrode forming region on the side of the first gate electrode forming region and the gate electrode forming metal layer An insulating film is opened, a thin metal layer is formed on the entire surface and patterned, and a gate electrode pattern shape is formed on the gate electrode forming metal layer in the second gate electrode forming planned region for processing the gate electrode. A second metal layer for processing a gate electrode, which has a resistance to etching and serves as a mask, is formed, and ohmic contact is made with the impurity diffusion layer exposed in the one of the opened regions. One of the first source electrode and the drain electrode extending to the first gate electrode formation-scheduled region on the electrode forming metal layer is formed, and a resist is applied on the entire surface to form the first source electrode or the drain. An upper part of one of the electrodes and the other region of the first source electrode or drain electrode formation planned region, and an upper part of the second gate electrode processing metal layer and both sides of the second gate electrode processing metal layer. The resist on the second source / drain electrode formation planned region is removed and patterned, and one of the first source electrode and the drain electrode, the second gate electrode processing metal layer, and the patterned layer are formed. Using the resist as a mask, the gate electrode forming metal layer and the insulating film are side-etched and removed by etching to remove the contact. An arm portion protruding from the hole on the insulating film is formed to form first and second T-type gate electrodes that make a Schottky junction with the impurity diffusion layer, and at the same time, the first source electrode or drain electrode is to be formed. The other region of the region and the second source /
The impurity diffusion layer in the drain electrode formation planned region is exposed, a metal layer is formed on the entire surface, and the resist is removed to lift off the metal layer on the resist.
One of the other one of the first drain electrode and the source electrode that makes an ohmic contact with the impurity diffusion layer, and one of the second source electrode and the drain electrode connected to one of the first drain electrode and the source electrode. And the other electrode of the second source electrode or the drain electrode are formed by the method of manufacturing a semiconductor device.

[0015]

According to the present invention, by forming a thin metal layer for processing a gate electrode having etching resistance,
Since the resist applied to the entire surface can be flattened, the resist can be accurately patterned,
Therefore, the source resistance and the like can be reduced. Furthermore, since the distance between the gate and the source / drain metal can be increased, the parasitic capacitance can be reduced. Further, it is possible to realize a Schottky gate FET having a T-type gate structure in which the gate electrode can be easily connected to the source electrode or the drain electrode.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a method of manufacturing the same according to a first embodiment of the present invention will be described with reference to FIGS. GaA
An n-GaAs layer 4 having a thickness of 200 nm is formed on the s substrate 2 by diffusing impurities in a concentration of about 2 × 10 ¹⁷ cm ^−3.
After forming a silicon oxide film 6 having a thickness of 300 nm on the As layer 4, a contact hole for forming a gate electrode is opened in the silicon oxide film 6 (FIG. 1A).

Next, tungsten silicide (WSi) having a thickness of 200 nm is formed on the entire surface as a metal layer for forming a gate electrode.
The layer 7 is formed (FIG. 1B). Next, on the tungsten silicide layer 7 above the contact hole, A as an etching-resistant metal layer for gate electrode processing which has a gate electrode pattern shape and serves as a mask for processing the gate electrode.
The uGe / Au layer 8b is formed with a thickness of 10/100 nm (FIG. 2A).

Next, a resist 14 is applied on the entire surface and Au is applied.
Resist 1 on the Ge / Au layer 8b and on the source / drain electrode formation-scheduled regions on both sides of the AuGe / Au layer 8b.
4 is removed and patterned. AuGe / Au layer 8b
As shown by the broken line in FIG.
Since the resist 14a in the region where the source / drain electrodes are to be formed is flattened and formed, the resist 1 is highly accurately formed.
4 is patterned.

Next, Au, which is a metal layer for processing the gate electrode, is formed.
Ge / Au layer 8b and patterned resist 14
Using the tungsten silicide layer 7 and the silicon as a mask.
Etching removal while side etching the oxide film 6
To do. The tungsten silicide layer 7 has a pressure of 10 Pa.
CF_FourAnd O₂SF in the atmosphere of or at a pressure of 1 Pa ₆
Reactive ion etching (RIE) in an atmosphere of
The silicon oxide film 6 is CHF₃By RIE in the atmosphere
Is etched.

Thus, the WSi arm portion 8a protruding from the contact hole onto the silicon oxide film 6 and the AuGe / Au layer 8b formed on the arm portion 8a and the end portion protruding more widely than the arm portion 8a are formed. , N-GaAs layer 4
A T-type gate electrode 8 is formed which makes a Schottky junction with. At the same time, the n-GaAs layer 4 in the regions where the source / drain electrodes are to be formed is also exposed on both sides of the T-type gate electrode 8 (FIG. 2).
(B)).

Next, a 20/30 AuGe / Au layer 8c, which is a metal layer for forming a source electrode and a drain electrode, is formed on the entire surface.
The source of the AuGe / Au layer having a thickness of 20/300 nm, which is evaporated to a thickness of 0 nm and lifts off the AuGe / Au layer 8c on the resist 14 by removing the resist 14 to form an ohmic contact with the n-GaAs layer 4. Electrode 10
And the drain electrode 12 is formed (FIG. 3A).

Next, the unnecessary tungsten silicide layer 7
Are removed by RIE to complete the semiconductor device according to the present embodiment (FIG. 3B). As shown in FIG. 3A, the semiconductor device according to this embodiment has a GaAs substrate 2 and an n-GaAs impurity diffusion layer formed on the GaAs substrate 2.
The layer 4, the silicon oxide film 6 formed on the n-GaAs layer 4, and the n-GaAs layer 4 are Schottky-junctioned through the contact hole opened in the silicon oxide film 6, and the cross section is T-shaped. As described above, the T-shaped gate electrode 8 having the arm portion 8a overhanging the silicon oxide film 6 from the contact hole, and the etching-resistant material which overhangs the arm portion 8a of the T-type gate electrode 8 above the T-type gate electrode 8 AuGe / Au
The layers 8b and 8c and the silicon oxide film 6 are opened to form n-Ga.
A source electrode 10 that makes an ohmic contact on the As layer 4 and T
This is a Schottky gate FET having a drain electrode 12 having an ohmic junction on the n-GaAs layer 4 by opening a silicon oxide film 6 on the side opposite to the source electrode 10 with respect to the type gate electrode 8.

According to the method of manufacturing a semiconductor device of this embodiment, the resist applied to the entire surface can be planarized by forming the metal layer for processing the gate electrode, which has etching resistance and is thin. Therefore, the resist can be patterned with high accuracy, and thus the source resistance and the like can be reduced. Further, according to the semiconductor device and the manufacturing method thereof according to the present embodiment, the arm portion 8 of the T-type gate electrode is formed.
Since a does not contact the source electrode 10 and the drain electrode 12, the source electrode 10 and the drain electrode 12
Can be increased to about 450 nm. The source electrode 10 of the conventional semiconductor device as shown in FIG.
The height of the drain electrode 12 must be lower than the height of the arm portion 8a of the T-type gate electrode 8, and the height is about 250 nm. Therefore, according to the semiconductor device of the present embodiment, the sheet resistance and the like of the source electrode 10 and the drain electrode 12 can be improved as compared with the conventional semiconductor device.

Au is used as the metal layer for processing the gate electrode.
The Ge / Au layer 8b was used, but layers of other materials, such as T
An i / Au layer may be used. A semiconductor device and a method of manufacturing the same according to a second embodiment of the present invention will be described with reference to FIGS. Impurities of 2 × 10 ¹⁷ cm on the GaAs substrate 2
The n-GaAs layer 4 having a thickness of 200 nm diffused by about ^-3 is formed, the silicon oxide film 6 having a thickness of 300 nm is formed on the n-GaAs layer 4, and then the silicon oxide film 6 is formed for forming a gate electrode. Open contact holes (Fig. 4
(A)).

Next, tungsten silicide (WSi) having a thickness of 200 nm is formed on the entire surface as a metal layer for forming a gate electrode.
The layer 7 is formed (FIG. 4B). Next, the tungsten silicide (WSi) layer 7 and the silicon oxide film 6 in the region where the source electrode is to be formed are removed by etching to open the n-G.
The aAs layer 4 is exposed (FIG. 5A).

Next, a thin AuGe / Au layer having a thickness of 20/150 nm is formed on the entire surface as a source electrode forming metal layer. A resist 20 is applied and patterned to form an ohmic contact with the n-GaAs layer 4 exposed in the opened source electrode formation planned region, and to extend to the gate electrode formation planned region on the tungsten silicide layer 7, thickness 20/1.
A 50 nm thin AuGe / Au layer 18 is formed (FIG. 5).
(B)).

Next, a resist 14 is applied on the entire surface and Au is applied.
The resist 14 on the Ge / Au layer 18 and on the drain electrode formation planned region is removed and patterned. AuGe
Since the thickness of the / Au layer 18 is thin, as shown by the broken line in FIG.
Since a is flattened and formed, the resist 14 can be patterned with high accuracy.

By using the AuGe / Au layer 18 and the patterned resist 14 as a mask, the tungsten silicide layer 7 and the silicon oxide film 6 are side-etched and removed. Thus, the WSi arm portion 8a protruding from the contact hole onto the silicon oxide film 6 and the AuGe / Au layer 18 having an end portion protruding wider than the arm portion 8a are formed above the arm portion 8a. GaA
A T-type gate electrode 8 that forms a Schottky junction with the s layer 4 is formed, and at the same time, n-GaAs in the drain electrode formation planned region is formed.
The layer 4 is exposed (FIG. 6 (a)).

Next, a AuGe / Au layer 22 which is a metal layer for forming a drain electrode is vapor-deposited on the entire surface to a thickness of 20/300 nm, and the resist 14 is removed to lift off the AuGe / Au layer 22 on the resist 14. , N-G
A thickness of 20 / 300n that makes ohmic contact with the aAs layer 4
The drain electrode 12 of the AuGe / Au layer of m is formed (FIG. 6B).

Next, the unnecessary tungsten silicide layer 7
Are removed by RIE to complete the semiconductor device according to the present embodiment (FIG. 7). As shown in FIG. 7, the semiconductor device according to the present embodiment has a GaAs substrate 2, an n-GaAs layer 4 which is an impurity diffusion layer formed on the GaAs substrate 2, and an n-type semiconductor layer.
Through the silicon oxide film 6 formed on the GaAs layer 4 and the contact hole opened in the silicon oxide film 6, n
-A Schottky junction with the GaAs layer 4 is provided, and the T-shaped gate electrode 8 in which the arm portion 8a extends from the contact hole above the silicon oxide film 6 so as to have a T-shaped cross section, and the silicon oxide film 6 are opened. An ohmic junction is formed on the n-GaAs layer 4 and extends to and is connected to the upper portion of the T-type gate electrode 8.
AuGe overhanging the arm portion 8a of the T-shaped gate electrode 8
Source electrode 10 formed of the / Au layers 18 and 22, and an AuGe / Au layer that forms an ohmic junction on the n-GaAs layer 4 by opening a silicon oxide film 6 on the side opposite to the source electrode 10 with respect to the T-type gate electrode 8. Drain electrode 12 composed of 22
And a Schottky gate FET having

According to the present embodiment, since the metal layer for processing the gate electrode, which has etching resistance and has a small thickness, is formed, it is possible to apply the flattened resist on the entire surface with high accuracy. The resist can be patterned and therefore the source resistance etc. can be reduced. Further, it is possible to realize a Schottky gate FET having a T-type gate structure in which the gate electrode is easily connected to the source electrode or the drain electrode.

Although the present invention is applied to the semiconductor device in which the source electrode is connected to the T-type gate electrode in this embodiment, it may be used in the semiconductor device in which the T-type gate electrode and the drain electrode are connected. A semiconductor device and a method of manufacturing the same according to a third embodiment of the present invention will be described with reference to FIGS.

The present embodiment is characterized in that a semiconductor device in which different elements are connected is manufactured by combining the semiconductor device manufacturing methods described in the first and second embodiments. In this embodiment, a case where a ring oscillator is formed as shown in FIG. 11 will be described. 11
11A is a logic circuit diagram of the ring oscillator, and FIG.
(B) is the circuit diagram. FIG. 11C is a plan view schematically showing a semiconductor device in which the circuit of FIG. 11B is formed. The semiconductor device according to the present embodiment and the method for manufacturing the same as seen from the AA cross section of FIG.
A description will be given using 0. 2 × impurities on the GaAs substrate 2
200 nm thick n-Ga diffused by about 10 ¹⁷ cm ⁻³
An As layer 4 is formed and a thickness of 300 n is formed on the n-GaAs layer 4.
m silicon oxide film 6 is formed, the silicon oxide film 6
Contact holes for forming two gate electrodes are opened at the two positions (FIG. 8A).

Next, tungsten silicide (WSi) having a thickness of 200 nm is formed on the entire surface as a metal layer for forming a gate electrode.
The layer 7 is formed (FIG. 8B). Next, FIG. 9 (a)
The tungsten silicide (WSi) layer 7 and the silicon oxide film 6 in the area where the source electrode is to be formed in the area A shown in (b) are removed by etching to open the n-GaAs layer 4.

Next, a thin AuGe / Au layer having a thickness of 20/150 nm is formed on the entire surface, a resist 20 is applied and patterned, and the n-GaAs layer exposed in the source electrode formation planned region of the opened A region is formed. Ohmic junction to 4,
A thin AuGe layer with a thickness of 20/150 nm that extends to the region where the gate electrode is to be formed on the tungsten silicide layer 7.
/ Au layer 18 is formed, and on the tungsten silicide layer 7 in the B region, an AuGe / Au layer having a gate electrode pattern shape and serving as an etching-resistant gate electrode processing metal layer that serves as a processing mask for the gate electrode. 8b is formed (FIG. 9A).

Next, a resist 14 is applied on the entire surface and Au is applied.
The resist 14 on the Ge / Au layer 18 and on the drain electrode formation planned region in the A region is removed, and at the same time, the A in the B region is removed.
The resist 14 is removed and patterned on the upper part of the uGe / Au layer 8b and the upper regions of the source / drain electrode formation regions on both sides of the AuGe / Au layer 8b. AuGe / Au layer 8
Since the thicknesses of a and 18 are thin, as shown by the broken line in FIG. 9B, the resist 14a in the drain electrode formation planned region is formed by being flattened, so that the resist 14 can be formed with high accuracy.
Can be patterned.

By using the AuGe / Au layers 8a and 18 and the patterned resist 14 as a mask, the tungsten silicide layer 7 and the silicon oxide film 6 are side-etched and removed. By doing so, the WSi that is projected from the contact hole onto the silicon oxide film 6 is formed.
And an AuGe / Au layer 8a or an AuGe / Au layer 18 whose ends are wider than the arm portion 8a are formed on the upper portion of the arm portion 8a. The T-type gate electrodes 8 are formed in the B region, and at the same time, n in the region where the drain electrode is to be formed in the A region
The -GaAs layer 4 and the n-GaAs layer 4 in the region where the source / drain electrodes are to be formed in the B region are exposed (FIG. 9B).

Next, a 20/3 AuGe / Au layer is formed on the entire surface.
The AuGe / Au layer on the resist 14 is lifted off by depositing a film having a thickness of 00 nm and removing the resist 14. A drain electrode 12 in the A region and a source electrode 11 in the B region of the AuGe / Au layer having a thickness of 20/300 nm, which makes ohmic contact with the n-GaAs layer 4, are formed.
Common electrode 1 for the source electrode in the region and the drain electrode in the region B
The AuGe / Au layer 22 to be 3 is formed.

Next, the unnecessary tungsten silicide layer 7
Are removed by RIE to complete the semiconductor device according to the present embodiment (FIG. 10). Thus, as shown in FIG. 10, the AA cross section of FIG. 11C of the semiconductor device according to the present embodiment shows the semiconductor devices formed in the first embodiment and the second embodiment in the B region, respectively. , The drain electrode in the B region and the source electrode in the A region are formed of the AuGe / Au layer 2.
A ring oscillator can be easily formed by forming an inverter formed as the common electrode 13 connected by 2 and connecting it as shown in the plan view of FIG.

Also in this embodiment, by forming a thin gate electrode processing metal layer having etching resistance, it is possible to apply a flattened resist on the entire surface, so that the resist can be accurately applied. Can be patterned.

[0041]

As described above, according to the present invention, a flattened resist can be applied to the entire surface by forming a metal layer for processing a gate electrode, which has etching resistance and is thin. As a result, the resist can be accurately patterned, and the source resistance and the like can be reduced. Further, as compared with the conventional example, the thickness of the ohmic electrode can be increased to provide a structure with low contact resistance. In addition, since the gate, source, and drain metals can be laterally separated by the side etching of WSi, parasitic capacitance generated between the electrode metals can be reduced.

In this way, a Schottky gate FET having a T-type gate structure in which the gate electrode is easily connected to the source electrode or the drain electrode can be realized.

[Brief description of drawings]

FIG. 1 is a diagram (No. 1) showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a view (No. 2) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 3 is a view (No. 3) showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a view (No. 1) showing the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 5 is a diagram (No. 2) showing the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 6 is a view (No. 3) showing the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 7 is a view (No. 4) showing the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a view (No. 1) showing the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 9 is a diagram (No. 2) showing the method for manufacturing the semiconductor device according to the third embodiment of the present invention.

FIG. 10 is a view (No. 3) showing the method for manufacturing the semiconductor device according to the third embodiment of the invention.

FIG. 11 is a diagram illustrating a ring oscillator.

FIG. 12 is a diagram illustrating a structure and a problem of a conventional T-type gate electrode.

[Explanation of symbols]

 2 ... GaAs substrate 4 ... n-GaAs layer 6 ... Silicon oxide film 7 ... Tungsten silicide layer 8 ... T-type gate electrode 8a ... Arm portions 8b, 8c ... AuGe / Au layers 10, 11 ... Source electrode 12 ... Drain electrode 13 ... Common electrodes 14, 14a, 16 ... Resist 18 ... AuGe / Au layer 20 ... Resist 22 ... AuGe / Au layer

Claims (6)

[Claims] 1. A semiconductor substrate, an impurity diffusion layer formed on the semiconductor substrate, an insulating film formed on the impurity diffusion layer, and the impurity diffusion through a contact hole formed in the insulating film. Layer and Schottky junction, and a T-shaped gate electrode having an arm extending from the contact hole onto the insulating film so as to have a T-shaped cross section, and an ohmic contact on the impurity diffusion layer by opening the insulating film. A semiconductor device having a source electrode to be joined, and a drain electrode which is ohmic-joined to the impurity diffusion layer by opening the insulating film on the side opposite to the source electrode with respect to the T-type gate electrode. A semiconductor device, characterized in that an etching resistant conductive layer is formed on the upper part of the electrode so as to extend wider than the arm portion of the T-shaped gate electrode. 2. An impurity diffusion layer is formed on a semiconductor substrate, an insulating film is formed on the impurity diffusion layer to form a contact hole, and a metal layer for forming a gate electrode is formed on the entire surface. On the gate electrode forming metal layer, a thin gate electrode processing metal layer having a gate electrode pattern shape and having etching resistance to serve as a gate electrode processing mask is formed, and a resist is applied on the entire surface, Sources on the upper side of the metal layer for processing the gate electrode and on both sides of the metal layer for processing the gate electrode
The resist on the drain electrode formation planned region is removed and patterned, and the gate electrode forming metal layer and the silicon oxide film are side-etched using the gate electrode processing metal layer and the patterned resist as a mask. The first arm portion formed of the metal layer for forming a gate electrode, which protrudes from the contact hole onto the insulating film by etching away, and the protrusion over the first arm portion, which is wider than the first arm portion. A T-shaped gate electrode having a second arm portion formed of the metal layer for processing the gate electrode and forming a Schottky junction with the impurity diffusion layer is formed, and at the same time, a source / drain is formed on both sides of the T-shaped gate electrode. The impurity diffusion layer in the electrode formation planned region is exposed, and the source electrode and drain electrode formation metal layers are formed on the entire surface, Manufacturing of a semiconductor device, characterized in that by removing the resist, the source electrode and drain electrode forming metal layer on the resist is lifted off to form a source electrode and a drain electrode which make ohmic contact with the impurity diffusion layer. Method. 3. A semiconductor substrate, an impurity diffusion layer formed on the semiconductor substrate, an insulating film formed on the impurity diffusion layer, and the impurity diffusion via a contact hole formed in the insulating film. Layer and Schottky junction, and a T-shaped gate electrode having an arm extending from the contact hole onto the insulating film so as to have a T-shaped cross section, and an ohmic contact on the impurity diffusion layer by opening the insulating film. A semiconductor device having a source electrode to be joined, and a drain electrode which is ohmic-joined to the impurity diffusion layer by opening the insulating film on the side opposite to the source electrode with respect to the T-type gate electrode, wherein the source electrode or The drain electrode extends to an upper portion of the T-shaped gate electrode, and an end portion of the drain electrode is formed to be wider than one end of the arm portion of the T-shaped gate electrode. The semiconductor device according to. 4. An impurity diffusion layer is formed on a semiconductor substrate, an insulating film is formed on the impurity diffusion layer to open a contact hole, and a metal layer for forming a gate electrode is formed on the entire surface to form a source electrode or a drain. The gate electrode forming metal layer and the insulating film in one region of the electrode formation planned region are opened, and ohmic contact is made with the impurity diffusion layer exposed in the opened one region, and the gate electrode forming metal layer is formed. One of a source electrode and a drain electrode is formed by depositing a thin first metal layer extending to the upper gate electrode formation region, and a resist is applied on the entire surface to form a resist on the first metal layer and the source. The resist in the other region of the electrode or drain electrode formation planned region is removed and patterned, and the first metal layer and the patterned resist are used as a mask. Then, the metal layer for forming the gate electrode and the insulating film are side-etched and removed by etching to form an arm portion protruding from the contact hole onto the insulating film, and a Schottky junction with the impurity diffusion layer is formed. The second metal layer on the resist is formed by forming a T-type gate electrode, exposing the impurity diffusion layer in the other region at the same time, forming a second metal layer on the entire surface, and removing the resist. Is lifted off to form the other electrode of the drain electrode or the source electrode which makes ohmic contact with the impurity diffusion layer. 5. A semiconductor substrate, an impurity diffusion layer formed on the semiconductor substrate, an insulating film formed on the impurity diffusion layer, and first and second contact holes formed in the insulating film. Schottky junction with the impurity diffusion layer via the first and second T-types in which arms extend from the first and second contact holes onto the insulating film so as to have a T-shaped cross section. A gate electrode, first and second source electrodes that open the insulating film and make ohmic contact with the impurity diffusion layer, and the first and second gate electrodes with respect to the first and second T-type gate electrodes. A semiconductor device having first and second drain electrodes that open the insulating film on opposite sides of the source electrode and make ohmic contact on the impurity diffusion layer. First T type An etching resistant conductive layer is formed that extends over the arm portion of the gate electrode, the second source electrode extends to an upper portion of the second T-shaped gate electrode, and an end portion of the second source electrode extends to the second portion. A semiconductor device, wherein the T-shaped gate electrode is formed so as to extend beyond one end of the arm portion and is connected to the first drain electrode. 6. A first and second impurity diffusion layer is formed on a semiconductor substrate, and an insulating film is formed on the impurity diffusion layer.
Of the first source electrode or drain electrode formation region on the side of the first gate electrode formation region is formed by forming a contact hole in the gate electrode formation region of The gate electrode forming metal layer and the insulating film in the region of are opened, a thin metal layer is formed on the entire surface, and patterning is performed.
A second gate electrode processing metal layer having a gate electrode pattern shape and having etching resistance serving as a gate electrode processing mask is formed on the gate electrode formation metal layer of A first source electrode or a drain electrode that makes ohmic contact with the impurity diffusion layer exposed in the opened one region and extends to the first gate electrode formation planned region on the gate electrode formation metal layer. One electrode is formed, a resist is applied on the entire surface, and one electrode upper part of the first source electrode or drain electrode and the other region of the first source electrode or drain electrode formation region and the second region are formed. Of the resist on the upper part of the gate electrode processing metal layer and on the second source / drain electrode formation planned regions on both sides of the second gate electrode processing metal layer. By removing and patterning, using the one electrode of the first source electrode or the drain electrode, the second metal layer for processing the gate electrode and the patterned resist as a mask, the metal layer for forming the gate electrode and the metal layer for forming the gate electrode By etching away the insulating film while side-etching, an arm portion protruding from the contact hole onto the insulating film is formed, and the first and second T-type gate electrodes that form a Schottky junction with the impurity diffusion layer are formed. And at the same time exposing the impurity diffusion layer in the other region of the first source electrode or drain electrode formation planned region and the second source / drain electrode formation planned region, forming a metal layer on the entire surface, The metal layer on the resist is lifted off by removing the resist and ohmic-bonded to the impurity diffusion layer. The other electrode of the serial first drain electrode or the source electrode, and the second being connected to one electrode of the first drain electrode or the source electrode
One of the source electrode or the drain electrode and the other electrode of the second source electrode or the drain electrode are formed.