JPS6177365A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of cracks in patterns by heat treatment by a method wherein heat treatment is carried out after removal of the coat film over patterns except in the neighborhood of aperture patterns. CONSTITUTION:In the process of heat treatment after N<+> conductive layers 6 are ion-implanted to a GaAs substrate 4 by using the mask of a gate pattern 21 of conventional oxide film and covered with a plasma nitride film 23, the pattern periphery of an FET and the like is covered with a photo resist film and etched away to the halfway of a plasma nitride film 21 and an oxide film 22 by parallel electrode tyep dry etching with CF4 gas, thus removing the photo resist film until the plasma nitride film 23 comes to remain only in the periphery by covering said exposed conductive layers 6 of the GaAs substrate. Thereafter, heat treatment is carried out in hydrogen, and a similar manufacturing process to that of the conventional example is carried out, resulting in the completion of a MESFET.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a field effect transistor in which the distance between a gate part and a source and drain part is short and is formed in a self-aligned manner, The present invention relates to a method of manufacturing a semiconductor device by integrating effect transistors.

(Prior art and its problems) G11 8 semiconductor has a high electron mobility that is 5 to 6 times higher than that of 8i, and because it has a major feature of high speed, in recent years it has been used for ultra-high-speed integrated circuits. Research on applications to (IC) is actively being conducted.

Schittky barrier field effect transistor (hereinafter referred to as ME8FET) as an active element of GaAs IC
is high resistance GaA and n-type GaA on the substrate surface.

On the active layer is a gate electrode made of a metal.

Source and drain electrodes made of ohmic metal are provided on both sides of this gate electrode.

However, in such a structure, a surface depletion layer is generated on the surface of the G B A @ active layer between the open cut key ti electrode and the ohmic electrode due to disturbances in crystallinity and adsorption of gas, which impairs effective operation. As the layer becomes thinner, the active layer resistance between the gate and the source (source series resistance) increases, and the mutual conductance gm decreases. In order to reduce the influence of such a surface depletion layer, it is necessary to set the electrode spacing to 0.5 μm or less. However, such highly accurate alignment is not possible with a general alignment exposure device.

Therefore, as a method for manufacturing MB8FFiT using a self-alignment method, a method has been proposed in which an n+ conductive layer is formed in a self-alignment manner by ion implantation using the gate pattern as a mask. #12 Figures (a) to (f) are conventional MISFE
FIG. 2 is a cross-sectional view showing the order of steps for explaining an example of a method for manufacturing T.

First, as shown in FIG. 2(a), an n-type active layer 5 is formed on a semi-insulating GaAs substrate 4. Next, as shown in FIG. 2(b), a plasma-9ized film (with a thickness of 0
．． 15 μm), followed by high heat resisting resist 11 (thickness 0.8
μm), sputter-deposited oxide film 13 (thickness 0.3 μm)
Using the photoresist as a mask, parallel plate dry etching is performed using CF, 10H, and gas to form an opening for forming an ohmic part by etching up to the high heat resisting resist 11, and then using the remaining oxide film 13 as a mask, a cylinder is etched. After etching the highly heat-resistant resist 11 by several thousand oxides using oxygen gas using dry etching, the remaining oxide film 1
Using 3 as a mask, ions are implanted through the plasma nitride protective film to form an n-type conductive layer 6.

Next, as shown in FIG. 2(C), the entire surface is covered with a sputter-deposited oxide film 14 (thickness: 0.3 μm). next.

As shown in FIG. 2(d), when lightly etched with a buffered hydrofluoric acid solution, the sputter-deposited oxide film 14 attached to the side wall of the highly heat-resistant resist 11 is weak and quickly melts away.
When the high heat resistant resist is dissolved with a stripping solution and lifted off, a gate opening 15 that becomes a gate portion is created. Plasma nitride film 1
The crystallinity of the active layer 5 and the n-conducting layer 6 is restored by heat treatment using 2 as a protective film. Next, Figure 2 (e
), the plasma nitride film 12 is etched using a cylindrical dry etching CF4 gas using the oxide film 14 as a mask, and the active layer 5 is atomized. Next, as shown in Figure 2), an overlay gate electrode 1 is formed on the gate opening 15, and source and drain ohmic electrodes 2 and 3 are formed on the n-type conductive layer 6 to complete the MISFET.

In this manufacturing method, the gate metal maple electrode is formed after the ion-implanted layer is heat-treated, so there is no problem of gate metal diffusing into the active layer. However, the problem with the manufacturing method is that the chemical resistance of the sputter-deposited oxide film attached to the high-temperature resist is weak, so it is dissolved with hydrofluoric acid, then the gate is removed. Although the opening 15 is formed, wet etching using such selectivity, which is required for FBTl properties, has poor reproducibility and processing accuracy, and is not suitable for stable mass production. In addition, in the protective film ion implantation, in order to prevent the carrier temperature on the surface of the n-conducting layer from increasing and the drain withstand voltage FET saturation property to deteriorate, a highly heat-resistant resist 11 is applied several thousand times using 1x13 oxide as a mask.
Although side etching is performed, the accuracy of the gate opening 15 must be less than this.

However, in wet etching that utilizes such etching selectivity, when the etching time is shortened in order to make the gate opening accurate, the portion 7bX that is not lifted or
However, if the etching time is increased in order to ensure lift-off, the gate opening widens by =5-, the final gate length increases, and problems such as drain withstand voltage and drain conductance decrease occur. Furthermore, the boundaries of the crystalline film at the corners of the sputter-deposited oxide film are in the direction of microcracks, and the wall surface of the etched gate opening 15 is not vertical but oblique. When the underlying plasma nitride film is aggressively etched by cylindrical dry etching using the gate opening of this oxide film as a mask, the oxide film itself is also etched and spread, and the gate opening of the plasma nitride film becomes wider. Furthermore, if the etching time is increased in an attempt to ensure that no plasma treatment film remains in the gate opening, side etching occurs and the gate opening becomes wider.

As described above, as the process progresses, the gate opening becomes wider and at the same time the variation in gate length also increases. As a result, the final FET characteristics also vary widely,
Even if such a manufacturing method is applied to highly integrated circuits, desired excellent circuit characteristics cannot be obtained due to poor matching of device characteristics.

Therefore, the inventor of the present application has proposed a method for manufacturing M1138FET that can form high-concentration n-conducting layers that will become the gate electrode, source, and drain portions with high precision in patent application No. 1.
It has been filed under No. 1858-124003.

FIGS. 3(a) to 3(11) are cross-sectional views showing the order of steps for explaining the method of manufacturing a semiconductor device previously filed by the inventor of the present application.

First, as shown in FIG. 3(a), 8i ions are deposited on a high-resistance GaAl substrate 4 using a photoresist film as a mask at an acceleration voltage of 50 KeV and a dose of 15×10”cTIL−.
” to form an n-type operating layer 5. Next, the third
As shown in Figure (b), a silicon oxide film is grown in a vapor phase to a thickness of 1.0 μm on this substrate 4, and the oxide film is etched by parallel electrode dry etching using a photoresist film as a mask, and the gate length is 1. .0μm gate pattern 2
1 and a mask 22 covering the FIT peripheral area is formed. Next, as shown in FIG. 3(C), using these oxide film patterns 21 and 22 as masks, 8i io/ was applied at an accelerating voltage of 130 KeV.

A high concentration impurity layer 6 is formed by ion implantation at a dose of 7 x 10''an-''. Next, as shown in FIG. 3(d), the entire surface is covered with a plasma nitride film 23 having a thickness of 0.4 μm as a coating film, and heat treatment is performed at 800°C for 20 minutes in hydrogen to remove the active layer 5 and the highly concentrated conductive film. The crystallinity of layer 6 is restored □. Next, as shown in FIG. 3(e), a photoresist film 24 is coated to a thickness of 1.0 μm and dried at 180° C. for 30 minutes, so that the photoresist film 24 becomes smooth and the photoresist film 24 on the gate pattern 21 is Become thin. Next, as shown in FIG. 3(f), the entire surface is etched by parallel electrode type dry etching using CF4 gas to expose the gate pattern 21 of the oxide film. Next, as shown in FIG. 3 (fI), the remaining photoresist film 24
is removed using a stripping solution, and the oxide film 21 of the gate pattern is selectively removed using a buffered hydrofluoric acid solution to form the gate opening 25.
form. Next, as shown in FIG. 3(h), aluminum is deposited on the entire surface and side etched using a photoresist film as a mask to form an aluminum gate electrode l.
An opening is formed on the highly concentrated conductive layer 6 by etching and removing the plasma nitride film 23 using the photoresist film as a mask, depositing an ohmic metal AuGe-pt, and dissolving the photoresist film.
7 to 7, heat treated in hydrogen for 5 minutes at 480℃
By diffusing e into the high concentration conductive layer 6, the source and drain ohmic electrodes 2 and 3 are formed.
s M B 8 F E T is completed.

When ME8FET was actually manufactured using this manufacturing method, the following problems sometimes occurred.

It has a thickness of 1. θμ skin oxide film gate pattern 21
was covered with a plasma nitride film 23 with a thickness of 0.4 μm, and
When heat treatment was performed for 20 minutes at °C, cracks were sometimes generated in areas where the distance between patterns was as wide as 50 μm or more. The occurrence of this crack seems to be caused by the usage conditions of the plasma nitride film growth apparatus, but this is not constant. This crack also appears to have entered the lower oxide film 22, and when the lower oxide film 22 is removed after pattern reversal, G, A8 groups i/! On the surface of i4, there are deep grooves where more GaA substrate components have evaporated, corresponding to cracks.

In integrated circuits, multi-layer wiring is formed between such patterns, but if there are grooves, disconnections or leaks may occur at these stepped parts, resulting in a problem of poor integrated circuit yield. .

(Object of the Invention) The object of the present invention is to form a semiconductor device manufacturing method in which cracks do not occur between pattern lines due to heat treatment in the production of an MF3SFFiT integrated circuit in which a high concentration n conductive layer is formed by a self-aligned method of ion implantation. Our goal is to provide the following.

(Structure of the Invention) According to the present invention, a step of forming a patterned film having an opening pattern on a semiconductor substrate, a step of covering the exposed semiconductor substrate and the patterned film with a coating film, and a step of performing heat treatment are performed. There is obtained a method for manufacturing a semiconductor device comprising the step of removing the covering film on the pattern film other than the vicinity of the opening pattern and performing heat treatment.

(Principle of the present invention) Oxidation-1 with a thickness of 1.0 μH is applied to a GaAs substrate with a diameter of 50 nm.
〇- Grow a film (8io,) in hydrogen or nitrogen for 80min.
No cracks were observed even after heat treatment at 0°C for 20 minutes. However, when a 1.0 μm thick oxide film (8i0*) and a 0.15 μm thick plasma nitride film were grown on a GaAs substrate and heat treated at 800° C. for 20 minutes, many cracks occurred. Possible causes of cracks include the internal stress of the plasma nitride film due to thermal expansion and the difference in thermal expansion coefficient between the plasma nitride film and the oxide film.

Therefore, since cracks do not occur with only a 1.0 μm thick oxide film, a plasma nitride film is provided only around the exposed GaAs substrate, and the plasma nitride film is removed from other parts to reduce stress. Try to prevent cracks from forming.

(Example) Next, an embodiment of the present invention will be described with reference to the drawings.

The n+ conductive layer 6 is ion-implanted into the G, A, and substrate 4 using the woven film nokate pattern 21 of FIG. 3(d) showing a conventional example of the present inventor as a mask, and is covered with a plasma nitride film 23 and heat-treated. In the process, the periphery of the pattern such as FIT is covered with a photoresist film, and the plasma nitride film 21 and oxide film 2 are removed by parallel electrode reduction dry etching using CF4 gas.
The photoresist film is removed by etching to the middle of 2.

Then, as shown in FIGS. 1(a) and 1(b), the nine exposed GaAst substrates are exposed. Plasma nitride film 23 remains only at the periphery of conductive layer 6. In addition, in Figure 1, (
(a) is a top view, and (b) is a cross-sectional view. Thereafter, a heat treatment is performed at 800° C. for 20 minutes in hydrogen, and the same manufacturing process as in the conventional example is performed to complete the MISFET.

Here, no cracks occurred even when the width of the plasma attenuating film 230 left on the oxidized R22 from the edge of the FET pattern was about 10 μm. In other words, the alignment accuracy of the photoresist film patterning in the peripheral area may be very rough.

(Effects of the Invention) According to the present invention, the insulating film between patterns is not cracked due to heat treatment, and the semiconductor substrate can be maintained. As a result, deep sieves do not occur on the surface of the semiconductor substrate between patterns, and the yield of multilayer wiring can be improved.

Although the present invention has been particularly described as a method for manufacturing field effect transistors, there are not only transistors but also diodes, resistors, marks, and other parts on an integrated circuit board, and the present invention is also effective for these parts.

[Brief explanation of the drawing]

Figures 1 (!1) and (b) are a plan view and a cross-sectional view for explaining the heat treatment process of an embodiment of the present invention, and Figure 2 (a)
) to (f) are cross-sectional views shown in the order of steps to explain an example of the conventional manufacturing method of MFf81'ET, and FIG.
a) to (h) are cross-sectional views shown in the order of steps for explaining a method for manufacturing a semiconductor device, which was previously filed by the inventor of the present invention. 1... Gate electrode, 2... Source electrode, 3... Drain electrode, 4... Semiconductor substrate, 5... Impurity operation l -56...
iI! ii Dense anti-conductive layer, 11... High heat resistance resistor x
), 12... plasma nitride film, 13.14...
... Sputter deposited oxide film, 15 ... Gate opening, 21 ... Gate pattern, 22 ...
...Membrane in peripheral area, 23...Coating film, 24...
...1/cyst membrane, 25...Game rod 1 time ((1) (d) rod 2
surface

Claims (1)

[Claims] A method for manufacturing a semiconductor device comprising: forming a patterned film having an opening pattern on a semiconductor substrate; covering the exposed semiconductor substrate and the patterned film with a coating film; and performing heat treatment. 1. A method of manufacturing a semiconductor device, comprising removing the covering film on the pattern film other than those in the vicinity and performing heat treatment.