JPS6143484A - Formation of electrode in semiconductor device - Google Patents
Formation of electrode in semiconductor deviceInfo
- Publication number
- JPS6143484A JPS6143484A JP16670584A JP16670584A JPS6143484A JP S6143484 A JPS6143484 A JP S6143484A JP 16670584 A JP16670584 A JP 16670584A JP 16670584 A JP16670584 A JP 16670584A JP S6143484 A JPS6143484 A JP S6143484A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- mask layer
- window
- forming
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims abstract description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000001301 oxygen Substances 0.000 claims abstract description 4
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 230000002093 peripheral effect Effects 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 17
- 239000010409 thin film Substances 0.000 claims description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims 2
- 238000004380 ashing Methods 0.000 claims 1
- 238000000137 annealing Methods 0.000 abstract description 3
- 238000000206 photolithography Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 21
- 239000002184 metal Substances 0.000 description 18
- 229910052751 metal Inorganic materials 0.000 description 18
- 239000010408 film Substances 0.000 description 8
- 239000000470 constituent Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 235000001674 Agaricus brunnescens Nutrition 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体装置の電極の形成方法に係り、特に、
電界効果トランジスタ(FEIT)のゲート電極などに
用いられる「きのこ」形電極の形成方法の改良に関する
ものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method of forming an electrode of a semiconductor device, and in particular,
This invention relates to an improvement in the method of forming a "mushroom"-shaped electrode used as a gate electrode of a field effect transistor (FEIT).
第1図は横方同エツチングプロセスを用いた従来のきの
こ形電極の形成方法を説明するためにその主要段階にお
ける状態を示す断面図で、まず、第1図Aに示すようV
C1半導体基板(1)の上に互いに異質の第1の金属層
(2)および第2の金属層(3)を形成する。次に、第
1図Bに示すように、その上にレジストを塗布し、写真
食刻技術によってバター二/グを施してレジスト薄膜マ
スク(4)を形成する。つづいて、第1図Cに示すよう
に、このレジスト薄膜マスク(4)を介して第1の金属
層(2)および第2の金属層(3)にエツチングを施し
、第1の金属層パターン仇)および第2の金属!−ハタ
ーン(3a)を形成したのち、@1図りに示すように、
レジスト薄膜マスク(4)を除去する。そして、第1図
Eに示すように、第1の金属層パターン(2a)のエツ
チング速度に比べて第2の金属層パターン(3a)のエ
ツチング速度が非常に小さいか、またはまったくエツチ
ングでれないエツチング方式で第1の金属層パターン(
2a)に横方向エツチングを施して第1の金蛎電極M
(2b)を形成し、第2の金属層パターン(3a)とで
きのこ形電極が完成する。(5)はこの電極の半導体基
板(1)の表面との接触面で、その幅がLである。FIG. 1 is a cross-sectional view showing the state at the main stages to explain the conventional method of forming a mushroom-shaped electrode using the lateral etching process. First, as shown in FIG.
A first metal layer (2) and a second metal layer (3) which are different from each other are formed on a C1 semiconductor substrate (1). Next, as shown in FIG. 1B, a resist is applied thereon and butter-printed by photolithography to form a resist thin film mask (4). Subsequently, as shown in FIG. 1C, the first metal layer (2) and the second metal layer (3) are etched through this resist thin film mask (4) to form a first metal layer pattern. enemy) and the second metal! - After forming Hataan (3a), as shown in diagram @1,
Remove the resist thin film mask (4). Then, as shown in FIG. 1E, the etching speed of the second metal layer pattern (3a) is very low compared to the etching speed of the first metal layer pattern (2a), or the etching cannot be performed at all. The first metal layer pattern (
2a) is laterally etched to form the first metal electrode M.
(2b) is formed, and a second metal layer pattern (3a) and a mushroom-shaped electrode are completed. (5) is the contact surface of this electrode with the surface of the semiconductor substrate (1), and its width is L.
ところが、上述の従来の方法では、第1の金属層の横力
同エツチングによって電極幅L (FETのゲート?l
C極の場合にはゲート長)を決定しているが、この横方
向エツチングはエツチング速度の制御が困難で、半導体
基板相互間は勿論、同一基板内においても位置によって
エツチングのばらつきが大きい。However, in the conventional method described above, the electrode width L (FET gate?l
In the case of the C pole, the gate length) is determined, but it is difficult to control the etching rate in this lateral etching, and there are large variations in etching depending on the position not only between semiconductor substrates but also within the same substrate.
従って、F訂のゲート′la極の場合はそのゲーi・長
にばらつきを生じることになる。これは周知の、i:5
にFETの電気的特性、特にトランスコンダクタンスも
及び1j!1和ドレ・丁/颯流ID5i1に大きい影響
を与え再現性が悪くなる。Therefore, in the case of the gate 'la pole of the F version, the gate i length will vary. This is well known, i:5
The electrical characteristics of the FET, especially the transconductance and 1j! It has a great effect on the 1W Dore・Ding/Soryu ID5i1 and deteriorates reproducibility.
虹に、r′A方回工2ンチングの特殊(生によって、甫
1の金4 % j;・よひ第2の金属層に用いる金属の
4頑、並びにエツチング方法に伺約忙生じ、また工程も
よ准になり、ill 第9 b fミもむつかし〜八と
いう・入点がbっだ。In addition, we have been busy inquiring about the special type of metal used for the second metal layer as well as the etching method. The process was also very good, and Ill 9th b f mi was also difficult to 8, and the entry point was b.
この発明に以上のような点に鑑みてなされたもので、レ
ジストを2#1こ用いるのみで、2層金属層も、横方向
エッチンググaセスも用いることなく、単層なエツチン
グ方法できのこ形電極を形成でざる方法を提供中るもの
である。This invention was made in view of the above points, and it is possible to use a single-layer etching method using only 2 #1 resists, without using two metal layers, or lateral etching. The present invention provides a method that does not require the formation of shaped electrodes.
〔発明の?ミIJ1例〕
第2図はこの祐明の一実施例を説明するために、その主
要段階における状態を示す断面図で、まず第2図Aに示
すように半導体基板(1)の上に第1のレジスト+!
(6)を形成し、写真食刻技術によって幅L(1)窓(
7) (+−形成する0次に、第2図Bに示すように、
1″i;(ノラズマぶ囲気中でアニーリングするか、ま
たンよ高@酸素雰囲気中で1ンシングすることによつ?
、41のレジスト膜(6)の窓(7ンの周縁のエツジ
(8)に丸みをつける。次に第2図Cに示すように、窓
(7)の中を含めて第1のレジスト膜(6)の上に金属
層(9)を形成する。つついて、その上に42図りに示
すよって所要パン′−ンの錫2のレジスト膜αりを形成
(−1この第2のレジスト=q ucp tマスクとじ
てtaz図Eに示すように、金属層(9)にエツチング
を・施して金rA’FIt@C9n)を形成した後に、
第2図Fに示すように第1のレジスト膜(6)及び第2
゛のレジスト膜αりを除去してきのこ形金属電極(9a
)は完成する0
このきのこ形@極の形成方法はFETのゲート電極の形
成方法として好適であることは言う°までもあるまい。[Invention? 1 Example of Mi IJ] Figure 2 is a cross-sectional view showing the state at the main stages in order to explain one embodiment of this Yumei.First, as shown in Figure 2A, a 1 resist+!
(6) and formed a width L(1) window (
7) (+- form the 0th order, as shown in Figure 2B,
(By annealing in a Norazuma atmosphere or by annealing in a high oxygen atmosphere?
, round the edge (8) of the periphery of the window (7) of the resist film (6) of 41. Next, as shown in FIG. A metal layer (9) is formed on the metal layer (6).A resist film of tin 2 with the required breadth is formed thereon as shown in Figure 42 (-1 This second resist= After etching the metal layer (9) to form gold rA'FIt@C9n) as shown in Figure E with the q ucp t mask,
As shown in FIG. 2F, the first resist film (6) and the second
After removing the resist film α of ゛, a mushroom-shaped metal electrode (9a
) is completed 0 It goes without saying that this method of forming the mushroom-shaped @pole is suitable as a method of forming the gate electrode of an FET.
なお、上記実施例ではマスク材としてレジストを用いた
が、酸化シリコン(S 1O2)、窒化シリコン(Si
lN4)などの絶縁物を用いてもよく、また、′II&
極の構成材も単層の金4層に限らず、その他の導゛成体
/Vまたは導電体膜と絶縁膜との捗層構造の電極用層状
体であってもよい。更にd極は半導体基体の表面に直接
接するように形成するとは限らず、一層またはそれ以上
の絶縁薄膜を介して接するように形成してもよい。In the above example, a resist was used as a mask material, but silicon oxide (S1O2), silicon nitride (Si
Insulators such as lN4) may also be used;
The constituent material of the electrode is not limited to a single layer of four gold layers, but may be another conductive material/V or a layered material for electrodes having a layered structure of a conductive film and an insulating film. Furthermore, the d-pole is not necessarily formed so as to be in direct contact with the surface of the semiconductor substrate, but may be formed so as to be in contact with the surface of the semiconductor substrate via one or more insulating thin films.
以上説明し7tように、この発明の方法によ−1ば、1
図のエツチングのみで、しかも横方向エツチングという
特殊な方法を用いることなく、きのこ形電極を形成する
ことができる。従って、電極を構成する材料及びエツチ
ング方法についての1「1j約は殆んど解消し、電極の
形成は極めて容易になる。As explained above, according to the method of the present invention, -1
A mushroom-shaped electrode can be formed only by the etching shown in the figure, and without using the special method of lateral etching. Therefore, the 1"1j problem regarding the material and etching method for forming the electrode is almost eliminated, and the formation of the electrode becomes extremely easy.
また、第1のマスク層に形成する窓の寸法で電極幅(F
ETのゲート電極の場合はゲート長)が決められるので
、その再現性は極めて良好である。しかもその電極の幅
および形状を工程の途中において確認することができる
。更に電極構成材層のパターニングのためのエツチング
液またはガスなどは第1のマスク層の存在によって半導
体基板には接触せず、半導体基板表面に悪影響を与える
のも防止できる。In addition, the electrode width (F
In the case of an ET gate electrode, since the gate length is determined, the reproducibility is extremely good. Moreover, the width and shape of the electrode can be confirmed during the process. Furthermore, the presence of the first mask layer prevents the etching liquid or gas used for patterning the electrode constituent material layer from coming into contact with the semiconductor substrate, thereby preventing any adverse effects on the surface of the semiconductor substrate.
第1図は従来のきのこ形電極形成方法を説明するために
その主要段階における状態を示す断面図、第2図はこの
発明の一実施例を説明するためにその主要段階における
状態を示す断面図である。
図において、(1)は半導体基板、(6)は第1のマス
ク層(第1のレジスト膜) 、(7)は窓、(8)は窓
(7)の周縁部、(9)は電極構成材層(全屈層)、(
9a)は電極、αqは第2のマスク層(第2のレジスト
膜)である。
なお、図中同一符号は同一または相当部分を示ず0FIG. 1 is a sectional view showing the state at the main stage to explain a conventional mushroom-shaped electrode forming method, and FIG. 2 is a sectional view showing the state at the main stage to explain an embodiment of the present invention. It is. In the figure, (1) is the semiconductor substrate, (6) is the first mask layer (first resist film), (7) is the window, (8) is the periphery of the window (7), and (9) is the electrode. Constituent material layer (total flexural layer), (
9a) is an electrode, and αq is a second mask layer (second resist film). In addition, the same reference numerals in the figures do not indicate the same or equivalent parts.
Claims (4)
所望寸法の窓を開ける第1の工程、上記窓の周縁のエッ
ジ部に丸みをもたせる第2の工程、上記第2の工程を経
た窓の内部を含めて上記第1のマスク層の上に電極構成
材層を形成する第3の工程、上記電極構成材層の上に第
2のマスク層を形成し、これに上記窓の上記寸法より大
きくかつ上記窓の上を完全に覆うようにパターニングを
施す第4の工程、この第4の工程を経た上記第2のマス
ク層を介して上記電極構成材層にエッチングを施す第5
の工程及び上記第1のマスク層と第2のマスク層とを除
去する第6の工程を備えた半導体装置の電極形成方法。(1) A first step of forming a first mask layer on a semiconductor substrate and opening a window of a desired size therein, a second step of rounding the peripheral edge of the window, and the second step described above. a third step of forming an electrode component layer on the first mask layer including the inside of the window, forming a second mask layer on the electrode component layer; a fourth step of patterning the window so as to be larger than the above dimensions and completely cover the top of the window; a fourth step of etching the electrode component layer through the second mask layer that has undergone this fourth step; 5
and a sixth step of removing the first mask layer and the second mask layer.
工程において、酸素プラズマ雰囲気中でアッシングする
ことによつて上記第1のマスク層の窓の周縁のエッジ部
に丸みをもたせることを特徴とする特許請求の範囲第1
項記載の半導体装置の電極形成方法。(2) A photoresist material is used for the first mask layer, and in the second step, the edges of the windows of the first mask layer are rounded by ashing in an oxygen plasma atmosphere. Characteristic claim 1
A method for forming an electrode of a semiconductor device as described in 1.
工程において高温の酸素雰囲気中に所要時間放置するこ
とによつて、上記第1のマスク層の窓の周縁のエッジ部
に丸みをもたせることを特徴とする特許請求の範囲第1
項記載の半導体装置の電極形成方法。(3) By using a photoresist material for the first mask layer and leaving it in a high-temperature oxygen atmosphere for a required period of time in the second step, the edges of the windows in the first mask layer are rounded. Claim 1 characterized in that
A method for forming an electrode of a semiconductor device as described in 1.
て形成することを特徴とする特許請求の範囲第1項ない
し第3項のいずれかに記載の半導体装置の電極形成方法
。(4) The method for forming electrodes of a semiconductor device according to any one of claims 1 to 3, wherein the first mask layer is formed on the semiconductor substrate with an insulating thin film interposed therebetween.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16670584A JPS6143484A (en) | 1984-08-07 | 1984-08-07 | Formation of electrode in semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16670584A JPS6143484A (en) | 1984-08-07 | 1984-08-07 | Formation of electrode in semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6143484A true JPS6143484A (en) | 1986-03-03 |
Family
ID=15836228
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16670584A Pending JPS6143484A (en) | 1984-08-07 | 1984-08-07 | Formation of electrode in semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6143484A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0538376U (en) * | 1991-10-25 | 1993-05-25 | シーケーデイ株式会社 | Roller pump for fluid supply |
JPH06260509A (en) * | 1993-03-03 | 1994-09-16 | Nec Corp | Method of manufacturing semiconductor device |
JPH07120280A (en) * | 1993-10-20 | 1995-05-12 | Gakunan Koki Kk | Metering apparatus for used paint in paint marker for road marking |
-
1984
- 1984-08-07 JP JP16670584A patent/JPS6143484A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0538376U (en) * | 1991-10-25 | 1993-05-25 | シーケーデイ株式会社 | Roller pump for fluid supply |
JPH06260509A (en) * | 1993-03-03 | 1994-09-16 | Nec Corp | Method of manufacturing semiconductor device |
JPH07120280A (en) * | 1993-10-20 | 1995-05-12 | Gakunan Koki Kk | Metering apparatus for used paint in paint marker for road marking |
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