JPH06104680A - Surface acoustic wave element - Google Patents
Surface acoustic wave elementInfo
- Publication number
- JPH06104680A JPH06104680A JP27809692A JP27809692A JPH06104680A JP H06104680 A JPH06104680 A JP H06104680A JP 27809692 A JP27809692 A JP 27809692A JP 27809692 A JP27809692 A JP 27809692A JP H06104680 A JPH06104680 A JP H06104680A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- acoustic wave
- idt
- surface acoustic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は表面弾性波素子に係り、
特に半導体基板上の圧電薄膜を利用した表面弾性波(S
AW)コンボルバ等に好適な素子において、半導体基板
表面の、入力くし型電極(以下IDTと記す)に対向し
た部分に下部電極を設けた構成の改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface acoustic wave device,
In particular, surface acoustic waves (S
AW) Concerning an element suitable for a convolver or the like, the present invention relates to an improvement of a structure in which a lower electrode is provided on a portion of a semiconductor substrate surface facing an input comb-shaped electrode (hereinafter referred to as IDT).
【0002】[0002]
【従来の技術】ZnO/SiO2/Si構造を有する従
来のSAWコンボルバの断面図を図2に示す。同図で、
1は基板電極、2はn/n+Siエピタキシャル基板、
3はSi熱酸化膜、5はZnO膜層、6は出力電極、7
a,7bはIDT、4は金属薄膜層から成るIDT下部
電極である。このIDT下部電極4は、次の2つの目的
を以って設けられている。 (i)IDT7a,7bに印加された入力信号の一部が
基板2のn−Si層に漏れるのを、このIDT下部電極
4でシールドすることによって防ぐ。これにより、結果
的に出力電極6からの出力の雑音を低減できる。 (ii)このIDT下部電極4の導入によりSAWコンボ
ルバの電気機械結合定数k2が理論的に大きくなり、コ
ンボルバの入力効率を高めることができる。このIDT
下部電極4としては、数十ないし数百nmの膜厚の金属
膜、例えばSiO2との密着性の良いAl薄膜等が多く
使われている。 2. Description of the Related Art A sectional view of a conventional SAW convolver having a ZnO / SiO 2 / Si structure is shown in FIG. In the figure,
1 is a substrate electrode, 2 is an n / n + Si epitaxial substrate,
3 is a Si thermal oxide film, 5 is a ZnO film layer, 6 is an output electrode, 7
Reference numerals a and 7b are IDTs, and 4 is an IDT lower electrode composed of a metal thin film layer. The IDT lower electrode 4 is provided for the following two purposes. (I) A part of the input signal applied to the IDTs 7a and 7b is prevented from leaking to the n-Si layer of the substrate 2 by shielding with the IDT lower electrode 4. As a result, the noise of the output from the output electrode 6 can be reduced. (Ii) By introducing the IDT lower electrode 4, the electromechanical coupling constant k 2 of the SAW convolver is theoretically increased, and the input efficiency of the convolver can be increased. This IDT
As the lower electrode 4, a metal film having a film thickness of several tens to several hundreds nm, for example, an Al thin film having good adhesion with SiO 2 is often used.
【0003】[0003]
【発明が解決しようとする課題】しかしながら、このよ
うな構成のコンボルバを実際に作ろうとすると、ZnO
膜層5を、例えばスパッタ法で形成する際に、IDT下
部電極4の表面がSiO2表面のような平滑な面になっ
ていないため、IDT下部電極4の上はZnO膜層5の
成長に伴いヒロックが多数発生し、結果的に、IDT7
a,7bの下のZnO膜層5の結晶性が悪く大きなk2
が得られないという問題があった。However, when an attempt is made to actually manufacture a convolver having such a structure, ZnO
When the film layer 5 is formed by, for example, a sputtering method, the surface of the IDT lower electrode 4 is not a smooth surface such as a SiO 2 surface, so that the ZnO film layer 5 does not grow on the IDT lower electrode 4. As a result, many hillocks were generated, resulting in IDT7
ZnO film layer 5 under a and 7b has a poor crystallinity and a large k 2
There was a problem that could not be obtained.
【0004】本発明の目的は、IDT下部電極上でも、
ヒロックの少ない良質のZnO膜を得ることにより、k
2が大きく入力効率の高いSAWコンボルバ等に好適な
表面弾性波素子を得ることにある。It is an object of the present invention, even on an IDT bottom electrode,
By obtaining a high-quality ZnO film with few hillocks, k
It is to obtain a surface acoustic wave device suitable for a SAW convolver or the like having a large 2 and a high input efficiency.
【0005】[0005]
【課題を解決するための手段】上記目的を達成するた
め、本発明の表面弾性波は、表面の所定位置に形成され
た低抵抗層を有しているシリコン基板と、上記シリコン
基板上に形成された二酸化シリコン膜層と、上記二酸化
シリコン膜上に形成された酸化亜鉛膜層と、上記酸化亜
鉛膜層表面の前記低抵抗層に対応する位置に設けられた
くし型電極(IDT)と、から成ることを要旨とする。In order to achieve the above object, the surface acoustic wave of the present invention is formed on a silicon substrate having a low resistance layer formed at a predetermined position on the surface and on the silicon substrate. A silicon dioxide film layer, a zinc oxide film layer formed on the silicon dioxide film, and a comb-shaped electrode (IDT) provided at a position corresponding to the low resistance layer on the surface of the zinc oxide film layer. The point is to make it.
【0006】[0006]
【作用】シリコン基板内にIDT下部電極としての低抵
抗層を有しているので、この部分は平滑性が良く、その
上に良好な膜質の酸化亜鉛膜を形成できる。Since the low resistance layer as the IDT lower electrode is provided in the silicon substrate, this portion has good smoothness, and a zinc oxide film of good film quality can be formed thereon.
【0007】[0007]
【実施例】以下図面を参照して本発明の実施例を説明す
る。図1は本発明の一実施例の表面弾性波素子としての
SAWコンボルバ(d)とその製造工程(a〜d)を示
す。同図において図2と同一符号は同一または類似の部
分を示し、8a,8bは高濃度不純物拡散層、9はフォ
トレジストパターンである。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a SAW convolver (d) as a surface acoustic wave device according to an embodiment of the present invention and manufacturing steps (a to d) thereof. In the figure, the same reference numerals as those in FIG. 2 indicate the same or similar portions, 8a and 8b are high-concentration impurity diffusion layers, and 9 is a photoresist pattern.
【0008】まず、図1(a)に示すようにn/n+エ
ピタキシャルSi基板2の表面に熱酸化により、例えば
50nmの厚さの酸化膜3を形成し、フォトリソ工程によ
りIDT下部電極のレジストパターン9をこの酸化膜3
上に形成する。次にイオン注入によりPhos+を例えば加
速電圧180keVで2×1015cm-2注入する。First, as shown in FIG. 1A, an oxide film 3 having a thickness of, for example, 50 nm is formed on the surface of an n / n + epitaxial Si substrate 2 by thermal oxidation, and a resist for an IDT lower electrode is formed by a photolithography process. Pattern 9 on this oxide film 3
Form on top. Next, by ion implantation, Phos + is implanted at 2 × 10 15 cm −2 at an acceleration voltage of 180 keV, for example.
【0009】次に、図1(b)に示すようにレジストパ
ターン9を除去し、アニール処理をした後、酸化膜3を
全て除去する。これにより基板2のnエピタキシャルS
i層中に低抵抗のn+層を形成して下部電極として構成
する。Next, as shown in FIG. 1B, the resist pattern 9 is removed, an annealing process is performed, and then the oxide film 3 is entirely removed. As a result, the n-epitaxial S of the substrate 2 is
A low resistance n + layer is formed in the i layer to form a lower electrode.
【0010】次に、図1(c)の如く、図1(b)のウ
エハを熱酸化し、表面に例えば100nmの厚さの熱酸化
膜3’を形成する。この段階で非常に平滑な表面が得ら
れている。そして、ウエハ裏面の酸化膜を除去し、基板
電極1を形成する。Next, as shown in FIG. 1C, the wafer shown in FIG. 1B is thermally oxidized to form a thermal oxide film 3'having a thickness of 100 nm on the surface. A very smooth surface is obtained at this stage. Then, the oxide film on the back surface of the wafer is removed to form the substrate electrode 1.
【0011】次に、図1(d)のようにこの基板上にZ
nO膜層5を、例えばスパッタ法で〜5μmの厚さに堆
積する。その後、表面の入出力電極6,7a,7bを形
成する。Next, as shown in FIG. 1D, Z is formed on this substrate.
The nO film layer 5 is deposited by sputtering, for example, to a thickness of ˜5 μm. After that, the input / output electrodes 6, 7a, 7b on the surface are formed.
【0012】なお、ここでは一例としてIDT下部電極
をn+−Si層にした場合について述べたが、例えば、
B+等を拡散してp+−Si層とすることもでき、高濃度
不純物拡散層から成る低抵抗層のIDT下部電極を設け
ればよい。Although the case where the IDT lower electrode is an n + -Si layer is described here as an example, for example,
It is also possible to diffuse B + or the like to form a p + -Si layer, and a low resistance layer IDT lower electrode composed of a high concentration impurity diffusion layer may be provided.
【0013】このようにしてIDT下部電極としてSi
エピタキシャル層n中に高濃度不純物拡散層を設けたた
めに、ZnO膜層5形成前の基板表面の平滑性が著しく
向上し、これによりIDT下部電極上でも他の領域と変
わらない良好な膜質のZnO膜層が形成できるようにな
り、IDT部のk2も大きくなりコンボルバの入力効率
が向上した。Thus, Si is used as the IDT lower electrode.
Since the high-concentration impurity diffusion layer is provided in the epitaxial layer n, the smoothness of the substrate surface before the formation of the ZnO film layer 5 is remarkably improved, and as a result, ZnO having a good film quality which is the same as other regions on the IDT lower electrode is also obtained. The film layer can be formed, the k 2 of the IDT section is increased, and the input efficiency of the convolver is improved.
【0014】[0014]
【発明の効果】以上説明したように本発明によれば、I
DT下部電極上でも良質のZnO膜を形成でき、k2が
大きく、入力効率の高い表面弾性波素子を得ることがで
きる。As described above, according to the present invention, I
A good quality ZnO film can be formed on the DT lower electrode, and a surface acoustic wave device having a large k 2 and a high input efficiency can be obtained.
【図面の簡単な説明】[Brief description of drawings]
【図1】本発明によるSAWコンボルバの一実施例とそ
の製造工程を示す概略図である。FIG. 1 is a schematic view showing an example of a SAW convolver according to the present invention and a manufacturing process thereof.
【図2】従来のSAWコンボルバを示す概略図である。FIG. 2 is a schematic diagram showing a conventional SAW convolver.
1 基板電極 2 n/n+Siエピタキシャル基板 3 Si酸化膜 4 IDT下部電極(金属薄膜層) 5 ZnO膜層 6 出力電極 7 入力電極 8 IDT下部電極(高濃度不純物拡散層) 9 フォトレジストパターン1 substrate electrode 2 n / n + Si epitaxial substrate 3 Si oxide film 4 IDT lower electrode (metal thin film layer) 5 ZnO film layer 6 output electrode 7 input electrode 8 IDT lower electrode (high concentration impurity diffusion layer) 9 photoresist pattern
Claims (4)
有しているシリコン基板と、 上記シリコン基板上に形成された二酸化シリコン膜層
と、 上記二酸化シリコン膜上に形成された酸化亜鉛膜層と、 上記酸化亜鉛膜層表面の前記低抵抗層に対応する位置に
設けられたくし型電極と、 から成ることを特徴とする表面弾性波素子。1. A silicon substrate having a low resistance layer formed at a predetermined position on the surface, a silicon dioxide film layer formed on the silicon substrate, and zinc oxide formed on the silicon dioxide film. A surface acoustic wave device comprising: a film layer; and a comb-shaped electrode provided at a position corresponding to the low resistance layer on the surface of the zinc oxide film layer.
成ることを特徴とする請求項1に記載の表面弾性波素
子。2. The surface acoustic wave device according to claim 1, wherein the low resistance layer comprises a high concentration impurity diffusion layer.
キシャル基板であり、そのSiエピタキシャル層中に前
記高濃度不純物拡散層が形成されていることを特徴とす
る請求項2に記載の表面弾性波素子。3. The surface acoustic wave according to claim 2, wherein the silicon substrate is an n / n + Si epitaxial substrate, and the high-concentration impurity diffusion layer is formed in the Si epitaxial layer. element.
れ、その間の前記酸化亜鉛膜層表面に出力電極を設けた
ことを特徴とする請求項1に記載の表面弾性波素子。4. The surface acoustic wave device according to claim 1, wherein a pair of the resistance layer and the comb-shaped electrode are provided, and an output electrode is provided on the surface of the zinc oxide film layer between them.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27809692A JPH06104680A (en) | 1992-09-21 | 1992-09-21 | Surface acoustic wave element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27809692A JPH06104680A (en) | 1992-09-21 | 1992-09-21 | Surface acoustic wave element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH06104680A true JPH06104680A (en) | 1994-04-15 |
Family
ID=17592584
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27809692A Pending JPH06104680A (en) | 1992-09-21 | 1992-09-21 | Surface acoustic wave element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06104680A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10938367B2 (en) * | 2016-03-31 | 2021-03-02 | Qorvo Us, Inc. | Solidly mounted layer thin film device with grounding layer |
US11588466B2 (en) | 2016-01-22 | 2023-02-21 | Qorvo Us, Inc. | Guided wave devices with selectively loaded piezoelectric layers |
-
1992
- 1992-09-21 JP JP27809692A patent/JPH06104680A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11588466B2 (en) | 2016-01-22 | 2023-02-21 | Qorvo Us, Inc. | Guided wave devices with selectively loaded piezoelectric layers |
US10938367B2 (en) * | 2016-03-31 | 2021-03-02 | Qorvo Us, Inc. | Solidly mounted layer thin film device with grounding layer |
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