JPH01120831A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the dispersion of chip thicknesses and simplify a relating process, by making each semiconductor layer grow on a substrate where an intermediate layer which can be etched selectively is interposed between lower and upper semiconductor layers and removing the lower semiconductor layer after etching the intermediate layer selectively. CONSTITUTION:After forming source, drain, and gate electrodes 6, 7, and 8 on an operating layer 5, an intermediate layer 2 consisting of AlxGa1-xAs is etched selectively to isolate a lower GaAs layer 1a. After isolating it, holes are made at a lower part of the source electrode 6 as well as at the rear of the GaAs layer 1b that acts as a substrate end AU plating 9 is carried out at the foregoing hole and the whole rear of the upper GaAs layer 1b. That is to day, as the thickness of a chip is controlled by removing layers located below the intermediate layer 2, its thickness of the chip comes to 3O+ or -3mum with the exception of Au plating and its dispersion decreases by less than one- half and the dispersion of thermal resistance values decreases by less than one-half as well in comparison with those of conventional ones.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a method of manufacturing a semiconductor device in which chip thickness can be easily controlled.

(Prior Art) FIGS. 2(a), 2(b), and 2(C) are diagrams showing an example of the manufacturing process of a conventional GaAs device.

In these figures, 3 is a GaAs substrate, 4 is a buffer layer, 5 is an active layer, 6 is a source electrode, 7 is a drain electrode,
8 is a gate electrode.

Conventionally, the chip thickness of such a GaAs device is as follows:
As shown in FIG. 2(a), a buffer layer 4. After growing the active layer 5 and then forming a source electrode 6, a drain electrode 7 and a gate electrode 8 as shown in FIG. 2(b), the GaAs substrate 3 itself is lapped and further chemical etched. (Fig. 2 (C)).

(Problems to be Solved by the Invention) In the conventional semiconductor device manufacturing method as described above, the accuracy of the chip thickness is about ±10 μm, and the variation in the thermal resistance value of the chip is large. In particular, in via-hole structures that require through-holes to be formed on the top and bottom surfaces of the chip, the size of the through-holes depends on the chip thickness, being smaller in thicker areas and larger in thinner areas. However, there was a problem in that the source inductance varied.

The present invention was made to solve these problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce variations in chip thickness and simplify the process.

[Means for solving problems]

A method for manufacturing a semiconductor device according to the present invention uses a substrate in which an intermediate layer that can be selectively etched is interposed between a lower semiconductor layer and an upper semiconductor layer, and includes the steps of growing each semiconductor layer on this substrate, and selecting the intermediate layer. The method includes a step of performing etching to remove the lower semiconductor layer.

[Effect]

In this invention, the chip thickness is determined by the sum of the thickness of the upper semiconductor layer and the thickness of each semiconductor layer grown on the upper semiconductor layer.

〔Example〕

FIGS. 1(a), (b), and (C) are diagrams for explaining an embodiment of the method for manufacturing a semiconductor device of the present invention. Here, the semiconductor device is a via-hole type high-power GaAsF
ET is shown.

In these figures, FIGS. 2(a) and (b).

The same symbols as in (C) indicate the same things, 1 is the substrate, 1a
is the lower GaAs layer, 1b is the upper GaAs layer, 2 is Aj2
．． Intermediate layer consisting of Ga1-, As (for example, X≧0.4)
It is.

Next, the manufacturing process will be explained.

For example, when the final chip thickness is 30 μm, first, as shown in FIG. 1(a), the active layer 5 is 0.5 μm thick, the buffer layer 4 is 1.0 μm thick, and the upper GaAsF 11b is 28 μm thick.
A 5 μm thick square is prepared.

Next, as shown in FIG. 1(b), a source electrode 6, a drain electrode 7, and a gate electrode 8 are formed on the active layer 5, and then, as shown in FIG. 1(c), AJ! , Gap-xA
By selectively etching the intermediate layer 2 made of s, the lower Ga
The As layer 1a is separated.

Then, after separation, a hole is made under the source electrode ti 6 and on the back side of the upper GaAs layer 1b serving as the substrate, and Au plating 9 is applied to the hole and the entire back surface of the upper GaAs layer 1b to complete the device.

That is, in this invention, since the chip thickness is controlled by removing the intermediate layer 2 and below, the Au plating 9
The chip thickness is 30 μm±3 μm, excluding the chip thickness, and the variation is less than half of the conventional value, and the variation in thermal resistance value is also less than half of the conventional value. Further, as the thickness variation is reduced, the through hole variation is also reduced, the source inductance becomes uniform, and the uniformity of device performance is also improved.

In addition, although the FET is shown as a semiconductor device in the above embodiment, the present invention is not limited to this, and it goes without saying that it can be applied to other semiconductor devices that require control of chip thickness in the manufacturing process. Nor.

(Effects of the Invention) As described above, the present invention uses a substrate in which an intermediate layer that can be selectively etched is interposed between a lower semiconductor layer and an upper semiconductor layer, and includes a step of growing each semiconductor layer on this substrate, and a step of growing each semiconductor layer on this substrate, and Since the chip thickness is determined by the sum of the thickness of the upper semiconductor layer and the thickness of each semiconductor layer grown on the upper semiconductor layer, lapping and etching are performed to remove the lower semiconductor layer. This has the effect that the chip thickness can be controlled through a simple process without having to do much.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is a diagram for explaining a conventional method for manufacturing a semiconductor device. In the figure, 1 is a substrate, 1a is a lower GaAS layer, 1b is an upper GaAs layer, 2 is an intermediate layer, 4 is a buffer layer, 5 is an active layer, 6 is a source electrode, 7 is a drain electrode, 8 is a gate electrode, 9 is Au plating. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2

Claims (1)

[Claims] Using a substrate in which an intermediate layer that can be selectively etched is interposed between a lower semiconductor layer and an upper semiconductor layer, growing each semiconductor layer on this substrate, and selectively etching the intermediate layer to remove the lower semiconductor layer. A method for manufacturing a semiconductor device, comprising the steps of: