JPH01166541A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH01166541A JPH01166541A JP32399287A JP32399287A JPH01166541A JP H01166541 A JPH01166541 A JP H01166541A JP 32399287 A JP32399287 A JP 32399287A JP 32399287 A JP32399287 A JP 32399287A JP H01166541 A JPH01166541 A JP H01166541A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- wiring
- metal
- semiconductor device
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 3
- 239000002184 metal Substances 0.000 claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000010409 thin film Substances 0.000 claims abstract description 20
- 239000010408 film Substances 0.000 claims abstract description 14
- 239000000463 material Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 6
- 229920000620 organic polymer Polymers 0.000 claims 3
- 239000012212 insulator Substances 0.000 claims 2
- 239000004642 Polyimide Substances 0.000 claims 1
- 230000000737 periodic effect Effects 0.000 claims 1
- 229920001721 polyimide Polymers 0.000 claims 1
- 229920000642 polymer Polymers 0.000 claims 1
- 229910052582 BN Inorganic materials 0.000 abstract description 6
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 abstract description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 238000004380 ashing Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000007747 plating Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 239000012779 reinforcing material Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002825 nitriles Chemical class 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に係り、特に超高速動作に好適な金
属配線構造およびその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a metal wiring structure suitable for ultra-high-speed operation and a method for manufacturing the same.
半導体装置の金属配線において、配線部分の寄生容量を
減少させることが、半導体素子の高速動作に有利であり
(例えばT、Enoki et al:エレクトロニツ
クスレターズ(ELECTRONIC:S LETTE
R5) 。In the metal wiring of a semiconductor device, reducing the parasitic capacitance of the wiring part is advantageous for high-speed operation of the semiconductor element (for example, T. Enoki et al.: ELECTRONIC: S LETTE).
R5).
van、22. Nn2. p 68(1986)に記
載され゛ている)、その具体的な方法として、いわゆる
エアーブリッジ方式が有効である事は公知である(例え
ばT、Andrada :ソリッド・ステート・テクノ
ロジー(Solid 5tate Technolog
y)誌1985年版第2号、P199に記載されている
)。van, 22. Nn2. It is known that the so-called air bridge method is effective as a specific method (for example, T. Andrada: Solid State Technology).
y) Magazine, 1985 Edition No. 2, P199).
上記従来技術では、空中に金属配線を形成するために例
えば最低1.5μm程度の厚さが必要とされ、かつ所定
の部分に選択的に形成することが必要であるため、通常
メツキ法が用いられていた。In the above-mentioned conventional technology, in order to form metal wiring in the air, a thickness of, for example, at least 1.5 μm is required, and it is necessary to selectively form it in a predetermined portion, so a plating method is usually used. It was getting worse.
メツキ法は、周知のように工業技術的に量産性が低く、
原料の使用効率が低いので、特に金などを使用する場合
コストが高くなる。さらに通常メツキ浴にはシアン化合
物が用いられ人体に有害な事が懸念される等の問題があ
った。As is well known, the Metsuki method has low industrial productivity and
Since raw materials are used inefficiently, costs are high, especially when gold is used. Furthermore, plating baths usually use cyanide compounds, which pose problems such as concerns that they may be harmful to the human body.
本発明品目的は、メツキ法を使用することなく。The purpose of the present invention is to eliminate the need for the Metsuki method.
工業的に確立されたドライエツチング等の手法を用いて
エアーブリッジ配線を実現する半導体装置の構造を提供
することにある。The object of the present invention is to provide a structure of a semiconductor device that realizes air bridge wiring using an industrially established method such as dry etching.
上記目的は、金属配線の機械的強度を確保し、かつ配線
の寄生容量を増加させないために、金属配線の上部に配
線を補強するための薄膜材料を設置した構造とすること
によって達成される。The above object is achieved by providing a structure in which a thin film material for reinforcing the metal wiring is provided on top of the metal wiring in order to ensure the mechanical strength of the metal wiring and to prevent the parasitic capacitance of the wiring from increasing.
配NiA層上に形成された補強用薄膜により、配線層の
厚さが1μm以下であっても下層に形成された半4体素
子あるいは他の配線層との間の空気絶縁が可能となり、
従来のようにAuメツキ等の微細配線が困難な方法をと
る必要がなくなる。The reinforcing thin film formed on the interconnection NiA layer enables air insulation between the half-quad elements formed below or other interconnection layers even if the interconnection layer has a thickness of 1 μm or less.
There is no need to use methods that are difficult for fine wiring, such as Au plating, as in the past.
以下1本発明の一実施例を第1図により説明する1本実
施例は、Q a A s単結晶を用いたショットキー接
合電界効果トランジスタのソース電極103への配線を
エアーブリッジで実現した例を示している0通常の方法
によりG a A s単結晶基板101に、不純物拡散
層102.ソースおよびドレイン電極103’、、ゲー
ト電極104により電界効果トランジスタ(MH3FE
T)を形成した1次に素子全体をCVD法によるS i
Oz膜105により被覆した後、通常のホトリソグラ
フィ法、およびドライエツチング法により、ソース電極
103上の所定箇所の5iOz105を選択的に除去し
た。ついでSingの加工に用いたホトレジスト(図示
せず)を除去することなく、全面に真空蒸着法によりM
o −A u −M oそれぞれ膜厚110−700
−10nの3層構造からなる金属配線107を被着した
。さらにスパッタリング法によりBN(窒化ホウ素)膜
108を厚さ11000n形成した。次に通常のホトリ
ソグラフィにより所定の配線パターンを形成し、フッ素
系プラズマによりBNおよび上側のMo薄膜を選択的に
加工した。An embodiment of the present invention will be explained below with reference to FIG. 1. This embodiment is an example in which wiring to the source electrode 103 of a Schottky junction field effect transistor using Q a A s single crystal is realized by an air bridge. 0 Impurity diffusion layers 102 . The source and drain electrodes 103', gate electrode 104 form a field effect transistor (MH3FE).
The entire primary element formed with T) is Si
After covering with the Oz film 105, the 5iOz 105 at predetermined locations on the source electrode 103 was selectively removed by normal photolithography and dry etching. Next, without removing the photoresist (not shown) used for Sing processing, M was applied to the entire surface by vacuum evaporation.
o -A u -Mo each film thickness 110-700
A metal wiring 107 having a three-layer structure of -10n was deposited. Further, a BN (boron nitride) film 108 with a thickness of 11000 nm was formed by sputtering. Next, a predetermined wiring pattern was formed by ordinary photolithography, and the BN and the upper Mo thin film were selectively processed by fluorine-based plasma.
次いでArイオンミリング法によりAu1l膜を加工し
、更に下側のMo膜をフッ素系プラズマエッチで加工し
、金属配線の形成1を完了した0次にバレル型プラズマ
アッシング装置を用いて、金属配線およびS i Oz
薄膜のパターン形成に用いたホトレジスト膜を同時にア
ッシング除去した。その結果、第1図に断面構造を示し
たように、例えば106の部分に空洞部を持つエアーブ
リッジ配線を形成することができた。ここでBN薄膜は
周知のように機械的強度が強いので薄膜の金属配線を変
形することなく空中に支持することができた。Next, the Au1L film was processed by Ar ion milling method, and the lower Mo film was further processed by fluorine-based plasma etching, and metal wiring and S i Oz
At the same time, the photoresist film used to form the thin film pattern was removed by ashing. As a result, as shown in the cross-sectional structure in FIG. 1, it was possible to form an air bridge wiring having a hollow portion, for example, at a portion 106. As is well known, the BN thin film has strong mechanical strength, so the thin film metal wiring could be supported in the air without being deformed.
なお本実施例ではG a A s基板を用いた半導体装
置について説明したが、本発明がInP他種他種化合物
半導体装置、あるいはSi半導体装置において超高速性
を追求する場合に同様に有効であることは発明の原理か
ら明白である。また、配線金属についても、素子の使用
箇所によりAQ、W。Although this embodiment describes a semiconductor device using a GaAs substrate, the present invention is equally effective in pursuing ultrahigh speed in InP and other compound semiconductor devices, or in Si semiconductor devices. This is clear from the principle of the invention. Also, regarding wiring metal, AQ and W depending on where the element is used.
Ni等を含む種々の材料を選択可能である。また配線金
属の補強材としてはBNの他にSiN。Various materials can be selected including Ni and the like. In addition to BN, SiN can be used as a reinforcing material for wiring metal.
5iOz等通常半導体プロセスに用いられる材料であっ
ても良いことを耐雷する。さらにつけ加えるならば、補
強材の形状は、金属配線層と同一パターンである必要は
ない。It can be made of a material commonly used in semiconductor processes, such as 5iOz, to provide lightning resistance. In addition, the shape of the reinforcing material does not need to be the same pattern as the metal wiring layer.
また本実施例においては配線層としてM o −A u
−M oを用いたが、さらに機械的強度の弱いBaY
CuO系などの超電導配線を用いる場合にも本発明は有
効であることは勿論である。Furthermore, in this embodiment, the wiring layer is M o -A u
-Mo was used, but BaY, which has even weaker mechanical strength,
Of course, the present invention is also effective when using superconducting wiring such as CuO-based wiring.
本発明によれば、エアーブリッジ配線をメツキによらず
形成することができるので、生産性を向上でき、また従
来法よりも精度よく微細配線を形成することができるの
で、半導体素子の信頼性向上、生産性向上ひいてはコス
ト低減に著しい効果がある。According to the present invention, since air bridge wiring can be formed without plating, productivity can be improved, and since fine wiring can be formed with higher precision than conventional methods, reliability of semiconductor devices can be improved. This has a significant effect on improving productivity and reducing costs.
第1図は本発明の一実施例のエアーブリッジ配線材G
a A s電界効果トランジスタの断面構造図である。
101・・・G a A s基板、102・・・不純物
拡散層。Figure 1 shows an air bridge wiring material G according to an embodiment of the present invention.
FIG. 2 is a cross-sectional structural diagram of an aAs field effect transistor. 101...G a As substrate, 102... Impurity diffusion layer.
Claims (1)
れた金属配線を有する半導体装置において、上記金属配
線の上に薄膜を設置したことを特徴とする半導体装置。 2、特許請求範囲第1項記載の半導体装置において、上
記薄膜材料は絶縁物である半導体装置。 3、特許請求範囲第1項記載の半導体装置において、上
記金属配線と上記薄膜とが、上記基板に平行な面内で同
一形状をしている半導体装置。 4、特許請求範囲第3項記載の半導体装置において、上
記金属配線の厚さは1μm以下である半導体装置。 5、特許請求範囲第3項記載の半導体装置において、該
金属配線に元素周期律表 I b、IIIbおよびVIa族のう
ち少なくとも一つの元素が含まれていることを特徴とす
る半導体装置。 6、特許請求範囲第2項記載の半導体装置において、該
薄膜材料がSi、B、N、Oからなる群より選ばれた少
なくとも1つの元素を含む絶縁物であることを特徴とす
る半導体装置。 7、特許請求範囲第2項記載の半導体装置において、該
薄膜材料がポリイミド系高分子であることを特徴とする
半導体装置。 8、半導体素子および金属層の少なくとも一方が形成さ
れた基板材料の上に、有機高分子膜を形成する工程と、
該有機高分子膜の定められた領域に上記半導体素子もし
くは上記金属層との電気的接続のための孔を開ける工程
と、該孔を含む全面に配線用金属薄膜を形成する工程と
、該配線用薄膜を補強する薄膜材料を被着する工程と、
該薄膜材料に所定の配線パターンを加工、形成する工程
と、加工された該薄膜材料をマスクとして上記配線用金
属薄膜を選択的に加工する工程と、上記有機高分子膜を
除去して基板材料と配線金属との間に空洞を形成する工
程を含むことを特徴とする半導体装置の製造方法。Claims: 1. A semiconductor device having a metal wiring insulated via air from a substrate on which a semiconductor element is formed, characterized in that a thin film is disposed on the metal wiring. 2. The semiconductor device according to claim 1, wherein the thin film material is an insulator. 3. The semiconductor device according to claim 1, wherein the metal wiring and the thin film have the same shape in a plane parallel to the substrate. 4. The semiconductor device according to claim 3, wherein the metal wiring has a thickness of 1 μm or less. 5. The semiconductor device according to claim 3, wherein the metal wiring contains at least one element from groups Ib, IIIb, and VIa of the periodic table of elements. 6. The semiconductor device according to claim 2, wherein the thin film material is an insulator containing at least one element selected from the group consisting of Si, B, N, and O. 7. The semiconductor device according to claim 2, wherein the thin film material is a polyimide polymer. 8. Forming an organic polymer film on the substrate material on which at least one of the semiconductor element and the metal layer is formed;
A step of forming a hole for electrical connection with the semiconductor element or the metal layer in a predetermined region of the organic polymer film, a step of forming a metal thin film for wiring on the entire surface including the hole, and a step of forming a metal thin film for wiring on the entire surface including the hole. a step of applying a thin film material to reinforce the thin film for use;
A step of processing and forming a predetermined wiring pattern on the thin film material, a step of selectively processing the metal thin film for wiring using the processed thin film material as a mask, and a step of removing the organic polymer film to form a substrate material. 1. A method of manufacturing a semiconductor device, the method comprising the step of forming a cavity between a metal interconnect and a metal interconnect.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32399287A JPH01166541A (en) | 1987-12-23 | 1987-12-23 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32399287A JPH01166541A (en) | 1987-12-23 | 1987-12-23 | Semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01166541A true JPH01166541A (en) | 1989-06-30 |
Family
ID=18160914
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32399287A Pending JPH01166541A (en) | 1987-12-23 | 1987-12-23 | Semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01166541A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6020215A (en) * | 1994-01-31 | 2000-02-01 | Canon Kabushiki Kaisha | Process for manufacturing microstructure |
JP2004514271A (en) * | 2000-07-12 | 2004-05-13 | モトローラ・インコーポレイテッド | Electronic components and manufacturing method |
-
1987
- 1987-12-23 JP JP32399287A patent/JPH01166541A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6020215A (en) * | 1994-01-31 | 2000-02-01 | Canon Kabushiki Kaisha | Process for manufacturing microstructure |
JP2004514271A (en) * | 2000-07-12 | 2004-05-13 | モトローラ・インコーポレイテッド | Electronic components and manufacturing method |
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