JPS6351679A - Semicondictor device - Google Patents
Semicondictor deviceInfo
- Publication number
- JPS6351679A JPS6351679A JP19607386A JP19607386A JPS6351679A JP S6351679 A JPS6351679 A JP S6351679A JP 19607386 A JP19607386 A JP 19607386A JP 19607386 A JP19607386 A JP 19607386A JP S6351679 A JPS6351679 A JP S6351679A
- Authority
- JP
- Japan
- Prior art keywords
- film
- titanium nitride
- gold
- layer
- tungsten silicide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 17
- 239000010931 gold Substances 0.000 claims abstract description 17
- 229910052737 gold Inorganic materials 0.000 claims abstract description 17
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 16
- 238000002844 melting Methods 0.000 claims abstract description 11
- 150000002736 metal compounds Chemical class 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 230000008018 melting Effects 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 15
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 10
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 10
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 abstract description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052804 chromium Inorganic materials 0.000 abstract description 7
- 239000011651 chromium Substances 0.000 abstract description 7
- 229910052719 titanium Inorganic materials 0.000 abstract description 7
- 239000010936 titanium Substances 0.000 abstract description 7
- 238000004544 sputter deposition Methods 0.000 abstract description 6
- 238000000992 sputter etching Methods 0.000 abstract description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 238000001020 plasma etching Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052786 argon Inorganic materials 0.000 abstract description 3
- -1 argon ions Chemical class 0.000 abstract description 3
- 239000007789 gas Substances 0.000 abstract description 2
- 238000010276 construction Methods 0.000 abstract 1
- 238000005755 formation reaction Methods 0.000 abstract 1
- 238000005546 reactive sputtering Methods 0.000 abstract 1
- 150000001875 compounds Chemical class 0.000 description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 3
- 239000003870 refractory metal Substances 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の電極構造およびその製造方法に関
し、特にＧａＡｓ ＭｇＳＦｇＴ の耐熱性ゲート電
極等の下層に高融点金属あるいは高融点金属化合物を備
え、上層に金属を備えた電極ｍ造およびその製造方法に
関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an electrode structure of a semiconductor device and a method of manufacturing the same, and in particular, to an electrode structure of a semiconductor device and a method of manufacturing the same, in particular, the present invention relates to an electrode structure of a semiconductor device and a method of manufacturing the same. , relates to an electrode structure having a metal upper layer and a method for manufacturing the same.
従来、ＧａＡｓＭｇ５ＦＥＴの耐熱性ゲート電極に代表
されるこの種の電極構造では、耐熱性を得るための下層
の高融点金属あるいは高融点金属化合物と電極の電気抵
抗を低減するための上層の金との密着性が悪いために、
チタンあるいはクロムを間に介した構造となっていた。Conventionally, in this type of electrode structure, typified by the heat-resistant gate electrode of GaAsMg5FET, a lower layer of a refractory metal or a refractory metal compound is used to obtain heat resistance, and an upper layer of gold is used to reduce the electrical resistance of the electrode. Due to poor adhesion,
It had a structure with titanium or chromium in between.
上述した従来の高融点金属（化合物）、チタンあるいは
クロム、金の多ＮＩ膜電極では、電極形成後の工程でシ
リコン酸化膜の除去等を行なう場合に、フッ酸系エツチ
ング液はチタンあるいはクロムがエツチングされるため
使用できないという問題点のほか、５００Ｃ程度の熱処
理で金がチタンあるいはクロム層および高融点金属（化
合物）層を透過して基鈑に侵入し、ＧａＡｓＭｇ８ＦＥ
Ｔのゲート電極等ではショートキー特性が劣化するとい
う欠点がある。In the conventional multi-NI film electrode made of high melting point metals (compounds) such as titanium, chromium, and gold, when removing the silicon oxide film in the process after electrode formation, the hydrofluoric acid-based etching solution is not suitable for titanium or chromium. In addition to the problem that it cannot be used because it is etched, gold penetrates the titanium or chromium layer and the high melting point metal (compound) layer and invades the base plate during heat treatment at about 500C.
There is a drawback that the short key characteristic deteriorates when using a T gate electrode or the like.
上述した従来の高融点金属（化合物）、チタンあるいは
クロム、金の多層膜電極構造に対し、本発明は従来の密
着性強化のためのチタンあるいはクロム層を使用せずに
、下層の高融点金属（化合物）と上層の金との密着性が
良好で耐熱性および耐熱性にすぐれた電極構造およびそ
の製造方法を提供する独創的内容を有する。In contrast to the above-described conventional multilayer electrode structure of high melting point metals (compounds), titanium, chromium, and gold, the present invention does not use the conventional titanium or chromium layer for reinforcing adhesion, but instead uses the lower layer of high melting point metals. The invention has an original content that provides an electrode structure with good adhesion between the compound (compound) and the upper layer of gold, and has excellent heat resistance and heat resistance, as well as a manufacturing method thereof.
本発明の電極構造は下層の高融点金属（化合物）上に直
接窒化チタン層を介して上層に金属を備え、その製造方
法とし７て、窒化チタン層の形成前に高融点金属（化合
物）層表面をスパッタエツチングする工程を有している
。The electrode structure of the present invention has a metal as an upper layer directly on a lower layer of a high melting point metal (compound) via a titanium nitride layer, and as a manufacturing method 7, a layer of a high melting point metal (compound) is formed before forming a titanium nitride layer. It has a step of sputter etching the surface.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例としてＧａＡｓ Ｍ Ｅ ８
ＦＥＴのゲート電極の形成方法を示す工程断面図である
。FIG. 1 shows GaAs M E 8 as an embodiment of the present invention.
FIG. 3 is a process cross-sectional view showing a method of forming a gate electrode of an FET.
まず表面の一部１／Ｃイオン注入等によりｎ型層２が形
成されているＧ ａ Ａ ｓ基板１上にスパッタリング
によりタングステンシリサイド膜３を２００ ＯＡの厚
さに形成する（第１図ａ）。次に反応性スノ（ツタリン
グにより窒化チタン膜４を厚さ１００ＯＡＫ形成するが
それに先立ってタングステンシリサイド膜３を数百Ａア
ルゴンイオン４によりスパッタエツチングしく第１図ｂ
）、表面をクリーニングするとともに荒らして窒化チタ
ン膜５の密層性を強化する。次に連続してスパッタリン
グにより金膜６を３００ＯＡ の厚さに形成する（第１
図Ｃ）。First, a tungsten silicide film 3 is formed to a thickness of 200 OA by sputtering on a GaAs substrate 1 on which an n-type layer 2 has been formed by 1/C ion implantation or the like on a part of the surface (FIG. 1a). . Next, a titanium nitride film 4 is formed to a thickness of 100 Å by reactive sintering, but prior to that, the tungsten silicide film 3 is sputter-etched using argon ions 4 of several hundred amps (see FIG. 1b).
), the surface is cleaned and roughened to strengthen the dense layered nature of the titanium nitride film 5. Next, a gold film 6 is successively formed to a thickness of 300 OA by sputtering (the first
Figure C).
ｍＫバタンニングしたフォトレジストをマスクにイオン
ミリングによシ金および窒化チタンを続いてＣＢ＋ ４
系ガスの反応性イオンエツチングによシタングステ
ンシリサイドを加工してゲート電極を得る（第１図ｄ）
。さらにこのゲート電極構造でＦＥＴを形成する場合に
、次にオーミック電極のコンタクト１−としてｎ 層を
形成するとソース寄生抵抗を低減し、ＦＥＴ０高周波特
性を向上することかできるが、ｎＪＷｔをこの構造のゲ
ート電極をマスクとしてイオン注入により形成すること
ができる。イオン注入後は注入層の活性化のために８０
０Ｃ程度のアニールを行なうが、ＧａＡｓ面から砒素が
分解してとび出すのを防ぐため通常、シリコン酸化膜を
マスクとしてアニールを行ないアニール後にはこのシリ
コン酸化膜をフッ酸系のエツチング液で除去する必要が
ある。本発明のゲート電極構造では以上の工程において
も、ショットキー特性の劣化はなく、７ツ酸系のエツチ
ング処理等の股剥れは生じない。Using the mK battened photoresist as a mask, ion milling was performed to deposit gold and titanium nitride, followed by CB+4.
A gate electrode is obtained by processing tungsten silicide by reactive ion etching using a system gas (Fig. 1d).
. Furthermore, when forming an FET with this gate electrode structure, if an n layer is then formed as contact 1 of the ohmic electrode, the source parasitic resistance can be reduced and the high frequency characteristics of the FET0 can be improved. It can be formed by ion implantation using the gate electrode as a mask. After ion implantation, 80°C was applied to activate the implanted layer.
Annealing is performed at approximately 0C, but in order to prevent arsenic from decomposing and jumping out from the GaAs surface, annealing is usually performed using a silicon oxide film as a mask, and after annealing, this silicon oxide film is removed using a hydrofluoric acid-based etching solution. There is a need. In the gate electrode structure of the present invention, there is no deterioration of the Schottky characteristics even in the above steps, and no peeling occurs due to etching treatment using a heptase-based etching process.
次に本発明の別の実施例として、Ｑ ａ Ａ ｓ Ｍ
Ｅ ５ＦＥＴのゲート電極の異なる形成方法の工程断面
図を第２図に示す。本実施例では、ＱａＡｓ基板１およ
び０Ｍ２上にシリコン酸化膜７を成長したのち、フォト
レジストをマスクに反応性イオンエツチングにより、シ
リコン酸化膜７の一部を窓あけしく第２図ａ）、全面に
タングステンシリサイド膜３をスパッタリングにより２
０００Ａ厚に形成し、スパッタエッチにより数百へエツ
チングしたのち、窒化チタン膜５、白金膜８、金膜６を
連続スパッタリングにより各々、５００Ａ、２００Ａ。Next, as another embodiment of the present invention, Q a A s M
FIG. 2 shows process cross-sectional views of different methods of forming the gate electrode of the E5FET. In this example, after a silicon oxide film 7 is grown on the QaAs substrate 1 and 0M2, a part of the silicon oxide film 7 is etched by reactive ion etching using a photoresist as a mask to open the entire surface as shown in FIG. 2a). 2 by sputtering a tungsten silicide film 3.
The titanium nitride film 5, the platinum film 8, and the gold film 6 were formed to a thickness of 500 A and 200 A, respectively, by continuous sputtering.
４０００Ａ と破着する（第２図ｂ）。ここで白金層は
窒化チタンと金とのｖｆｊ着強化の目的で入れている。4000A (Fig. 2b). Here, the platinum layer is included for the purpose of strengthening the VFJ adhesion between titanium nitride and gold.
次にフォトレジストをマスクに金、白金、窒化チタンを
イオンミリングで、タングステンシリサイドを反応性イ
オンエツチングにより加工し、′ｒ字型の断面形状をも
つゲート電極を形成する（第２図ｃ）。本実施例ではゲ
ート長を小さく制御でき、かつＴ′ｆ−型することによ
りゲート電極抵抗を小さくすることができる特徴をもつ
。さらに、シリコン酸化膜をフッ酸系エツチング液で除
去することＫよジ（第２図ｄ）浮遊ｇ」°を低減し、Ｆ
ＥＴ０高周波特性を向上することができる。Next, using the photoresist as a mask, the gold, platinum, and titanium nitride are processed by ion milling, and the tungsten silicide is processed by reactive ion etching to form a gate electrode having an 'r-shaped cross-section (FIG. 2c). This embodiment has the characteristics that the gate length can be controlled to be small and that the gate electrode resistance can be made small by making it T'f-type. Furthermore, by removing the silicon oxide film with a hydrofluoric acid-based etching solution, the floating g'° (Fig. 2 d) can be reduced and the F
ET0 high frequency characteristics can be improved.
以上説明したように本発明は、高融点金属（化合物）表
面をスパッタエッチ処理した後直接窒化チタンを介し、
上層に金を備えた構造及び形成方法により、密着性およ
び耐酸性が良好で高耐熱性をもつ電極を得ることができ
る。智Ｎ性については、通常の４桜き試験、ポンドプル
試験での電極剥れは生じない。また耐熱性ではこの構造
、形成方法によるタングステンシリサイドショットキー
ダイオードの８００Ｃアニール後のφ８は０．７５Ｖ、
ｎ値は１． ｌと安定して良好なショットキー特性が得
られている。As explained above, in the present invention, after sputter etching the surface of a high melting point metal (compound), directly through titanium nitride,
With the structure and formation method in which the upper layer includes gold, an electrode with good adhesion and acid resistance and high heat resistance can be obtained. Regarding the strength and resistance, electrode peeling does not occur in the usual four-way test and pound-pull test. In terms of heat resistance, the φ8 of the tungsten silicide Schottky diode with this structure and formation method after annealing at 800C is 0.75V.
The n value is 1. A stable and good Schottky characteristic of 1 was obtained.
第ｔｈａ−ｄは本発明によるＱａＡｓ ＭＥ Ｓ ＦＥ
Ｔのゲート電極構造の形成方法を示す工程断面図の一例
である。第２図ａ−ｚｄは同じく本発明によるＱａＡｓ
ＭＥ８Ｔ！’ＥＴのゲート電極構造の形成方法を示す工
程断面図の別の例である。
１・・・・・・Ｇ ａ Ａ ｓ 基板、２・・・・・・
ＱａＡｓｎ層、３・・・・・・タングステンシリサイド
膜、４・・・・・・アルゴンイオン、５・・・・・・窒
化チタン、６・・・・・・金、７・・・・・・シリコン
酸化膜、８・・・・・・白金。
代理人 弁理士 内 涼 ｘｒ−”：。
日
ｔ ：
（−゛
第１図The th-d are QaAs ME S FE according to the present invention.
3 is an example of a process cross-sectional view showing a method for forming a gate electrode structure of T. FIG. FIG. 2 a-zd also show QaAs according to the present invention.
ME8T! It is another example of a process cross-sectional view showing a method for forming a gate electrode structure of 'ET. 1...G a As substrate, 2...
QaAsn layer, 3...Tungsten silicide film, 4...Argon ions, 5...Titanium nitride, 6...Gold, 7... Silicon oxide film, 8...Platinum. Agent Patent Attorney Ryo Uchi xr-”:. Date: (-゛Figure 1
Claims (1)
ン層を介し上層に金層をそなえていることを特徴とする
半導体装置。A semiconductor device comprising a titanium nitride layer directly interposed on a high melting point metal or a high melting point metal compound and a gold layer thereon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19607386A JPS6351679A (en) | 1986-08-20 | 1986-08-20 | Semicondictor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19607386A JPS6351679A (en) | 1986-08-20 | 1986-08-20 | Semicondictor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6351679A true JPS6351679A (en) | 1988-03-04 |
Family
ID=16351750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19607386A Pending JPS6351679A (en) | 1986-08-20 | 1986-08-20 | Semicondictor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6351679A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02143422A (en) * | 1988-11-24 | 1990-06-01 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| EP0552763A2 (en) * | 1992-01-22 | 1993-07-28 | Mitsubishi Denki Kabushiki Kaisha | Compound semiconductor device with self-aligned gate and method of producing this compound semiconductor device |
| JPH06326297A (en) * | 1993-03-19 | 1994-11-25 | Nec Corp | Semiconductor device |
| US5567647A (en) * | 1993-12-07 | 1996-10-22 | Nec Corporation | Method for fabricating a gate electrode structure of compound semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59171171A (en) * | 1983-03-17 | 1984-09-27 | Fujitsu Ltd | Manufacture of compound semiconductor device |
| JPS59181676A (en) * | 1983-03-31 | 1984-10-16 | Fujitsu Ltd | Semiconductor device |
| JPS61127181A (en) * | 1984-11-26 | 1986-06-14 | Fujitsu Ltd | Manufacture of field-effect compound semiconductor device |
-
1986
- 1986-08-20 JP JP19607386A patent/JPS6351679A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59171171A (en) * | 1983-03-17 | 1984-09-27 | Fujitsu Ltd | Manufacture of compound semiconductor device |
| JPS59181676A (en) * | 1983-03-31 | 1984-10-16 | Fujitsu Ltd | Semiconductor device |
| JPS61127181A (en) * | 1984-11-26 | 1986-06-14 | Fujitsu Ltd | Manufacture of field-effect compound semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02143422A (en) * | 1988-11-24 | 1990-06-01 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| EP0552763A2 (en) * | 1992-01-22 | 1993-07-28 | Mitsubishi Denki Kabushiki Kaisha | Compound semiconductor device with self-aligned gate and method of producing this compound semiconductor device |
| JPH06326297A (en) * | 1993-03-19 | 1994-11-25 | Nec Corp | Semiconductor device |
| US5567647A (en) * | 1993-12-07 | 1996-10-22 | Nec Corporation | Method for fabricating a gate electrode structure of compound semiconductor device |
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