JPS61188959A - Manufacture of capacitor for integrated circuit - Google Patents

Manufacture of capacitor for integrated circuit

Info

Publication number
JPS61188959A
JPS61188959A JP2969185A JP2969185A JPS61188959A JP S61188959 A JPS61188959 A JP S61188959A JP 2969185 A JP2969185 A JP 2969185A JP 2969185 A JP2969185 A JP 2969185A JP S61188959 A JPS61188959 A JP S61188959A
Authority
JP
Japan
Prior art keywords
layer
metal layer
high melting
melting point
point metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2969185A
Other languages
Japanese (ja)
Inventor
Yoshihiro Kinoshita
木下　義弘
Motoki Furukawa
古川　元己
Masumi Hiroya
真澄 廣谷
Tatsuro Mitani
三谷　達郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2969185A priority Critical patent/JPS61188959A/en
Publication of JPS61188959A publication Critical patent/JPS61188959A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body

Abstract

PURPOSE:To reduce an input loss to a capacitor and to increase the degree of freedom of a production process by forming a 3-layer structure of a high melting point metal layer, a gold layer and a high melting metal layer in a lower metal layer for forming the capacitor, thereby enhancing the reliability of an electrode of an upper layer metal layer. CONSTITUTION:A high melting point metal layer 23 made of Ti, Mo of approx. 1,000Angstrom of thickness, a gold layer 24 of approx. 6,000Angstrom of thickness, and a high melting point metal layer 25 made of Ti, Mo of approx. 4,000Angstrom of thickness are sequentially laminated by a sputtering method on the main surface of a GaAs substrate 21 which contains an active region 22. With resist films 26, 27 as masks the layer 25 is patterned by an RIE method, and the layer 24 is then patterned. Then, the resist films 26, 27 are removed, with the layers 25, 24 as masks the layer 23 directly thereunder is patterned by the RIE method.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、集積回路用キャパシターの製造方法に関する
。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a capacitor for an integrated circuit.

（発明の技術的背景） 従来、マイクロ波用モノリシックＩＣのコンデンサーと
して使用される集積回路用キャパシターは、第２図に示
すような構造を有している。図中１は、半絶縁性のＧａ
ＡＳ基板２上の所定領域に形成された下層メタル層であ
る。下層メタル層１は、１１層３、ＡＩ層４、Ｔｉ層５
を順次積層した構造を有している。下層メタル層１上に
は、ＣＶＤ酸化ｌｌ１６を介して上層メタル層７が形成
されている。上層メタル層７は、Ｔｉ層８、Ｐｔ１１９
、ＡＵ層１０を順次積層した構造を有している。上層メ
タル層７は、ＧａＡｓ基板２の能動領域１１にオーミッ
ク電極１２を介して接続されている。(Technical Background of the Invention) Conventionally, an integrated circuit capacitor used as a capacitor for a microwave monolithic IC has a structure as shown in FIG. 1 in the figure is semi-insulating Ga
This is a lower metal layer formed in a predetermined area on the AS substrate 2. The lower metal layer 1 includes an 11 layer 3, an AI layer 4, and a Ti layer 5.
It has a structure in which layers are sequentially laminated. An upper metal layer 7 is formed on the lower metal layer 1 via a CVD oxidation layer 116. The upper metal layer 7 includes a Ti layer 8 and a Pt119 layer.
, AU layer 10 are sequentially laminated. The upper metal layer 7 is connected to the active region 11 of the GaAs substrate 2 via an ohmic electrode 12.

（背景技術の問題点〕 このように構成された従来の集積回路用キャパシターの
製造に際しては、ＣＶＤ酸化膜６を剥ぐ場合、予め下層
メタル層１をレジスト膜で覆い、ｃｖｏａ化膜６をエツ
チングしてからレジスト膜を除去する工程を経ている。(Problems in the Background Art) When manufacturing a conventional integrated circuit capacitor configured as described above, when removing the CVD oxide film 6, the lower metal layer 1 is covered in advance with a resist film, and the CVOA film 6 is etched. After that, the resist film is removed.

このため、工程が複雑になると共に、レジスト膜を除去
する際に能動領域１１に損傷を及ぼす問題がある。また
、Ｔｉ層３、Ａ１層４．７ｉ層５からなる下層メタル層
１を形成した後に熱処理ができないため、製造プロセス
の自由度が小さくなる。また、下層メタル層１にＡ１層
４を用いているため、十分な信頼性が得られない。更に
、Ｔｉ１１３、ＡＩ層４をリフトオフ法によって形成す
るためパリが発生し易く、キャパシターの破壊原因とな
っていた。Therefore, there is a problem that the process becomes complicated and that the active region 11 is damaged when the resist film is removed. Further, since heat treatment cannot be performed after forming the lower metal layer 1 consisting of the Ti layer 3, the A1 layer 4, and the i layer 5, the degree of freedom in the manufacturing process is reduced. Furthermore, since the A1 layer 4 is used as the lower metal layer 1, sufficient reliability cannot be obtained. Furthermore, since the Ti layer 113 and the AI layer 4 are formed by a lift-off method, particles are likely to occur, which causes destruction of the capacitor.

〔発明の目的〕[Purpose of the invention]

本発明は、電極の信頼性を高くし、キャパシターへの入
力ロスを小さくすると共に、製造プロセスの自由度を大
きくし、かつ、歩留りの向上を達成することができる集
積回路用キャパシターの製造方法を提供することをその
目的とするものである。The present invention provides a method for manufacturing a capacitor for integrated circuits that can increase the reliability of electrodes, reduce input loss to the capacitor, increase the degree of freedom in the manufacturing process, and improve yield. Its purpose is to provide.

〔発明の概要〕[Summary of the invention]

本発明は、キャパシターを構成する下層メタル層を高融
点メタル層、金層、高融点メタル層の三層構造で形成す
るようにしたことにより、上層メタル層である電極の信
頼性を高くし、キャパシターへの入力ロスを小さくする
と共に、製造プロセスの自由度を大きくし、かつ、歩留
りの向上を達成することができる積回路用キャパシター
の製造方法である。The present invention improves the reliability of the electrode, which is the upper metal layer, by forming the lower metal layer constituting the capacitor with a three-layer structure of a high melting point metal layer, a gold layer, and a high melting point metal layer. This is a method of manufacturing a capacitor for a multi-layer circuit, which can reduce input loss to the capacitor, increase the degree of freedom in the manufacturing process, and improve yield.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.

まず、第１図（Ａ＞に示す如く、ＧａＡｓ基板２１の所
定領域にＦＥＴ動作層となるＮ−領域とこれに連なるＮ
＋層からなる能動領域２２を選択イオン注入法により形
成する。次いで、能動領域２２を含むＧａＡｓ基板２１
の主面に厚さ約１０００人のＴｉ、Ｍｏ等からなる高融
点メタルｍ２３、厚さ約６０００人の金層２４、厚さ約
４０００人のＴｉ、Ｍｏ等からなる高融点メタル層２５
、をスパッタ法により順次積層形成する。First, as shown in FIG.
An active region 22 made of a positive layer is formed by selective ion implantation. Next, a GaAs substrate 21 containing an active region 22 is formed.
A high melting point metal layer 23 made of Ti, Mo, etc. with a thickness of about 1000 thick, a gold layer 24 of about 6000 thick, and a high melting point metal layer 25 made of Ti, Mo, etc. with a thickness of about 4000 thick on the main surface of the
, are sequentially layered by sputtering.

次に、同図（Ｂ）に示す如く、ゲート電極及び下層メタ
ル層を形成するためのマスクとなる所定パターンのレジ
スト膜２６．２７を高融点メタル層２５上の所定領域に
形成する。このレジスト膜２６．２７をマスクにしてを
ＲＩＥ　（ｒｅａｃｔｉＶｅ　　ｉｏｎ　　ｅｔｃｈｉ
ｎｇ）法により高融点メタル層２５をパターニングする
。次いで、パターニングされた高融点メタル層２５をマ
スクにして直下の金層２４をイオンミーリング法により
パターニングする。次いで、レジスト膜２６．２７を除
去してから高融点メタル［１２５及び金層２４をマスク
にして直下の高融点メタル層２３をＲＩＥ法でパターニ
ングする。Next, as shown in FIG. 2B, a resist film 26, 27 having a predetermined pattern is formed in a predetermined region on the high melting point metal layer 25 to serve as a mask for forming a gate electrode and a lower metal layer. Using these resist films 26 and 27 as a mask, perform RIE (reactiVeion etc.)
The high melting point metal layer 25 is patterned by the ng) method. Next, using the patterned high melting point metal layer 25 as a mask, the gold layer 24 immediately below is patterned by ion milling. Next, after removing the resist films 26 and 27, the high melting point metal layer 23 immediately below is patterned by RIE using the high melting point metal layer 125 and the gold layer 24 as masks.

次に、同図（Ｃ）に示す如く、上述のようにして得られ
たゲート電極２８及び下層メタル層２９を覆うＣＶＤ酸
化ｇ！３０を厚さ約２０００人形成する。次いで、スパ
ッタダメージを回復するためにこれに５００℃３０分の
熱処理を施す。次いで、Ｎ＋領領域らなるソース、ドレ
インに通じるコンタクトホールを形成するために、所定
パターンのレジスト膜をＣＶＤ酸化膜３０上に形成する
。レジスト膜を介してコンタクトホールを形成した後、
コン’）　’）　ト＊　−Ａｔ内にＡｕＧｅ／Ｐｔ　（
２０００人１５００人）からなるオーミック電極３１を
リフトオフ法により形成し４３０℃、５分の熱処理を施
す。Next, as shown in FIG. 2C, CVD oxidation (g!) covering the gate electrode 28 and lower metal layer 29 obtained as described above is performed. 30, about 2000 people thick. Next, this is subjected to heat treatment at 500° C. for 30 minutes in order to recover from sputter damage. Next, a resist film having a predetermined pattern is formed on the CVD oxide film 30 in order to form contact holes communicating with the source and drain made of N+ regions. After forming a contact hole through the resist film,
AuGe/Pt (
An ohmic electrode 31 consisting of 2,000 and 1,500 electrodes is formed by a lift-off method and heat-treated at 430° C. for 5 minutes.

次に、同図（Ｄ）に示す如く、オーミック電極３１を介
してソース、ドレインに接続する上層メタル層３２．３
３を、厚さ約１５００人のＴｉ層３４、厚さ約１０００
人のｐｔ上層５、厚さ約６０００人のＡｕ１１３６の三
層構造にしＴＣＶＤ酸化膜３０上に形成して、集積回路
用キャパシターを有する半導体装置を得る。Next, as shown in FIG. 3D, an upper metal layer 32.3 is connected to the source and drain through the ohmic electrode 31
3, a Ti layer 34 with a thickness of about 1500 mm, a thickness of about 1000 mm
A three-layer structure consisting of a PT upper layer 5 and an Au 1136 layer having a thickness of about 6,000 thick is formed on the TCVD oxide film 30 to obtain a semiconductor device having a capacitor for an integrated circuit.

このようにこの集積回路用キャパシターの製造方法によ
れば、Ｔｉ、Ｍｏ等からなる高融点メタル層２５をマス
クにして金層２４にイオンミーリングを施すことができ
るので、金層２４の厚さを十分に厚くしてキャパシター
への入力ロスを小さくすることができる。また、ゲート
電極２８の形成と同時に或はゲートＩｔ極２８の前に下
層メタル！！２９を形成することができるので、製造プ
ロセスの自由度を大きくすることができる。また、下層
メタル１！２９を構成する高融点メタル層２３．２５を
、ＧａＡＳ基板２１及びＣＶＤ酸化膜３０の各々との密
着性に優れた金属に設定することにより、信頼性の高い
上層メタル１３２．３３からなるＩ！極を形成すること
ができる。これらの結果、歩留りの向上を達成すること
ができる。According to this method of manufacturing a capacitor for an integrated circuit, the gold layer 24 can be subjected to ion milling using the high melting point metal layer 25 made of Ti, Mo, etc. as a mask, so that the thickness of the gold layer 24 can be reduced. By making it sufficiently thick, input loss to the capacitor can be reduced. Also, at the same time as forming the gate electrode 28 or before forming the gate electrode 28, a lower metal layer may be formed. ! 29, the degree of freedom in the manufacturing process can be increased. In addition, by setting the high melting point metal layer 23.25 constituting the lower metal layer 1!29 to a metal that has excellent adhesion to each of the GaAS substrate 21 and the CVD oxide film 30, the upper layer metal layer 132 has high reliability. I consisting of .33! can form poles. As a result, an improvement in yield can be achieved.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く、本発明に係る集積回路用キャパシタ
ーの製造方法によれば、 電極の信頼性を高くし、キャパシターへの入力ロスを小
さくすると共に、製造プロセスの自由度を大きくし、か
つ、歩留りの向上を達成することができるものである。As explained above, according to the method of manufacturing a capacitor for an integrated circuit according to the present invention, the reliability of the electrodes is increased, the input loss to the capacitor is reduced, the degree of freedom in the manufacturing process is increased, and the yield is improved. It is possible to achieve improvements in

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（Ａ）乃至同図（Ｄ）は、本発明方法を工程順に
示す説明図、第２図は、従来の方法で製造された集積回
路用キャパシター゛の構成を示す説明図である。 ２１・・・ＧａＡｓ基板、２２・・・能動領域、２３・
・・高融点メタル層、２４・・・金層、２５・・・高融
点メタル層、２６．２７・・・レジスト躾、２８・・・
ゲート電極、２９・・・下層メタル層、３０・・・ＣＶ
ＤＭ化膜、３１・・・オーミック電極、３２．３３・・
・上層メタル層、３４　・Ｔ　ｉ層、３５　・Ｐ　を層
、３６−Ａ　ｕ層。 出願人代理人　弁理士　鈴江武彦 第１　図 第２図1(A) to 1(D) are explanatory diagrams showing the method of the present invention in the order of steps, and FIG. 2 is an explanatory diagram showing the structure of an integrated circuit capacitor manufactured by a conventional method. 21... GaAs substrate, 22... active region, 23...
... High melting point metal layer, 24... Gold layer, 25... High melting point metal layer, 26.27... Resist layer, 28...
Gate electrode, 29... Lower metal layer, 30... CV
DM film, 31... Ohmic electrode, 32.33...
- Upper metal layer, 34 - Ti layer, 35 - P layer, 36 - Au layer. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 　半導体基板上に第１の高融点メタル層、金層、第２の
高融点メタル層を順次積層形成する工程と、前記第２の
高融点メタル層上に所定パターンのレジスト膜を形成し
、該レジスト膜をマスクにして前記第２の高融点メタル
層を反応性イオンエッチング法によりパターニングする
工程と、前記レジスト膜及びパターニングされた前記第
２の高融点メタル層をマスクにして前記金層をイオンミ
ーリング法によりパターニングする工程と、前記レジス
ト膜を除去する工程と、パターニングされた前記第２の
高融点メタル層及び前記金層をマスクにして前記第１の
高融点メタル層を反応性イオンエッチング法によりパタ
ーニングする工程と、パターニングされた前記第２の高
融点メタル層、前記金層及び前記第１の高融点メタル層
を覆う絶縁膜を前記半導体基板上に形成する工程とを具
備することを特徴とする集積回路用キャパシターの製造
方法。A step of sequentially laminating a first high melting point metal layer, a gold layer, and a second high melting point metal layer on a semiconductor substrate, forming a resist film in a predetermined pattern on the second high melting point metal layer, patterning the second high melting point metal layer using a resist film as a mask, and patterning the gold layer with ions using the resist film and the patterned second high melting point metal layer as a mask; A step of patterning by a milling method, a step of removing the resist film, and a reactive ion etching method of the first high melting point metal layer using the patterned second high melting point metal layer and the gold layer as a mask. and forming an insulating film on the semiconductor substrate to cover the patterned second high melting point metal layer, the gold layer, and the first high melting point metal layer. A method for manufacturing a capacitor for an integrated circuit.
JP2969185A 1985-02-18 1985-02-18 Manufacture of capacitor for integrated circuit Pending JPS61188959A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2969185A JPS61188959A (en) 1985-02-18 1985-02-18 Manufacture of capacitor for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2969185A JPS61188959A (en) 1985-02-18 1985-02-18 Manufacture of capacitor for integrated circuit

Publications (1)

Publication Number Publication Date
JPS61188959A true JPS61188959A (en) 1986-08-22

Family

ID=12283128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2969185A Pending JPS61188959A (en) 1985-02-18 1985-02-18 Manufacture of capacitor for integrated circuit

Country Status (1)

Country Link
JP (1) JPS61188959A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0312950A (en) * 1989-06-12 1991-01-21 Fujitsu Ltd Formation of insulator coating

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0312950A (en) * 1989-06-12 1991-01-21 Fujitsu Ltd Formation of insulator coating

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