JP2792421B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP2792421B2
JP2792421B2 JP5347000A JP34700093A JP2792421B2 JP 2792421 B2 JP2792421 B2 JP 2792421B2 JP 5347000 A JP5347000 A JP 5347000A JP 34700093 A JP34700093 A JP 34700093A JP 2792421 B2 JP2792421 B2 JP 2792421B2
Authority
JP
Japan
Prior art keywords
substrate
etching
phs
film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5347000A
Other languages
Japanese (ja)
Other versions
JPH07193122A (en
Inventor
隆文 今村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP5347000A priority Critical patent/JP2792421B2/en
Publication of JPH07193122A publication Critical patent/JPH07193122A/en
Application granted granted Critical
Publication of JP2792421B2 publication Critical patent/JP2792421B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Element Separation (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は化合物半導体装置の製造
方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a compound semiconductor device.

【0002】[0002]

【従来の技術】図4は従来技術によるGaAsFETの
PHS(Plated Heat Sink)構造の一例の断面図、図5
は平面図である。同図において、1は電界効果トランジ
スタ(FET)の形成されたGaAs基板、2は絶縁
膜、3は金/白金/チタン/(Au/Pt/Ti)より
なるゲート電極、4は前記GaAs基板1上に形成され
た金/白金/チタン/ニッケル/金・ゲルマニウム(A
u/Pt/Ti/Ni/Au・Ge)よりなるソース電
極、5は前記ソース電極と同時に形成されたドレイン電
極、8は補強板となるガラス板、7は前記ガラス板8に
GaAs基板1を貼り付けるための貼り付け材、10は
バイアホール(Via Hole),12は金メッキからなるP
HS、11は前記PHS12を電解メッキするための通
電膜、13は前記PHS12をマスクとして通電膜11
とGaAs基板1をエッチングして形成した素子分離領
域、9はガラス板8とGaAs基板1との間の貼り付け
材7中に発生した気泡または隙間である。
BACKGROUND ART FIG. 4 is cross-sectional view of one example of prior art of GaAsFET PHS (P lated H eat S ink) structure, Figure 5
Is a plan view. In the figure, 1 is a GaAs substrate on which a field effect transistor (FET) is formed, 2 is an insulating film, 3 is a gate electrode made of gold / platinum / titanium / (Au / Pt / Ti), 4 is the GaAs substrate 1 The gold / platinum / titanium / nickel / gold / germanium (A
u / Pt / Ti / Ni / Au.Ge), 5 is a drain electrode formed simultaneously with the source electrode, 8 is a glass plate serving as a reinforcing plate, 7 is a GaAs substrate 1 on the glass plate 8. Pasting material for pasting, 10 is a via hole, 12 is a gold-plated P
HS, 11 is a conductive film for electroplating the PHS 12, and 13 is a conductive film 11 using the PHS 12 as a mask.
And an element isolation region formed by etching the GaAs substrate 1, and 9 are bubbles or gaps generated in the bonding material 7 between the glass plate 8 and the GaAs substrate 1.

【0003】[0003]

【発明が解決しようとする課題】従来技術による図4お
よび図5の構造において、素子分離領域13を形成する
には、PHS12をマスクとして通電膜11をイオンミ
リングにてエッチングした後、これと同様にPHS12
をマスクとしてドライエッチング技術にてGaAs基板
1をエッチングするが、この場合、以下の問題がある。
GaAs基板は500μm程度のものが用いられている
が、GaAs基板に発生した熱を速やかに逃がすために
はGaAs基板の厚さを20〜150μm程度に薄くす
ることが有効で、そのために一般的にガラス板等の透明
な板にFETの形成された表側を貼り付けた状態にて裏
面から研磨、エッチングを行って所望の厚さまで薄化し
た後、PHS構造を従来技術により形成している。この
後、PHSまたはフォトレジストをマスクとしてドライ
エッチング技術によりGaAs基板をエッチングし、素
子分離を行う。
4 and 5, the element isolation region 13 is formed by etching the conductive film 11 by ion milling using the PHS 12 as a mask, and then forming the same. PHS12
Is used to etch the GaAs substrate 1 by dry etching technology. In this case, however, there are the following problems.
Although a GaAs substrate having a thickness of about 500 μm is used, it is effective to reduce the thickness of the GaAs substrate to about 20 to 150 μm in order to quickly release heat generated in the GaAs substrate. A PHS structure is formed by a conventional technique after polishing and etching from the back surface to a desired thickness in a state where the front side on which the FET is formed is attached to a transparent plate such as a glass plate. Thereafter, the GaAs substrate is etched by dry etching using PHS or a photoresist as a mask to perform element isolation.

【0004】しかしこの場合、ガラス板と、貼り付け材
により貼り付けられたGaAs基板との間に、貼り付け
材の塗布時の塗布膜厚及び貼り付け方法及び加工過程の
熱履歴またはストレスにより隙間または気泡が発生する
という問題がある。素子分離のためにGaAs基板をエ
ッチングした後に露出する貼り付け材の表面はエッチン
グガスにより変質硬化するが、この変質硬化層は酸素
(O2)プラズマによるアッシングにより除去すること
ができる。しかし前記した隙間または気泡にエッチング
ガスが入り込み広範囲の貼り付け材の表面を変質硬化さ
せた場合には、その変質硬化層をO2プラズマによるア
ッシングにより除去することは難しく、素子分離した後
のGaAs基板を従来の方法にてガラス板から剥がす時
に、除去しきれなかった変質硬化層がGaAs基板上に
形成されたFETの上に付着して外観を損ね、製造歩留
りを悪化させる。この外観歩留り悪化防止のためには前
記の除去しきれない広範囲の変質硬化層を作らないこと
が必要である。本発明の目的は、このような従来の問題
点を解決して、除去しきれない変質硬化層を作ることの
ない半導体装置の製造方法を提供することにある。
In this case, however, there is a gap between the glass plate and the GaAs substrate attached by the adhesive due to the applied film thickness at the time of application of the adhesive, the attaching method, and the heat history or stress of the working process. Alternatively, there is a problem that air bubbles are generated. The surface of the adhesive material exposed after etching the GaAs substrate for element isolation is altered and hardened by the etching gas, and the altered hardened layer can be removed by ashing with oxygen (O 2 ) plasma. However, when the etching gas enters the gaps or bubbles and the surface of the adhesive material over a wide area is altered and hardened, it is difficult to remove the altered hardened layer by ashing with O 2 plasma, and it is difficult to remove GaAs after element isolation. When the substrate is peeled off from the glass plate by a conventional method, the deteriorated hardened layer that cannot be completely removed adheres to the FET formed on the GaAs substrate, impairing the appearance and deteriorating the manufacturing yield. In order to prevent the appearance yield from deteriorating, it is necessary not to form the above-mentioned altered hardened layer which cannot be completely removed. An object of the present invention is to provide a method of manufacturing a semiconductor device which solves such a conventional problem and does not form an altered hardened layer which cannot be completely removed.

【0005】[0005]

【課題を解決するための手段】本発明は、半絶縁性化合
物半導体基板の表面にゲート電極、ソース電極およびド
レイン電極を含む素子部を形成すると共に、前記ゲート
電極、ソース電極またはドレイン電極の形成と同時にこ
れと全部もしくは一部の同一構造を有する積層金属膜を
前記基板の素子分離領域に形成する工程と、前記基板の
素子形成面に貼り付け材を介して補強板を貼り付ける工
程と、前記基板の裏面にPHS(PlatedHeat Sink)メ
ッキ用の通電膜および所定のパターンのPHSを形成す
る工程と、前記基板の裏面より前記PHSをマスクとし
て前記通電膜をエッチングする工程と、前記PHSをマ
スクとして前記基板の裏面より前記基板の素子分離領域
をエッチングする工程とを備え、前記積層金属膜を前記
基板のエッチングの際のエッチングを止める膜として用
いることを特徴とする半導体装置の製造方法である。
According to the present invention, an element portion including a gate electrode, a source electrode and a drain electrode is formed on a surface of a semi-insulating compound semiconductor substrate, and the formation of the gate electrode, the source electrode or the drain electrode is performed. At the same time, a step of forming a laminated metal film having the same structure as the whole or a part thereof in the element isolation region of the substrate, and a step of attaching a reinforcing plate to the element formation surface of the substrate via an adhesive, Forming a conductive film for PHS (Plated Heat Sink) plating and a PHS having a predetermined pattern on the back surface of the substrate; etching the conductive film from the back surface of the substrate using the PHS as a mask; Etching a device isolation region of the substrate from the back surface of the substrate, wherein the laminated metal film is used for etching the substrate. A method of manufacturing a semiconductor device, which comprises using as the film to stop the etching.

【0006】また、本発明は、半絶縁性化合物半導体基
板の表面にゲート電極、ソース電極およびドレイン電極
と、該各電極間の絶縁膜とを含む素子部を形成すると共
に、前記絶縁膜の形成と同時に前記基板の素子分離領域
に絶縁膜を形成する工程と、前記基板の素子形成面に貼
り付け材を介して補強板を貼り付ける工程と、前記基板
の裏面にPHS(Plated Heat Sink)メッキ用の通電膜
および所定のパターンのPHSを形成する工程と、前記
基板の裏面より前記PHSをマスクとして前記通電膜を
エッチングする工程と、前記PHSをマスクとして前記
基板の裏面より前記基板の素子分離領域をエッチングす
る工程とを備え、前記絶縁膜を前記基板のエッチングの
際のエッチングを止める膜として用いることを特徴とす
る半導体装置の製造方法である。
The present invention also provides a method for forming an element portion including a gate electrode, a source electrode, and a drain electrode on a surface of a semi-insulating compound semiconductor substrate and an insulating film between the electrodes, and forming the insulating film. At the same time, a step of forming an insulating film in an element isolation region of the substrate, a step of attaching a reinforcing plate to an element formation surface of the substrate via an adhesive, and a PHS (Plated Heat Sink) plating on the back surface of the substrate Forming a conductive film and a PHS having a predetermined pattern, etching the conductive film from the back surface of the substrate using the PHS as a mask, and isolating the substrate from the back surface of the substrate using the PHS as a mask. Etching a region, wherein the insulating film is used as a film for stopping etching at the time of etching the substrate. It is.

【0007】[0007]

【作用】本発明では、まずGaAs基板上に従来の技術
によりゲート電極、ソース電極、ドレイン電極、活性領
域からなる素子部を形成する。そして、このゲート電極
あるいはソース電極・ドレイン電極を形成するとき、前
記GaAs基板上の素子分離領域に前記ゲート電極ある
いはソース電極・ドレイン電極と同一金属の積層金属膜
を同時に形成する。GaAs基板上の素子部形成が完了
した後、このGaAs基板上の素子が形成された表面を
貼り付け材にて補強板に貼り付け、従来の技術にてGa
As基板の裏面を研磨薄化し、バイアホール、PHSを
形成する。このPHSをマスクとしてGaAs基板の素
子分離領域を裏面からドライエッチングによりエッチン
グ除去し、積層金属膜を露出させる。次に露出させた積
層金属膜を前記したPHSをマスクとしてイオンミリン
グによりエッチングを行い前記したGaAs基板の素子
分離を行う。ここで積層金属膜は、GaAs基板の素子
分離領域のドライエッチング時に、エッチングガスが貼
り付け材内部に発生した隙間、気泡に浸入し貼り付け材
を変質硬化させるのを防止する。このため貼り付け材の
変質硬化層は表面にのみ形成されるので、O2プラズマ
によるアッシングにより容易に除去される。また、積層
金属膜の代わりに絶縁膜を用いてもよく、この場合は、
従来の技術により素子部ゲート、ソース、ドレイン電極
間の絶縁膜として形成された酸化膜を素子分離領域に残
すことでエッチングを止めるための膜として利用するこ
とができる。この酸化膜によるエッチングを止めるため
の膜はウエットエッチングにて除去が可能であり、貼り
付け材表面のドライエッチングによる変質硬化層を防止
することに有効である。
According to the present invention, an element portion including a gate electrode, a source electrode, a drain electrode and an active region is first formed on a GaAs substrate by a conventional technique. When forming the gate electrode or the source electrode / drain electrode, a laminated metal film of the same metal as the gate electrode or the source electrode / drain electrode is simultaneously formed in the element isolation region on the GaAs substrate. After the formation of the element portion on the GaAs substrate is completed, the surface on which the element is formed on the GaAs substrate is attached to a reinforcing plate with an adhesive, and Ga is formed by a conventional technique.
The back surface of the As substrate is polished and thinned to form via holes and PHS. Using the PHS as a mask, the element isolation region of the GaAs substrate is etched away from the back surface by dry etching to expose the laminated metal film. Next, the exposed laminated metal film is etched by ion milling using the above-mentioned PHS as a mask to perform element isolation of the GaAs substrate. Here, the laminated metal film prevents the etching gas from penetrating into gaps and bubbles generated inside the adhesive material during dry etching of the element isolation region of the GaAs substrate, thereby preventing the adhesive material from being altered and hardened. Therefore, the altered hardened layer of the adhesive is formed only on the surface, and is easily removed by ashing with O 2 plasma. Further, an insulating film may be used instead of the laminated metal film. In this case,
The oxide film formed as an insulating film between the gate, source, and drain electrodes of the element portion by the conventional technique can be used as a film for stopping etching by leaving the oxide film in the element isolation region. The film for stopping the etching by the oxide film can be removed by wet etching, which is effective in preventing a deteriorated hardened layer due to dry etching on the surface of the adhesive material.

【0008】[0008]

【実施例】次に、本発明の実施例について、図面を参照
して説明する。図1は本発明の方法によって得られる半
導体装置の平面図であり、図2は図1におけるA−A’
線による断面図である。図1において、GaAs基板1
上に従来の技術によりゲート電極3、ソース電極4、ド
レイン電極5からなる素子が形成されている。また各素
子の素子分離領域には、GaAs基板の裏面から素子分
離領域のドライエッチング時に、エッチングガスが貼り
付け材内部に発生した隙間または気泡に浸入し、貼り付
け材を変質硬化させるのを防止する積層金属膜6が形成
されている。図2に示すように、GaAs基板1は素子
が形成された面(表面)を貼り付け材7により補強板で
あるガラス板8に固定されている。気泡9は貼り付け材
7の塗布時の塗布膜厚のばらつき、貼り付け方法及び加
工過程の熱履歴またはストレスにより発生する。またG
aAs基板1の裏面には、バイアホール10、通電膜1
1、PHS12が形成されている。素子分離領域13は
PHS12をマスクとして通電膜11を除去後、積層金
属膜6をエッチングを止めるための膜として用いてGa
As基板1の除去を行う。
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a semiconductor device obtained by the method of the present invention, and FIG.
It is sectional drawing by a line. In FIG. 1, a GaAs substrate 1
An element including a gate electrode 3, a source electrode 4, and a drain electrode 5 is formed thereon by a conventional technique. Also, in the element isolation region of each element, during dry etching of the element isolation region from the back surface of the GaAs substrate, the etching gas is prevented from penetrating into gaps or bubbles generated inside the adhesive material, thereby preventing the adhesive material from being altered and hardened. The laminated metal film 6 is formed. As shown in FIG. 2, the surface (surface) of the GaAs substrate 1 on which the elements are formed is fixed to a glass plate 8 as a reinforcing plate by an adhesive 7. The bubbles 9 are generated due to a variation in the applied film thickness when the adhesive 7 is applied, a heat history or a stress during the attaching method and the processing process. G
The via hole 10 and the conductive film 1 are provided on the back surface of the aAs substrate 1.
1. The PHS 12 is formed. After removing the conductive film 11 using the PHS 12 as a mask, the element isolation region 13 is used as a film for stopping the etching of the laminated metal film 6 to form a Ga.
The As substrate 1 is removed.

【0009】次に、図1および図2の構造の半導体装置
の製造工程を図3を参照して説明する。まず、図3
(a)に示すように、従来技術により、活性層領域を形
成したGaAs基板1上に絶縁膜2を形成した後、蒸着
法によりチタン(Ti)の厚さ500オングストロー
ム、白金(Pt)の厚さ1000オングストローム、金
(Au)の厚さ2000オングストロームからなるゲー
ト電極3と、金ゲルマニウムの厚さ1500オングスト
ローム、ニッケルの厚さ500オングストローム、チタ
ンの厚さ500オングストローム、白金の厚さ1000
オングストローム、金の厚さ2000オングストローム
からなるソース電極4およびドレイン電極5とで構成さ
れる素子部を形成する。この前記したゲート電極3を形
成するときに、ゲート電極と同時に同一構造の積層金属
膜6を素子分離領域13に形成する。次に、図3(b)
に示すように、従来の技術を用いて、GaAs基板1上
の素子部形成された面(表面)を貼り付け材7(例え
ば、ネガレジスト)にてガラス板8に貼り付ける。この
時、貼り付け材7の塗布時の塗布膜厚のばらつき、貼り
付け方法及び加工過程の熱履歴またはストレスによっ
て、貼り付け材7の内部に気泡9が発生する。次いで、
GaAs基板1の裏面を30〜150μmの厚さに研磨
薄化し、バイアホール10、チタンの厚さ500オング
ストローム及び金の厚さ2000オングストロームから
なる通電膜11を形成した後、フォトレジスト15をマ
スクとしてPHS12を厚さ約30μmの金メッキにて
形成する。次に、図3(c)に示すように、前記したP
HS12をマスクとして、素子分離領域13の通電膜1
1をイオンミリングにてエッチングした後、同じくPH
S12をマスクとして、GaAs基板1を塩素系のガス
にてエッチングして積層金属膜6を露出させる。次に、
図3(d)に示すように、前記したPHS12をマスク
として、素子分離領域13の積層金属膜6をイオンミリ
ングにてエッチング除去して素子間の分離を終える。こ
の後、イオンミリングにて前記積層金属膜6をエッチン
グ除去したときに形成される貼り付け材7の表面の硬化
層14を酸素(O2)プラズマにて除去する。最後に、
図3(d)のガラス板8に貼り付けられた状態にて素子
間分離の完了したGaAs基板1を従来の技術を用いた
洗浄方法により貼り付け材7を除去して各素子単位に分
離し、半導体装置の製造工程が完了する。
Next, a manufacturing process of the semiconductor device having the structure shown in FIGS. 1 and 2 will be described with reference to FIG. First, FIG.
As shown in FIG. 1A, after an insulating film 2 is formed on a GaAs substrate 1 on which an active layer region is formed by a conventional technique, a thickness of 500 Å of titanium (Ti) and a thickness of platinum (Pt) are formed by a vapor deposition method. A gate electrode 3 having a thickness of 1000 angstroms and a thickness of 2000 angstroms of gold (Au); a thickness of 1500 angstroms of gold germanium; a thickness of 500 angstroms of nickel; a thickness of 500 angstroms of titanium;
An element portion composed of the source electrode 4 and the drain electrode 5 each having a thickness of Å and a thickness of 2,000 Å of gold is formed. When the gate electrode 3 is formed, the laminated metal film 6 having the same structure is formed in the element isolation region 13 simultaneously with the gate electrode. Next, FIG.
As shown in FIG. 1, the surface (surface) on which the element portion is formed on the GaAs substrate 1 is attached to the glass plate 8 with an adhesive 7 (for example, a negative resist) using a conventional technique. At this time, bubbles 9 are generated in the inside of the bonding material 7 due to a variation in the applied film thickness when the bonding material 7 is coated, a heat history or a stress in the bonding method and the processing process. Then
The back surface of the GaAs substrate 1 is polished and thinned to a thickness of 30 to 150 μm, and a via hole 10, a conductive film 11 having a thickness of 500 Å of titanium and a thickness of 2,000 Å of gold are formed, and the photoresist 15 is used as a mask. The PHS 12 is formed by gold plating having a thickness of about 30 μm. Next, as shown in FIG.
Using the HS 12 as a mask, the conductive film 1 in the element isolation region 13
After etching 1 by ion milling,
Using S12 as a mask, the GaAs substrate 1 is etched with a chlorine-based gas to expose the laminated metal film 6. next,
As shown in FIG. 3D, using the PHS 12 as a mask, the stacked metal film 6 in the element isolation region 13 is removed by etching by ion milling to complete the isolation between the elements. Thereafter, the hardened layer 14 on the surface of the adhesive 7 formed when the laminated metal film 6 is removed by etching by ion milling is removed by oxygen (O 2 ) plasma. Finally,
The GaAs substrate 1 which has been separated from elements in the state of being bonded to the glass plate 8 of FIG. 3D is separated into individual elements by removing the bonding material 7 by a cleaning method using a conventional technique. Then, the manufacturing process of the semiconductor device is completed.

【0010】また、本発明の第2の実施例として、以下
のような方法も挙げられる。第1の実施例ではGaAs
基板1の裏面より、PHS12をマスクとして、塩素系
のガスにて前記GaAs基板1をエッチング除去する時
のエッチングを止めるための膜として、ゲート電極3と
同時に形成し、かつ同一構造の積層金属膜6を用いた
が、ソース電極(またはドレイン電極)の一部を積層金
属膜6として用いることも可能である。この場合には、
ソース電極の構成金属である金ゲルマニウムの厚さ15
00オングストローム,ニッケルの厚さ500オングス
トローム,チタンの厚さ500オングストローム,白金
の厚さ1000オングストローム,金の厚さ2000オ
ングストロームの内、チタンの厚さ500オングストロ
ーム,白金の厚さ1000オングストローム,金の厚さ
2000オングストロームを素子分離領域にも同時形成
することで積層金属膜6となり、第1の実施例と同等の
効果が得られる。
[0010] As a second embodiment of the present invention, the following method is also mentioned. In the first embodiment, GaAs
Using the PHS 12 as a mask, a laminated metal film formed simultaneously with the gate electrode 3 and having the same structure as a film for stopping the etching when the GaAs substrate 1 is etched and removed with a chlorine-based gas from the back surface of the substrate 1 Although 6 is used, a part of the source electrode (or the drain electrode) may be used as the laminated metal film 6. In this case,
Thickness of gold germanium which is a constituent metal of source electrode 15
00 Å, nickel 500 Å, titanium 500 Å, platinum 1000 Å, gold 2,000 Å, titanium 500 Å, platinum 1000 Å, and gold By simultaneously forming 2,000 Å in the element isolation region, the laminated metal film 6 is obtained, and the same effect as in the first embodiment can be obtained.

【0011】また、本発明の第3の実施例として、積層
金属膜の代わりに酸化膜等の絶縁膜をGaAs基板の裏
面よりPHSをマスクとして塩素系のガスにて前記Ga
As基板をエッチング除去する時のエッチング制御膜と
して用いることも可能である。この場合、従来の技術に
より素子部ゲート、ソース、ドレイン電極間の絶縁膜と
して形成された酸化膜を素子分離領域に残すことでエッ
チングを止めるための膜として利用することができる。
この酸化膜によるエッチングを止めるための膜はウエッ
トエッチングにて除去が可能であり、貼り付け材表面の
ドライエッチングによる変質硬化層を防止することに有
効である。
In a third embodiment of the present invention, an insulating film, such as an oxide film, is formed from the back surface of a GaAs substrate using a PHS as a mask with a chlorine-based gas instead of a laminated metal film.
It can be used as an etching control film when the As substrate is removed by etching. In this case, an oxide film formed as an insulating film between the gate, source, and drain electrodes of the element portion by the conventional technique can be used as a film for stopping etching by leaving the oxide film in the element isolation region.
The film for stopping the etching by the oxide film can be removed by wet etching, which is effective in preventing a deteriorated hardened layer due to dry etching on the surface of the adhesive material.

【0012】[0012]

【発明の効果】以上述べたように、本発明では、GaA
s基板上の素子分離領域にゲート電極等と同時に積層金
属膜等を形成することで、PHS構造の半導体装置の素
子分離工程において、塩素系ガスがガラス板とGaAs
基板を貼り付けている貼り付け材の内部に発生した気泡
内部に浸入することによりできる広範囲の貼り付け材表
面の変質硬化層の発生を防止することができ、酸素プラ
ズマによる硬化層の除去を容易にする。この効果によ
り、従来の技術を用いた洗浄方法における貼り付け材除
去時において前記した硬化層が半導体装置へ再付着する
ことにより発生する汚れによる製造歩留りの悪化を防止
することができる。
As described above, according to the present invention, GaAs is used.
By forming a laminated metal film and the like at the same time as the gate electrode and the like in the element isolation region on the s substrate, in the element isolation step of the semiconductor device having the PHS structure, the chlorine-based gas and the GaAs
It is possible to prevent the formation of a deteriorated hardened layer on the surface of the adhesive material over a wide range, which can be caused by infiltrating the inside of the air bubbles generated inside the adhesive material on which the substrate is attached, and it is easy to remove the hardened layer by oxygen plasma. To With this effect, it is possible to prevent the production yield from deteriorating due to contamination caused by re-adhesion of the above-described cured layer to the semiconductor device at the time of removing the adhesive in the cleaning method using the conventional technique.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例により得られる半導体装置の
平面図である。
FIG. 1 is a plan view of a semiconductor device obtained according to an embodiment of the present invention.

【図2】本発明の一実施例により得られる半導体装置の
断面図である。
FIG. 2 is a cross-sectional view of a semiconductor device obtained according to one embodiment of the present invention.

【図3】本発明の一実施例を工程順に示す工程断面図で
ある。
FIG. 3 is a process sectional view showing one embodiment of the present invention in the order of processes.

【図4】従来例による半導体装置の断面図である。FIG. 4 is a cross-sectional view of a conventional semiconductor device.

【図5】従来例による半導体装置の平面図である。FIG. 5 is a plan view of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 GaAs基板 2 絶縁膜 3 ゲート電極 4 ソース電極 5 ドレイン電極 6 積層金属膜 7 貼り付け材 8 ガラス板 9 気泡 10 バイアホール 11 通電膜 12 PHS 13 素子分離領域 14 硬化層(イオンミリングによるもの) 15 フォトレジスト 16 硬化層(塩素系ガスによるもの) DESCRIPTION OF SYMBOLS 1 GaAs substrate 2 Insulating film 3 Gate electrode 4 Source electrode 5 Drain electrode 6 Laminated metal film 7 Adhesive material 8 Glass plate 9 Bubbles 10 Via hole 11 Conductive film 12 PHS 13 Element isolation region 14 Hardened layer (by ion milling) 15 Photoresist 16 Hardened layer (by chlorine-based gas)

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01L 21/337 - 21/338 H01L 27/095 H01L 27/098 H01L 29/775 - 29/778 H01L 29/80 - 29/812 H01L 21/70 - 21/74 H01L 21/76 - 21/765 H01L 21/77──────────────────────────────────────────────────の Continued on the front page (58) Surveyed fields (Int.Cl. 6 , DB name) H01L 21/337-21/338 H01L 27/095 H01L 27/098 H01L 29/775-29/778 H01L 29 / 80-29/812 H01L 21/70-21/74 H01L 21/76-21/765 H01L 21/77

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半絶縁性化合物半導体基板の表面にゲー
ト電極、ソース電極およびドレイン電極を含む素子部を
形成すると共に、前記ゲート電極、ソース電極またはド
レイン電極の形成と同時にこれと全部もしくは一部の同
一構造を有する積層金属膜を前記基板の素子分離領域に
形成する工程と、前記基板の素子形成面に貼り付け材を
介して補強板を貼り付ける工程と、前記基板の裏面にP
HS(Plated Heat Sink)メッキ用の通電膜および所定
のパターンのPHSを形成する工程と、前記基板の裏面
より前記PHSをマスクとして前記通電膜をエッチング
する工程と、前記PHSをマスクとして前記基板の裏面
より前記基板の素子分離領域をエッチングする工程とを
備え、前記積層金属膜を前記基板のエッチングの際のエ
ッチングを止める膜として用いることを特徴とする半導
体装置の製造方法。
An element portion including a gate electrode, a source electrode, and a drain electrode is formed on a surface of a semi-insulating compound semiconductor substrate, and at the same time as the formation of the gate electrode, the source electrode, or the drain electrode, all or part thereof. Forming a laminated metal film having the same structure in an element isolation region of the substrate, attaching a reinforcing plate to an element formation surface of the substrate via an adhesive, and forming a P on the back surface of the substrate.
A step of forming an electrically conductive film for HS (Plated Heat Sink) plating and a PHS of a predetermined pattern; a step of etching the electrically conductive film from the back surface of the substrate using the PHS as a mask; and a step of etching the substrate using the PHS as a mask. Etching a device isolation region of the substrate from a back surface, wherein the laminated metal film is used as a film for stopping etching when etching the substrate.
【請求項2】 半絶縁性化合物半導体基板の表面にゲー
ト電極、ソース電極およびドレイン電極と、該各電極間
の絶縁膜とを含む素子部を形成すると共に、前記絶縁膜
の形成と同時に前記基板の素子分離領域に絶縁膜を形成
する工程と、前記基板の素子形成面に貼り付け材を介し
て補強板を貼り付ける工程と、前記基板の裏面にPHS
(Plated Heat Sink)メッキ用の通電膜および所定のパ
ターンのPHSを形成する工程と、前記基板の裏面より
前記PHSをマスクとして前記通電膜をエッチングする
工程と、前記PHSをマスクとして前記基板の裏面より
前記基板の素子分離領域をエッチングする工程とを備
え、前記絶縁膜を前記基板のエッチングの際のエッチン
グを止める膜として用いることを特徴とする半導体装置
の製造方法。
2. An element portion including a gate electrode, a source electrode, and a drain electrode and an insulating film between the electrodes is formed on a surface of a semi-insulating compound semiconductor substrate, and the substrate is formed simultaneously with the formation of the insulating film. Forming an insulating film in the element isolation region of step (a), bonding a reinforcing plate to the element forming surface of the substrate via a bonding material, and forming a PHS on the back surface of the substrate.
(Plated Heat Sink) a step of forming a conductive film for plating and a PHS having a predetermined pattern; a step of etching the conductive film using the PHS as a mask from the back surface of the substrate; and a back surface of the substrate using the PHS as a mask. Etching a device isolation region of the substrate, wherein the insulating film is used as a film for stopping etching when etching the substrate.
JP5347000A 1993-12-27 1993-12-27 Method for manufacturing semiconductor device Expired - Lifetime JP2792421B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5347000A JP2792421B2 (en) 1993-12-27 1993-12-27 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5347000A JP2792421B2 (en) 1993-12-27 1993-12-27 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH07193122A JPH07193122A (en) 1995-07-28
JP2792421B2 true JP2792421B2 (en) 1998-09-03

Family

ID=18387250

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5347000A Expired - Lifetime JP2792421B2 (en) 1993-12-27 1993-12-27 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2792421B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6512292B1 (en) 2000-09-12 2003-01-28 International Business Machines Corporation Semiconductor chip structures with embedded thermal conductors and a thermal sink disposed over opposing substrate surfaces
JP2003045875A (en) 2001-07-30 2003-02-14 Nec Kagobutsu Device Kk Semiconductor device and its fabricating method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5122352A (en) * 1974-08-20 1976-02-23 Asahi Glass Co Ltd CHOONPAKO TAICHENSEN
JPS5749252A (en) * 1980-09-09 1982-03-23 Matsushita Electronics Corp Manufacture of semiconductor device
JPH0265155A (en) * 1988-08-30 1990-03-05 Mitsubishi Electric Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPH07193122A (en) 1995-07-28

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