JPS63213943A - Three-dimensional semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To design a circuit easily by connecting a circuit element formed to a lower- layer semiconductor single crystal layer and a circuit element shaped to an upper-layer semiconductor single crystal layer through a through-hole formed to the upper layer semiconductor single crystal layer by an electrode layer. CONSTITUTION:MOS.FETs 4, 4 are shaped to the upper surface of a first silicon layer 1, a contact hole 13 is formed in an insulating film 11 for protection, the whole surface is coated with a polyimide film layer 12, MOS.FETs 4, 4 are also shaped to a second silicon layer 2, and the hole 13 is formed and the whole surface is coated with an insulating film 14. A protective substrate 15 is stuck onto the upper surface of the insulating film 14, the polyimide film layer 12 is formed onto a lower surface, these film, substrate and layer are superposed and bonded, and the protective substrate 15 is removed. A third silicon layer 3 to which MOS.FETs 4, 4 are shaped is bonded with the upper layer of the second silicon layer 2, the upper surface of the layer 3 is coated with a polyimide film layer 12, a contact hole 23 is bored, and an electrode pad 24 is formed. The MOS.FETs 4... separately shaped to each silicon layer 1, 2, 3 are connected by buried metallic layers 20 in holes 13. Accordingly, a circuit is designed easily.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a three-dimensional semiconductor integrated circuit in which a semiconductor single crystal layer on which circuit elements are formed has a multilayer structure.

[Conventional technology]

In recent years, as the density of two-dimensional semiconductor integrated circuits is reaching its limit, three-dimensional semiconductor integrated circuits are being developed. Compared to two-dimensional semiconductor integrated circuits, three-dimensional semiconductor integrated circuits not only allow circuit elements to be integrated at a higher density, but also facilitate parallel processing of information, resulting in faster processing speeds. It has the advantage of being highly functional.

Such three-dimensional semiconductor integrated circuits have conventionally been manufactured through the following steps. For example, when using a silicon semiconductor, first the upper surface of a silicon wafer on which predetermined circuit elements and electrodes are formed is covered with an insulating layer, and a polycrystalline silicon film is grown thereon by low-temperature vapor phase growth or the like. Next, this polycrystalline silicon film is partially melted and recrystallized using a laser or an electron beam, and upper layer circuit elements are formed in the crystallized portions. After forming electrodes and the like on the circuit element, the upper surface is again covered with an insulating layer, and this process is repeated as many times as necessary.

The above-mentioned conventional technology is well known, and for example, it is described in "Electronic Materials J, January 1987 issue, No. 4," published by Kogyo Kenkyukai.
It is disclosed on pages 4 to 51, etc.

[Problem that the invention seeks to solve]

However, in conventional three-dimensional semiconductor integrated circuits manufactured in this way, upper layer circuit elements are formed by melting and recrystallizing a polycrystalline silicon film by irradiating a small spot such as a laser or electron beam. Obtaining a crystalline region has caused the following problems.

■ Because melt recrystallization occurs rapidly, crystallinity is poor and crystal orientation is not constant. For this reason, there are many variations in the characteristics of the elements, making circuit design difficult.
It also causes a decrease in yield.

■ Since it is not easy to make a thick layer into a single crystal, devices such as MOS/FET are usually formed using the interface of the single crystal region, and the bulk cannot be fully utilized, making it difficult to form bipolar transistors, etc. Have difficulty.

■ It is not easy to make the entire surface a uniform single crystal region;
Due to the occurrence of crystal grain boundaries, etc., it is difficult to increase the density of the device.

■ Because a laser or electron beam, etc. is sequentially irradiated to a predetermined location to melt and recrystallize it, it is not possible to process many wafers at once, which results in long manufacturing times, poor productivity, and Process development becomes complicated and difficult, which becomes an obstacle to cost reduction.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the three-dimensional semiconductor integrated circuit according to the present invention has circuit elements separately added to the upper layer of the lower semiconductor single crystal layer in which the circuit elements are formed. The lower semiconductor single crystal layer formed with is bonded, and a through hole is provided in the upper semiconductor single crystal layer, and the circuit element formed in the lower semiconductor single crystal layer and the upper semiconductor single crystal layer are connected through the through hole. It is characterized in that the formed circuit elements are connected through an electrode layer.

[For production]

A method for manufacturing a three-dimensional semiconductor integrated circuit according to the present invention will be explained.

As the semiconductor single crystal layer constituting each layer, a silicon wafer or the like with good crystallinity formed by the conventional CZ method or FZ method is used. Formation of circuit elements on the lower and upper semiconductor single crystal layers is performed individually for each layer using a conventional method. First, through holes are opened at predetermined locations in the upper semiconductor single crystal layer. Next, an upper semiconductor single crystal layer is bonded to a predetermined position above the lower semiconductor single crystal layer. Note that after bonding the upper and lower semiconductor single crystal layers, a through hole may be opened in the upper semiconductor single crystal layer. Finally, an electrode layer with a predetermined pattern is formed on the upper surface of the upper semiconductor single crystal layer and in the through holes to connect the circuit elements formed in the upper semiconductor single crystal layer and the circuit elements formed in the lower semiconductor single crystal layer. Connect the necessary points in between.

When a two-layer three-dimensional semiconductor integrated circuit is formed as described above, ``This upper layer semiconductor single crystal layer is now used as a lower layer semiconductor single crystal layer, and a new upper layer semiconductor single crystal layer is added above it by the same process. By bonding the crystal layers and repeating this process, a three-dimensional semiconductor integrated circuit having three or more layers can be constructed.

[Embodiment 1] An embodiment of the present invention will be described below based on FIGS. 1 to 10.

In this embodiment, a first silicon layer 1 made of a p-type (100) wafer is used as the lower semiconductor single crystal layer which is the first layer, and the first silicon layer 1 is an upper layer for the first layer and the lower layer is for the third layer. The second silicon layer 2 made of an n-type (100) wafer is used as the second semiconductor single crystal layer, and the second silicon layer 2 made of an n-type (100) wafer is used as the third upper layer semiconductor single crystal layer. The present invention relates to a three-dimensional semiconductor integrated circuit using a MOS-FET using a silicon layer 3 and a polyimide film as an adhesive layer for bonding each semiconductor single crystal layer.

To explain the manufacturing process of this three-dimensional semiconductor integrated circuit, first, as shown in FIG. 2, n-channel MOS-FETs 4 are provided at predetermined locations on the upper surface of the first silicon layer 1.

The MOS-FET 4 includes an insulating film 5 that covers the upper surface of the first silicon layer 1 and has a window at a predetermined location, and an insulating film 5 that is formed at both ends of this window in the surface layer of the first silicon layer 1 and serves as a source and a drain, respectively. The mold diffusion layers 6 and 6 and the insulating film 5
a gate oxide film 7 formed to cover the entire window; a gate polycrystalline silicon film 8 formed only on the central upper surface of this gate oxide film 7; and a protective insulating film 9 covering these upper surfaces. Consists of a predetermined pattern of wiring type +110,
Further, a protective insulating film 11 is formed to cover the entire upper surface. The insulating film 5 is a film of Sin, SiN, etc. formed by a thermal oxidation method or a low-temperature vapor phase growth method, and is first formed on the entire upper surface of the first silicon layer 1 and then etched by a photoetching technique or a selective etching technique. A window is opened in the portion where the gate oxide films 7, 7 are to be formed. and,
A thin gate oxide film 7 is formed by thermal oxidation or the like. The gate polycrystalline silicon film 8 is a polycrystalline silicon film formed by low-temperature vapor phase epitaxy, etc., and is formed by photoetching technology,
It is formed into a predetermined pattern by selective etching technology.

The diffusion layer 6 is formed by selectively diffusing n-type impurities into the first silicon layer 1 using the gate polycrystalline silicon film 8 and the insulating film 5 as a mask using an ion implantation method, a thermal diffusion method, or the like. Ru. The protective insulating film 9 is a film of 5iOz, SiN, etc. formed by low temperature vapor phase growth or the like. The film forming the wiring electrode 10 is formed by forming a contact hole in the protective insulating film 9 and the gate oxide film 7 in a portion located above the center of the formation location of each diffusion layer 6 by photo-etching technology or selective etching technology. Then, sputtering, electron beam evaporation, or low pressure CVD (Che
AI, Mo5W, WSi2, Mo formed by the vapor deposition method etc.
A conductive film made of a material such as 5iz or TiSi,
It is formed into a predetermined pattern by photo-etching technology or selective etching technology, and becomes the source electrode or drain electrode of the MOS-FET 4. The protective insulating film 11 is a film of SiO□ or the like formed by low-temperature vapor phase epitaxy or the like.
To ensure the subsequent adhesion of the second silicon layer 2,
The surface is smoothed using a flattening technique such as an etch bank method.

Next, as shown in FIG. 3, after forming a contact hole 13 at a predetermined position of the protective insulating film 11 corresponding to the position of the through hole, this protective insulating film 11 and the hole 13 are formed.
A polyimide film IEJ12 is coated on the entire upper surface of the sample. This polyimide film layer 12 is used as an adhesive layer, and usually finishes curing at a temperature of about 200°C to 250°C, but here it is cured at a temperature of 80°C for later adhesion.
Heat it to about ℃ and leave it in a semi-hardened state.

Further, as shown in FIG. 4, the second silicon layer 2 is also formed with MOS FETs 4 and 4 in the same process as the first silicon layer 2.
will be established. However, since the second silicon layer 2 is an n-type semiconductor, n-type impurities are diffused into the diffusion layer 6, and this MOS
-FET4.4 becomes p-channel.

As shown in FIG. 5, in the second silicon layer 2 on which the MOS-FETs 4 and 4 are formed, through holes are formed from the protective insulating film 11 on the surface to the second silicon layer 2. A hole 13 is formed, and the hole 13 and the protective insulating film 11 are covered with an insulating film 14. The holes 13 are formed by photo-etching or selective etching using an enchantment such as fluoro-nitric acid using a resist film as a mask. However, if the resist film cannot withstand the edging agent sufficiently because the holes 13 are deep, a metal film such as CrAu or TiAu is formed by vapor deposition or sputtering, and then etched by photo-etching or selective etching. 1 pJ of the -F metal at a predetermined hole position is removed, and holes 13 are formed using an alkaline etchant such as F.7 nitric acid or KOHXNaOH using the remaining metal film as a mask. C r A u −, T i A remaining after the formation of the hole 13
Films such as u are removed by etching with aqua regia, hot concentrated sulfuric acid, etc.

The insulating film 14 is a film of 5i02, SiN, etc. formed by a sputtering method, a low-temperature vapor phase growth method, a photo-CVD method, or the like.

Then, as shown in FIG. 6, a protective substrate 15 is pasted on the upper surface of this second silicon layer 2 via a wax layer I6, and then smoothed from the lower surface side to a thickness of about 0.5 to 200 μm. A polyimide film layer 12 similar to the first silicon layer 1 is formed on the entire lower surface. The wax layer 16 is made of wax or the like, and is also filled in the holes 13 to reliably attach the protective substrate 15. The protective substrate 15 is a temporary support material made of glass, ceramics, or the like. The smoothing process is carried out from the back side until the thickness reaches about 0.5 to 200 μm by boring, lapping, etc., or etching using KOH, NaOH, fluoronitric acid, etc. In this case, the second silicon N2 is (1
00) Since a wafer is used, preferential etching using KOH or NaOH is effective. The polyimide film layer 12 is heated to 80° C. as in the case of the first silicon layer 1.
Heat to a moderate degree to semi-cure.

The first silicon layer 1 and second silicon layer 2 formed as described above are overlapped at a predetermined position as shown in FIG. 7, and bonded by applying appropriate pressure at a temperature of about 100°C. do. During this bonding, the wax N16 has a softening point of about 120° C., so it will not deform even if pressure is applied between the second silicon layer 2 and the protective substrate 15.

Once the first silicon layer 1 and the second silicon layer 2 have been bonded, as shown in FIG. Remove. At this time, the wax layer 16 remaining on the second silicon layer 2 is removed using a solvent such as Tricrane. Moreover, when the wax layer 16 is completely removed, the polyimide film layers 12 exposed at the bottom of the hole 13 are removed and the second
The hole 13 on the silicon layer 2 side is replaced with the hole 13 on the first silicon layer 1 side.
Complete the through hole. The polyimide film layers 12 are removed by plasma etching or K.
This is done by etching using an etchant such as Oll. Polyimide film layer 12 exposed at the bottom of hole 13.
12 is removed, a predetermined pressure is applied to the first silicon layer 1 and the second silicon layer 2 again in order to completely cure the polyimide film layers 12 remaining on the adhesive layer and ensure adhesion. is added for a predetermined time and at a predetermined temperature.

When the first silicon layer l and the second silicon layer 2 are securely bonded together in this way, as shown in FIG.
and a second metal film 18, and further cover the second metal film 18 other than the hole 13.
The upper surface of the metal film 18 is covered with a resist film 19, and a buried metal layer 20 is formed in the hole 13 using the resist film 19 as a mask.

The first metal film 17 is a metal film made of Cr, Ti, etc., and the second metal film 18 is a metal film made of Cu, Ni, etc., and is continuously formed by sputtering or electron beam evaporation. be done. The resist film 19 is patterned using a photoetching technique so as to cover the upper surface positions other than the through-holes 13. The embedded metal layer 20 is
The holes 13 are filled with metal such as Au by electrolytic plating. The first metal film 17 is for firmly adhering the embedded metal layer 20 to the through-hole hole 13, and the second metal film 18 is for serving as a plating base layer for the embedded metal layer 20. It is.

After the buried metal layer 20 is buried, the unnecessary resist film 19 and the first metal film 17 and second metal film 18 under it are removed with hot sulfuric acid or the like, and then as shown in FIG. In order to connect the hole-embedding metal layer 20 and the wiring electrode 10 on the second silicon layer 2, or to connect the wiring electrodes 10 to each other as necessary, the insulation Jl! Contact holes 21 are opened at predetermined locations of 14, a wiring electrode film 22 is formed in a predetermined pattern, and the upper surface thereof is further covered with a polyimide film layer 12. The contact hole 21 is formed by removing the insulating film 14 and the protective insulating film 11 at predetermined locations using a photo-etching technique or a selective etching technique. The wiring electrode film 22 is made of a single metal layer such as AI, Mo, W, etc. or multiple metal layers such as TiAu, Ticu, CrAu, CrNi, etc., and is formed over the entire upper surface of the insulating film 14 by sputtering, electron beam evaporation, etc. After coating, a predetermined pattern is formed by photoetching, selective etching, or the like. The polyimide film layer 12 is formed as an adhesive layer for adhering the third silicon layer 3, and is made of 800 Heat it to about ℃ and leave it in a semi-hardened state.

Then, in a separate process, MOS-FET 4.4
The third silicon layer 3 formed with the above is bonded to the upper layer of the second silicon layer 2, and as shown in FIG.
After covering the upper surface with a polyimide film layer 12 and opening a contact hole 23, an external electrode pad 24 is formed. The formation of the MOS-FETs 4 in the third silicon layer 3 is performed in the same process as in the case of the first silicon layer l and the second silicon layer 2, in which a hole 13 serving as a through hole is formed and a buried metal is formed. Layer 20 is embedded. This third silicon layer 3 is the same n-type semiconductor as the second silicon layer 2, so
A p-type impurity is diffused into the diffusion layer 6, and this MOS/FE
T4.4 becomes a p channel. The adhesion of the third silicon layer 3 is also performed in the same process as the case of adhesion of the second silicon layer 2. Since the polyimide film layer 12 on the upper surface of the third silicon layer 3 is formed not as an adhesive layer but as a surface protective layer, it is cured by heating to about 200° C. from the beginning. The contact hole 23 is formed by removing a predetermined portion of the polyimide film layer 12 using a photoetching technique or a selective etching technique. Electrode pad 2
4 is made of a metal film such as AI, Mo, W% Cu or a multilayer metal film such as TiAu, T1Cu, CrCu, etc., and after coating the upper surface of the polyimide film layer 12 by sputtering, electron beam thinning, etc. A predetermined pattern is formed using photoetching technology or selective etching technology.

The three-dimensional semiconductor integrated circuit of this embodiment is manufactured by the above-described process, and the MOS-FETs 4 formed separately in each silicon layer 1, 2, and 3 are buried in holes 13 forming through holes. The connection is made by an embedded metal layer 20.

Note that in this embodiment, the buried metal layer 20 in the through hole is
Although a metal film formed by electrolytic plating is used as the metal film, it is also possible to use an electroless plated film or a vapor-deposited film. Furthermore, in this embodiment, a MOS-IC was explained, but a C-IC was explained.
MOS-IC, bipolar transistor IC, etc. can also be configured in a similar manner.

[Embodiment 2] Another embodiment of the present invention will be described below based on FIGS. 11 to 17.

In this embodiment, the semiconductor single crystal layer to be bonded is made particularly thin to facilitate connection between each layer and to enable parallel processing of signals, thereby increasing processing speed.

In this embodiment, the first silicon layer 25 made of a p-type (100) wafer is used as the lower semiconductor single crystal layer which is the first layer, and the first silicon layer 25 is an upper layer for the first layer and a lower layer for the third layer. As the second semiconductor single crystal layer, p-type (100)
A second silicon layer 26 made of a wafer is used, a third silicon layer 27 made of a p-type (100) wafer is used as the third upper layer semiconductor single crystal layer, and the semiconductor single crystal layers are bonded together. A polyimide film is used as the adhesive layer, and M is used for the first silicon layer 25 and the second silicon layer 26.
This is a three-dimensional semiconductor integrated circuit that incorporates an OS/FET and a bipolar transistor in the third silicon layer 27.

To explain the manufacturing process of this three-dimensional semiconductor integrated circuit, first, as shown in FIG. 11, p-channel MOS-FETs 28 are provided at predetermined locations on the upper surface of the first silicon layer 25. The MOS-FET 28 is connected to the first silicon layer 25
SiO2, SiN that covers the top surface and has windows at designated locations
an insulating film 29 consisting of the like, p-type diffusion layers 30 and 30 formed at both ends of this window in the surface layer of the first silicon layer 25 and serving as a source and a train, respectively;
A gate oxide film 31 formed to cover the entire window 9, a gate polycrystalline silicon 1!32 formed only on the upper center surface of this gate oxide film 31, and a protective insulating film 33 covering these upper surfaces. and A formed in a predetermined pattern.
1% Mo, W, MoSi2, Ti5iz, WSi
A protective insulating film 3 made of 5iOz or the like covers the entire upper surface thereof.
5 is formed. This MOS-FET 28 is formed in the same process as the MOS-FET 4 in the first embodiment. Further, the upper surface of this protective insulating film 35 is covered with a polyimide film layer 36. As in the case of Example 1, this polyimide film layer 36 is also heated to about 80° C. to be in a semi-cured state for the subsequent bonding process.

Further, as shown in FIG. 12, MOS-FETs 28 are also formed in the second silicon layer 26, and holes 37 that will later become through holes and ohmic contacts I-Ji 38 are formed in the second silicon layer 26.
After forming, it is covered with a protective insulating film 33. MOS-F
The ET 28 is formed in the same process as the first silicon layer 25, but here the insulating film 29 and the diffusion layers 30 and 30 are formed.
After forming the gate oxide film 31 and the gate polycrystalline silicon film 32, the process moves to the next step. The hole 37 serving as a through hole is formed by photo-etching technology or selective etching technology, similar to the hole 13 in the first embodiment. At this time, use the resist film as a mask to apply effluent and nitric acid.
- may be etched, or Cr A Ll, T
i Fluoronitric acid, K using a metal film such as A u as a mask
Etching may be performed using an etchant such as OHlN a OH. The ohmic contact layer 38 is made of At, Pt.
, Pd, etc., first, the gate oxide film 31 on the diffusion layer 30 is removed by photo-etching technology, selective etching technology, etc., and then, for example, a thin AI film is deposited on the entire surface, and then photo-etching technology, selective etching technology, etc. 4 to remove the other A1 films leaving only on the diffusion layer 30.
It is formed by sintering at a temperature of about 00 to 500°C. The protective insulating film 33 is made of 5i02 or SiN, and the first
It is formed in the same process as the silicon layer 25.

Next, as shown in FIG. 13, in the same process as in Example 1, a protective substrate 40 made of glass, quartz plate, etc. is attached to the upper surface of the second silicon layer 26 with a wax layer 39 interposed therebetween. After smoothing the lower surface of the second silicon layer 26, a polyimide film layer 36 is formed. Second silicon layer 26
The lower surface of the second silicon layer 26 is smoothed to a thickness of 0.5 to 10 μm, and as shown in FIG. A groove is formed by etching, and the upper surface is
, etc., the processing can be stopped at the point where the smoothing stop film 41 is exposed during smoothing from the bottom surface, thereby making it possible to process a predetermined thickness with high precision. It can be done in degrees. The polyimide film layer 36 has a thickness of 80 mm as in the case of the first silicon layer 265.
Heat it to a semi-hardened state at about ℃.

The first MO3-FET 28 was formed as described above.
As shown in FIG. 15, the silicon layer 25 and the second silicon layer 26 are bonded to each other at predetermined positions, and the wax layer 39
After removing the protective substrate 40, the polyimide film layer 36 exposed at the bottom of the hole 37 is removed to form a through hole.

These steps are performed in the same steps as in Example 1.

When the hole 37 penetrates and a through hole is formed in this way, a contact hole is opened on the ohmic contact layer 38 and a predetermined pattern of wiring electrodes 42 is formed, as shown in FIG. , the entire upper surface is covered with a polyimide film layer 36. The wiring electrode 42 is a single metal film made of AI, Mo, W, etc. or TiAu, TiCu, CrCu.
It is formed by coating the entire upper surface with a metal film by sputtering, electron beam evaporation, etc., and then forming a predetermined pattern by photo-etching or selective etching. This wiring electrode 42
is easily connected to the diffusion layer 30 via the ohmic contact layer 38 formed in advance, and when forming the wiring electrode 42, high-temperature treatment such as sintering is not required, and a polyimide film with low heat resistance is used. No negative effects are exerted on the layer 36. Further, this wiring electrode 42 is connected to the hole 3.
Although the second silicon layer 26 is thin, there is no risk of disconnection, although the second silicon layer 26 is thin. As with the upper surface of the first silicon layer 25 and the lower surface of the second silicon layer 2G, the polyimide film layer 36 is heated to about 80° C. to be in a semi-cured state.

Finally, as shown in FIG. 17, the third silicon layer 27 on which the separate bipolar transistor 52 is formed is adhered to the upper layer of the second silicon layer 26, and the through hole of the hole 37 is passed through to form the electrode 42. Completed a three-dimensional semiconductor integrated circuit.

The formation of the bipolar transistor 52 in the third silicon layer 27 is a conventional and general method. First, an n+ diffusion layer 43 is formed by selective diffusion of sb from the upper surface of the third silicon layer 27, and then an n+ diffusion layer 43 is formed on the upper surface. An n-type single crystal 144 is formed by an epitaxial method, and a p-type diffusion layer 45 for separating each layer is formed by selective diffusion. Next, a p-type base layer 46 and an n-type emitter layer 47 are formed by selective diffusion, respectively, and the entire upper surface is covered with an insulating film 48. Then, a hole 37 to be a through hole is formed in the same manner as in the case of the second silicon layer 26, and a silicon layer is formed by low temperature vapor phase epitaxy, sputtering, etc.
The entire upper surface is covered with an insulating film 49 such as g. Finally, after forming contact holes 1-holes at corresponding positions in the p-type base layer 46, n-type emitter layer 47, and collector layer 50 by photo-etching technology and selective etching technology, the same process as in the case of the second silicon layer 26 is performed. In the process, an ohmic contact layer 51 is formed using AI, Pt, Pd, or the like. After the bipolar transistor 52 is formed in this way, the lower surface of the third silicon layer 27 is smoothed in the same process as the second silicon layer 26, and the second silicon layer 26 is formed through the polyimide film layer 36. It is adhered to the upper layer and electrodes 42 are formed in a predetermined pattern.

The three-dimensional semiconductor integrated circuit of this embodiment is manufactured by the process described in L, and the MOS/FET 28 and the /X Ibora transistor 52 formed separately in each of the silicon layers 25, 26, and 27 form through holes. The connection is made by an electrode 42 formed throughout the hole 37 .

In this embodiment, the electrode 42 is directly connected to the lower electrode 42 or the electrode 34 through a through hole, but as in the case of embodiment 1, the electrode 42 is connected directly to the lower electrode 42 or 34 through a through hole. It is also possible to form a metal layer.

In addition, Example 1 describes a three-dimensional semiconductor integrated circuit using MOS-FET, and Example 2 describes MOS-FET.
Although a three-dimensional semiconductor integrated circuit using FETs and bipolar transistors has been described, the types and combinations of elements to be formed can be freely selected, including C-MOS/IC.

Furthermore, in Examples 1 and 2, n-type or p-type (1
00) wafer was used, but the semiconductor type and crystal plane are not limited to this.

Further, in Examples 1 and 2, a polyimide film was used as the adhesive layer for each silicon layer, but the adhesive layer is not limited to this, and an epoxy resin, acrylic resin, or other adhesive layer may be used.

Furthermore, in Examples 1 and 2, the holes 13 and 37, which serve as through holes, were formed before adhering each silicon layer, but they can also be formed after adhering.

Further, in the first and second embodiments, a three-layer three-dimensional semiconductor integrated circuit is shown, but a three-dimensional semiconductor integrated circuit with four or more layers can also be obtained in the case of only 2N or by repeating the same process.

Furthermore, in Examples 1 and 2, each layer was composed of only a silicon layer, but a three-dimensional semiconductor integrated circuit could be constructed by combining it with a mixed crystal semiconductor such as GaAs or InP, or by using only a mixed crystal semiconductor. A three-dimensional semiconductor integrated circuit can also be constructed.

〔Effect of the invention〕

As described above, the three-dimensional semiconductor integrated circuit according to the present invention has the following features:
An upper semiconductor single crystal layer in which a circuit element is separately formed is bonded to the upper layer of a lower semiconductor single crystal layer in which a circuit element is formed, and a through hole is provided in the upper semiconductor single crystal layer, and a through hole is inserted through the through hole. In this structure, a circuit element formed in a lower semiconductor single crystal layer and a circuit element formed in an upper semiconductor single crystal layer are connected through an electrode layer.

As a result, in the present invention, the crystallization of the semiconductor single crystal layer of each layer and the formation of the circuit elements can be performed in separate steps.
The following effects will be produced.

Since a material with good crystallinity, such as a silicon wafer, can be used for each semiconductor single crystal layer, variations in the characteristics of the formed circuit elements are reduced, making circuit design easier and improving yield. Furthermore, since a single crystal with sufficient thickness can be obtained, it becomes easy to form bipolar transistors and the like using bulk. Furthermore, since each layer can be made into a uniform single crystal, there are no grain boundaries, etc.
This makes it possible to form circuit elements with high density.

Furthermore, since the circuit elements of each layer are formed separately for each layer, the process for conventional two-dimensional semiconductor integrated circuits can be used as is, making product development and manufacturing easier. Furthermore, instead of melting and recrystallizing each layer in turn and stacking them up, each layer can be processed in parallel and in separate processes using traditional methods, and many bonding processes can be performed at once. Therefore, productivity is improved and manufacturing can be completed in a short period of time.

[Brief explanation of the drawing]

1 to 10 show one embodiment of the present invention, and FIG. 1 shows a vertical cross-sectional portion 1E of a three-dimensional semiconductor integrated circuit.
2 to 10 are vertical sectional partial front views showing the manufacturing process of a three-dimensional semiconductor integrated circuit, and FIGS. 11 to 17 show other embodiments of the present invention. 1
1 to 16 are vertical cross-sectional partial front views showing the manufacturing process of a three-dimensional semiconductor integrated circuit, and FIG. 17 is a vertical cross-sectional partial front view of the three-dimensional semiconductor integrated circuit. 1 and 25 are the first silicon layer (lower semiconductor single crystal layer), 2
・26 is the second silicon layer (upper layer semiconductor single crystal layer and lower layer semiconductor single crystal layer), 3 and 27 are the third silicon layers (upper layer semiconductor single crystal layer), 4 and 28 are MOS-FET (circuit element), lO・34 and 42 are electrodes (electrode layers), 12 and 3
6 is a polyimide film layer, 13 and 37 are holes (through holes), 20 is a buried metal layer (electrode N), 22 is a wiring electrode film (electrode N), and 52 is a bipolar transistor (circuit element).

Claims (1)

[Claims] 1. An upper semiconductor single crystal layer in which circuit elements are separately formed is bonded to the upper layer of the lower semiconductor single crystal layer in which circuit elements are formed, and a through hole is provided in the upper semiconductor single crystal layer, and the through hole is A three-dimensional semiconductor integrated circuit characterized in that a circuit element formed in a lower semiconductor single crystal layer and a circuit element formed in an upper semiconductor single crystal layer are connected by an electrode layer.