DE19516487C1 - Vertical integration process for microelectronic system - Google Patents

Abstract

The vertical integration process uses 2 separately prepared substrates (1,8), each incorporating at least one circuit structure layer (3,10) and at least one metallisation plane (5,10), brought together to provide a substrate stack. The thickness of one substrate (1) is reduced until metallised holes formed in this substrate are reached, with subsequent deepening of the holes until the metallisation of the metallisation plane of the other substrate is reached for formation of an electrical connection between the substrate metallisation planes.

Description

The invention relates to a method for vertical integration of microelectronic Systems. Vertical connections enable three-dimensional production integrated circuits. The advantages of a three-dimensional integrated microelectronic systems are u. a. the same design rules achievable higher packing densities and switching speeds against about two-dimensional systems (planar technology). The latter is on the one hand due to shorter cable routes between the individual components or circuits, on the other hand by the possibility of parallel informa tion processing. The increase in the performance of the system is at Realization of a connection technology with freely selectable top ink gratable vertical contacts optimal.

The following methods are known for producing three-dimensional circuit arrangements with freely selectable vertical contacts:
Y. Akasaka, Proc. IEEE 74 (1986) 1703, suggests to deposit and recrystallize polycrystalline silicon on a finished processed component layer so that further components can be manufactured in the recrystallized layer. Disadvantages of this method are the yield-reducing de-gradation of the components in the lower level due to the high thermal load during the recrystallization process, and the necessary serial processing of the overall system. The latter, on the one hand, requires a correspondingly long throughput time in production and, on the other hand, results in a reduction in yield by adding up the process-related failures. Both increase the manufacturing costs considerably compared to processing the individual levels separately from one another in different substrates.

No. 4,902,637 describes a method for producing a three-dimensional semiconductor arrangement described in which an insulation layer on a finished component layer and a further component layer can be applied. Components on top of each other the different layers are directly through the insulation layer via via holes connected to each other to keep the lines short. This method is disadvantageous however, here too, as with the method already mentioned, the serial processing of the Ge entire system and the associated long lead times during production.

From Y. Hayashi et al., Proc. 8th Int. Workshop on Future Electron Devices, 1990, page 85, it is known, first the individual component levels separately from each other in different To manufacture substrates. The substrates are then thinned to a few micrometers, with Front and rear contacts are provided and connected vertically by means of a bonding process. However, special processes are necessary for the provision of the front and rear contacts, which are not provided for in standard semiconductor manufacturing (CMOS), namely machining MOS incompatible materials (e.g. gold) and rear structuring of the substrate.

Another method for producing three-dimensional circuit arrangements is in the US 4,612,083. In the process, the individual component levels are separated processed from each other in different substrates. With an insulation layer and an adhesive sion layer on the component levels are conductive connections via contact holes that exposed on the surface of the adhesive layer, to the individual components of the respective Manufactured substrate. The surfaces of the two substrates are finally covered by the adhesi onsschichten connected so that the exposed contacts touch.

When connecting two fully processed component substrates, an exact adjustment of the two substrates via alignment marks required before joining. Should be a back structuring can be avoided, so the adjustment marks were previously in the area of the front of the substrates applied and the adjustment is carried out using the infrared transmitted light method (known, for example from so-called flip-chip bonding). The one at the time of assembly Layer sequence of the upper substrate closes an optical transmitted light adjustment of the components planes to each other in the visible spectral range.  

However, the use of the infrared transmitted light process requires one in semiconductor production unusual special equipment, in particular a bonding device with integrated infrared transmission adjustment tion. The substrates to be adjusted must also only have polished surfaces (Handling substrate and lower component substrate), since otherwise the infrared light at the interface Chen is diffusely scattered and therefore the alignment marks can not be displayed. The Ju bull accuracy is even when using polished surfaces  Chen due to the longer wavelength of the infrared light compared to visible light is about a factor of two smaller than with adjustment in sight ble spectral range, so that the packing density of the vertical connection is only approx. 25% of the value that can be achieved with visible light. About that In addition, the complex layer structure of an integrated circuit also helps a large number of interfaces and the associated reflections further reduction of the adjustment accuracy in the transmitted light method. Farther This method limits the freedom of design and the Substrate selection because of a good beam in the areas of the alignment marks lung transmission is required.

Finally, JP 63-213943 A2 describes a method for vertical integration mi Croelectronic systems known in which the processing of two components level in different substrates (top and bottom substrate) he follows. In the process, the top substrate is first versed with vial holes hen that through all layers with circuit structures of this substrate penetrate. The top substrate is then ver front with an auxiliary substrate bound, thinned on the back and on the front of the bottom substrate brought. The auxiliary substrate is removed and the existing via holes opened up to the metallization of the bottom substrate. The via holes are filled and the connection to the metallization level of the top substrate is made via contact holes. Thinning the top substrate before closing However, joining with the bottom substrate requires special handling technology for the top substrate. The handling technique consists in applying and later removal of an auxiliary substrate (handling substrate). These additional Manufacturing steps increase manufacturing costs. The removal of the Auxiliary substrates after thinning the top substrate also reduces the Yield of the components, since component layers are damaged in the process can.

Another feature of the method is that after the together add the structuring of the substrates to a component stack Compound metallization based on deposition of metallic material  the surface of the upper component level was generated is required. The lithography steps necessary for this bring u. a. the following after share with yourself: High demands on the coating and lighting technology due to the non-standard substrate material (stack of thinned and glued substrates) as well as reduction in yield in lithography for the Metal structuring due to the strong topography leading via technology as a result of inhomogeneity of lacquer thickness and lacquer benet problems up to lacquer tears.

The disadvantages of the methods mentioned are therefore particularly high Throughput times of the substrates during production, high production costs, off loot reduction or in the necessary application of special processes, that are incompatible with standard semiconductor manufacturing.

The invention is therefore based on the object of a method for vertical insertion tegration with freely selectable vertical contacts - that with CMOS- compatible standard semiconductor technologies is feasible and high Yield.

This object is achieved according to the invention with the method according to claim 1 solves. Special features of the process are the subject of the sub Expectations.

In the method according to the invention, the individual component layers are in different substrates processed independently and merged below. First, the finished substrate (first substrate; hereinafter referred to as top substrate) with one or several component layers and metallization levels, the components lay in the finished integrated circuit structure above the component mentelagen another substrate (second substrate; in the following as Bottom substrate designated) should lie, provided with vias on the front.  

For this purpose, a masking layer can preferably be used, which is preferably takes on a planarizing function or is planarized.

The vial holes are opened at the point (e.g. by etching) at which later on vertical contact between metallization layers of the top substrate and the Bottom substrates should be created, and penetrate all in the top substrate existing component layers and metallization levels. The via holes, the preferably according to claim 2, the metallization layer to be contacted open, preferably end a few microns below the component layers the top substrate, when using an SOI substrate, preferably on the buried oxide layer (claim 4).

Then another finished substrate with one or more meh Other component layers and metallization levels, the bottom substrate, with connected to the top substrate. For this purpose, preferably according to claim 7 Front of the bottom substrate, d. H. the surface of the upper construction element layer of the bottom substrate, with a transparent adhesive layer verse hen. The adhesive layer can simultaneously passivate and / or planarize Take over function (claim 8). Alternatively, according to claim 9 dispenses with the adhesive layer, preferably according to claim 10, a planarian rende or planarized layer generated, and after appropriate surface activation directly binds to the surface of the upper components Topage of the top substrate are produced (direct bonding process). Then top substrate and bottom substrate are aligned and the front of the top substrate connected to the front of the bottom substrate. The Adjustment can be done with the help of split optics based on alignment marks in the visible spectral range take place (claim 2). The alignment marks can here in the top substrate and in the bottom substrate in each case in the uppermost metallization level or contained in the top substrate analogous to the via holes, d. H. preferably by etching adjustment structures from the front of the Top substrates.

The top substrate connected to the bottom substrate is then removed from the back is thinned to the via holes. The thinning can, for example se by wet or dry chemical etching and / or by mechanical  and / or chemomechanical grinding take place (claim 5). When used The SOI silicon can be used as a top substrate here Etch stop serve (claim 6).

The via holes that are now open are covered by the remaining layers (e.g. Adhesive layer and passivation layer of the bottom substrate) except for the metal layer of a metallization layer of the bottom substrate is deepened (e.g. by etching). No lithography step is required here, as with Vialö Structured top substrate serves as a mask (so-called hard mask; claim 11).

The electrical contact between the me tallization of a metallization level of the top and the metallization of a Metallization level of the bottom substrate produced.

For this purpose, metallic material is preferably on the Deposited substrate stack, which the via holes through the metallization of the top substrate down to the metallization of the bottom substrates covered, and then using an anisotropic etching process or a chemomechanical grinding process on the substrate surface removed so that only material remains in the via holes (so-called plug- Technology). With these metallic plugs, vertical integration is the building Element layers made from top and bottom substrates. In conclusion by applying a dielectric layer to the front of the device passages are passivated.

This embodiment enables the implementation of the invention Process without lithography steps on the assembled substrate stack. This simplifies the process and additionally improves its yield increases.

The vertical integration with a further component level can be according to the described methods can be realized by the present substrate sta pel analogous to a bottom substrate with the metallic plugs as bottom metals treatment is treated. The vertical connection between two or more Component levels are determined by the design of the corresponding metal levels of implementation.  

Due to the processing of individual component layers separately in different substrates (parallel processing) results with the inventive method a significant reduction in throughput times the manufacture of the vertical circuit structure and thus a reduction in Manufacturing costs.

In the method according to the invention, advantageously only CMOS Compatible technologies used, especially on the back structuring of the substrates can be dispensed with.

The manufacture of the via holes on the individual substrate (i.e. on disks level) enables this process step to be included in the process sizing of the individual substrate (parallel processing). The waiver Auxiliary substrates and the avoidance of any lithography steps together quantity-added component stacks advantageously leads to a reduction throughput times and an increase in yield.

Another advantage of the method is that for individual adjustment Component layers on top of each other are split optics in the visible spectral range can be used. Therefore, in contrast to transmitted light methods neither the layer sequence below the alignment marks in the top substrate nor that Layer sequence below the alignment marks in the bottom substrate should be transparent. A higher adjustment accuracy and thus a higher packing density are thus achievable in comparison to infrared transmission methods. The application of Alignment marks can already be used when processing the individual Substrates are made in the topmost component layer of each substrate and does not require additional techniques.

The method according to the invention is described in the following using an embodiment Example and the drawings explained in more detail.

Show:  

FIG. 1 shows an example of the process flow of the method of the invention with reference to the structures of a top and a bottom substrate after different processing steps; For this:

FIG. 1a is a Topsubstrat with component planes Dreilagenmetallisierung and passivated surface;

Fig. 1b the top substrate

• - plasma oxide deposition,
• - applying a paint mask,
• - Photo technology for the via holes, and
• - anisotropic etching of the via holes;

Fig. 1c the top substrate after

• - paint removal and
• - Trench etching of the via holes down to the silicon;

Fig. 1d the joining of top and bottom substrates after

• Passivation of the surface of the bottom substrate and
• - Application of an adhesive layer on the bottom substrate;

Fig. 1e the top and bottom substrate (the substrate stack) after

• - adjusted assembly (gluing) and
• - Thin up on the side of the top substrate the via holes;

Fig. 1f the substrate stack after the recessing the via holes to a metallization of the bottom substrate;

Fig. 1g after the substrate stack

• - Deposition of a barrier and adhesive layer and
• - subsequent deposition of metallic material;

Fig. 1h the substrate stack by

• - grinding the stack surface and
• - application of a protective layer;

In this example, the top substrate 1 is a bulk silicon wafer ( 2 : silicon) with completely processed MOS circuits in the chip level 3 and three-layer metalization, passivated with an oxide / nitride protective layer 4 , as shown in FIG. 1a. The metallization 5 of the top metallization level is, for. B. an aluminum alloy. Undoped and doped oxide layers are located below the metallization level. As a mask for later dry etching, a layer serving as a hard mask, such as e.g. B. plasma oxide 6 from divorced and carried out a photo technique for the via holes 7 . With the aid of a resist mask 18 , the plasma oxide 6 , the oxide / nitride protective layer 4 , the metallization 5 and the underlying oxide layers of the chip level 3 are etched anisotropically. The result is shown in Fig. 1b. After the paint has been removed, the so-called trench etching process etches approximately 10 μm deep into the silicon 2 (see FIG. 1c). When using SOI material as the top substrate 1 is etched up to the surface of the buried oxide (SiO₂ as an etch stop).

On the bottom plate 8 ( 9 : silicon) with processed MOS circuits in the bottom 10 chip level, three-layer metallization (metallization 11 ) and passivation 12 , a polyimide layer 13 is spun up as an inter-chip adhesive, so that the surface topography is leveled. Then the bonding of top 1 and bottom substrate 8 (polyimide layer 13 on plasma oxide 6 ) takes place in a disk bonding device with split optic adjustment, as is standardly used in flip-chip bonding (cf. FIG. 1d).

After the optically adjusted gluing of the top 1 and bottom substrate 8 , the substrate stack 14 that is now present is thinned mechanically, wet-chemically and chemomechanically until the via holes 7 are open (cf. FIG. 1e). If SOI material is used instead of bulk silicon 2 , the first step is to etch down to the surface of the buried oxide (etch stop: SiO₂) and then remove the oxide layer (etch stop: silicon). After thinning, the substrate stack 14 can be processed like a standard wafer. The polyimide layer 13 and the protective layer 12 over the metal 11 of the bottom metalization are anisotropically etched in the via holes with the silicon 2 as a hard mask. The metallization 11 serves as an etch stop. The result is shown in Fig. 1f.

For electrically connecting the Topmetallisierung 5 and the Bottommetallisie tion 11 is first deposited a titanium nitride layer 15 as the adhesion and barrier layer for the subsequent tungsten metallization 16 (by W Deposition).

With the help of chemomechanical grinding with a CMP device, the tungsten (titanium nitride layer 15, 16 is removed from the surface of the silicon 2 , so that the remaining isolated tungsten / titanium nitride "plugs" the so-called plugs) the vertical connection between top and bottom components Finally, to passivate the component stack, an oxide / nitride protective layer 17 is deposited ( FIG. 1h).

Claims (12)

1. Procedure for the vertical integration of microelectronic systems with the following process steps:

• - Providing a first substrate ( 1 ) containing one or more first layers ( 3 ) with circuit structures and at least one first metallization level with a metallization ( 5 ) in the area of a first main surface;
• - Opening of via holes ( 7 ) in a first step in the area of the first main surface of the first substrate, the via holes penetrating all first layers with circuit structures and the metallization ( 5 );
• - Providing a second substrate ( 8 ), which contains at least a second layer ( 10 ) with circuit structures and at least one second metallization level with a metallization ( 11 ) in the region of a second main surface;
• - connecting the first substrate ( 1 ) to the second substrate ( 8 ), the side of the first main surface of the first substrate and the side of the second main surface of the second substrate being brought together in an adjusted manner, so that a substrate stack ( 14 ) is formed;
• - Thinning the substrate stack ( 14 ) on the side of the first substrate ( 1 ) until the via holes ( 7 ) are open on this side;
• - Deepening the existing via holes ( 7 ) in a second step up to the metallization ( 11 ) of the second metallization level of the second substrate ( 8 );
• - Establish an electrically conductive connection between the metallization ( 5 ) of the first and the metallization ( 11 ) of the second metallization level via the recessed via holes ( 7 ).

2. The method according to claim 1, characterized in that the adjusted merging of the first and second substrates by means of a split optics in the visible spectral range on the basis of adjustment marks that surface the first substrate ( 1 ) in the region of the first Hauptflä and the second substrate ( 8 ) ent in the area of the second main surface. 3. The method according to any one of claims 1 to 2, characterized, that the via holes are opened by etching. 4. The method according to claim 3, characterized, that the via holes in the first step with an anisotropic etch ver drive through all the first layers with circuit structures and then with a trench etching process up to about 10 µm below the first layers are opened, a buried oxide layer serving as an etch stop can. 5. The method according to any one of claims 1 to 4, characterized in that the thinning of the substrate stack ( 14 ) takes place by means of etching and / or grinding. 6. The method according to claim 5, characterized in that when using an SOI substrate as the first substrate ( 1 ) the thinning by etching to the buried oxide layer of the SOI substrate is carried out as an etch stop layer and subsequent removal of this oxide layer with the substrate material as an etch stop layer . 7. The method according to any one of claims 1 to 6, characterized, that connecting the substrates by means of a transparent adhesive layer takes place, which is applied to the second main surface of the second substrate becomes. 8. The method according to claim 7, characterized, that uses a passivating and / or planarizing adhesive layer becomes. 9. The method according to any one of claims 1 to 6, characterized, that the bonding of the substrates by means of direct bonding (Direct Bonding Procedure). 10. The method according to claim 9, characterized, that before connecting a planarizing and / or planarized Layer is generated. 11. The method according to any one of claims 1 to 10, characterized in that the deepening of the via holes ( 7 ) is carried out in the second step by anisotropic etching, the substrate material of the first substrate ( 1 ) serves as a hard mask. 12. The method according to any one of claims to 1 to 11, characterized in that the production of an electrically conductive connection between the first and the second metallization level comprises the following process steps:

• - Deposition of an adhesive and barrier layer in the via holes ( 7 );
• - deposition of a metallic material in the vial holes;
• - Chemomechanical grinding of the adhesive and barrier layer and the metallic material from the surface of the substrate stack ( 14 ).