JP3013786B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JP3013786B2
JP3013786B2 JP23962796A JP23962796A JP3013786B2 JP 3013786 B2 JP3013786 B2 JP 3013786B2 JP 23962796 A JP23962796 A JP 23962796A JP 23962796 A JP23962796 A JP 23962796A JP 3013786 B2 JP3013786 B2 JP 3013786B2
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor substrate
layer
silicon wafer
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP23962796A
Other languages
Japanese (ja)
Other versions
JPH1092778A (en
Inventor
久 佐脇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23962796A priority Critical patent/JP3013786B2/en
Publication of JPH1092778A publication Critical patent/JPH1092778A/en
Application granted granted Critical
Publication of JP3013786B2 publication Critical patent/JP3013786B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which reduces the crack and the chipping of a silicon wafer at the time of using the large silicon wafer and which can obtain a satisfactory ohmic contact from the back side of the silicon wafer. SOLUTION: A diffused silicon wafer is polished, an Au thin film is deposited on the back side of the silicon wafer, heat treatment is executed on it and a metallic silicide layer is formed on the back side of the silicon wafer (S1-S4). The Au thin film layer is deposited on the metallic silicide layer, and a conductive tape made of epoxy resin is adhered on the Au thin film layer (S5 and S6). Then, heat treatment is executed and the silicon wafer is rigidly and closely adhered to the conductive tape made of epoxy resin. Respective chips are separated by dicing and the semiconductor device is assembled by using the respective chips (S7 and S8).

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体装置の製造方
法に関し、特に厚さの薄い半導体基板を用い、その半導
体基板の裏面から電極をとる必要のある半導体装置の製
造に関するものである。The present invention relates to a method for manufacturing a semiconductor device.
More particularly, the present invention relates to a method of manufacturing a semiconductor device which requires a thin semiconductor substrate and requires electrodes from the back surface of the semiconductor substrate.

【０００２】[0002]

【従来の技術】半導体装置に供する半導体基板としては
シリコンの単結晶からスライスした基板に対して研磨及
び研削等を施し、０．５ｍｍ程度に仕上げたシリコンウ
エハが用いられている。通常、このシリコンウエハに対
して公知の拡散技術やリソグラフィ技術等を用いて素子
を形成し、ダイシングやボンディング等の組立て工程を
経て半導体装置を製造している。2. Description of the Related Art As a semiconductor substrate used for a semiconductor device, a silicon wafer obtained by subjecting a substrate sliced from a single crystal of silicon to polishing, grinding, or the like and finishing it to about 0.5 mm is used. Usually, a semiconductor device is manufactured by forming an element on the silicon wafer by using a known diffusion technique, lithography technique, or the like, and performing an assembling process such as dicing or bonding.

【０００３】シリコンウエハは製造する半導体装置の構
造上や特性上の問題から、その半導体装置に組み込む前
に、さらに研磨（又は、研削）して所定の厚みまで薄く
する必要がある。一般に、その厚みは０．２〜０．４ｍ
ｍ程度である。特に、一部の薄型パッケージではその半
導体基板の厚さが０．ｌｍｍ程度まで薄くする必要があ
る。[0003] Because of the problems in the structure and characteristics of the semiconductor device to be manufactured, the silicon wafer must be further polished (or ground) to a predetermined thickness before being incorporated into the semiconductor device. Generally, its thickness is 0.2-0.4m
m. In particular, in some thin packages, the thickness of the semiconductor substrate is set to 0. It is necessary to reduce the thickness to about 1 mm.

【０００４】また、トランジスタやダイオード等のディ
スクリート系半導体装置では半導体基板の裏面から電極
をとっているので、半導体基板における抵抗値を低下さ
せるためにできるだけ薄くすることが望ましい。さら
に、ディスクリート系半導体装置ではシリコンウエハの
裏面からの良好なオーミックコンタクトが必要となる。Further, in a discrete semiconductor device such as a transistor or a diode, an electrode is taken from the back surface of the semiconductor substrate. Therefore, it is desirable to make the semiconductor device as thin as possible in order to reduce the resistance value of the semiconductor substrate. Further, a discrete semiconductor device requires good ohmic contact from the back surface of the silicon wafer.

【０００５】この良好なオーミックコンタクトを得るた
め方法としては一般的に使用される方法として、金薄膜
を用いてリードフレームにダイボンディングする方法
と、予めシリコン基板の裏面に金属シリサイド層を形成
した後、さらに金属層を形成してＡｇ入りの導電性接着
剤（通称Ａｇペースト）等を用いて半導体装置を製造す
る方法とがある。[0005] As a method for obtaining this good ohmic contact, there are generally used a method of die bonding to a lead frame using a gold thin film and a method of forming a metal silicide layer on the back surface of a silicon substrate in advance. Further, there is a method in which a metal layer is formed and a semiconductor device is manufactured using a conductive adhesive containing Ag (commonly called an Ag paste).

【０００６】これら方法ではディスクリート系半導体装
置に限らず、一部の半導体集積回路装置において裏面か
らのオーミックコンタクト性を付与することで、半導体
基板の表面から電流パスをとることができない場合に半
導体基板の裏面から電流パスがとれるようになるという
ラッチアップ動作の改善が確認されている。[0006] These methods are not limited to the discrete type semiconductor device, but are provided with an ohmic contact from the back surface in some semiconductor integrated circuit devices, so that a current path cannot be taken from the front surface of the semiconductor substrate. It is confirmed that the current path can be taken from the back surface of the latch-up operation.

【０００７】一方、半導体基板のサイズ（直径）は市場
からの強いプライスダウンの要求や生産効率の向上等を
目的として、１００ｍｍから１２５ｍｍ，１５０ｍｍへ
とますます大きくなっている。しかしながら、ディスク
リート系半導体装置では半導体基板サイズが大きくなつ
ても、シリコン基板の厚みを変えることができないた
め、半導体基板のサイズの大型化が進まず、生産効率の
低下を招いている。On the other hand, the size (diameter) of a semiconductor substrate is increasing from 100 mm to 125 mm and 150 mm for the purpose of requesting a strong price reduction from the market and improving production efficiency. However, in a discrete semiconductor device, the thickness of the silicon substrate cannot be changed even if the size of the semiconductor substrate is increased. Therefore, the size of the semiconductor substrate is not increased and the production efficiency is reduced.

【０００８】[0008]

【発明が解決しようとする課題】上述した従来の半導体
装置の製造方法では、製造する半導体装置の構造上や特
性上の問題からその半導体装置に組み込む前に研磨（又
は、研削）して所定の厚みまで薄くする必要があるの
で、薄い基板を使用しなければならない半導体装置に使
用するシリコンウエハの大型化にともなって、シリコン
ウエハの割れや欠けがますます発生しやすくなってい
る。In the above-described conventional method of manufacturing a semiconductor device, due to problems in the structure and characteristics of the semiconductor device to be manufactured, the semiconductor device is polished (or ground) before being incorporated into the semiconductor device. Since it is necessary to reduce the thickness of the silicon wafer, a silicon wafer used for a semiconductor device that requires the use of a thin substrate has become larger, and the silicon wafer has been more likely to be cracked or chipped.

【０００９】その対策として、半導体基板の裏面にエポ
キシ樹脂等の有機物層等を形成して半導体基板を補強す
る方法が提案されており、その方法を用いることで半導
体基板の割れや欠けの確率を大幅に減少させることが期
待され、ダイボンディング用の樹脂の代わりになること
も期待されている。この方法については、特開昭６３−
３７６１２号公報に開示されている。As a countermeasure, a method has been proposed in which an organic layer such as an epoxy resin is formed on the back surface of the semiconductor substrate to reinforce the semiconductor substrate. By using this method, the probability of cracking or chipping of the semiconductor substrate is reduced. It is expected to be greatly reduced, and is expected to be a substitute for resin for die bonding. This method is disclosed in
No. 37612.

【００１０】しかしながら、上記の方法では半導体基板
の裏面にエポキシ樹脂等の有機物層等を形成しているの
で、半導体基板の裏面からのオーミックコンタクトを実
現することが期待できないため、半導体基板の裏面から
電極をとる構造の半導体装置や半導体基板の裏面からの
オーミックコンタクト性を付与することで特性の改善が
期待できる半導体装置に適用することができない。ま
た、この方法では有機物層の塗布に際して、工程数が多
くなるという問題がある。However, in the above-described method, since an organic material layer such as an epoxy resin is formed on the back surface of the semiconductor substrate, it is not expected to realize ohmic contact from the back surface of the semiconductor substrate. It cannot be applied to a semiconductor device having an electrode structure or a semiconductor device that can be expected to have improved characteristics by providing ohmic contact from the back surface of a semiconductor substrate. In addition, this method has a problem that the number of steps is increased in applying the organic material layer.

【００１１】そこで、本発明の目的は上記の問題を解消
し、大型のシリコンウエハを使用する際のシリコンウエ
ハの割れや欠けを低減することができ、シリコンウエハ
の裏面から良好なオーミックコンタクトを得ることがで
きる半導体装置の製造方法を提供することにある。Therefore, an object of the present invention is to solve the above-mentioned problems, to reduce cracking or chipping of a silicon wafer when using a large silicon wafer, and to obtain a good ohmic contact from the back surface of the silicon wafer. It is an object of the present invention to provide a method of manufacturing a semiconductor device that can be used.

【００１２】[0012]

【課題を解決するための手段】本発明による半導体装置
の製造方法は、シリコン半導体基板部と電気伝導性が確
保された導電層を含むテープとを張り合わせる工程と、
前記導電層を前記シリコン半導体基板部から剥がすこと
なく半導体装置のダイボンディングを行う工程とを備
え、前記シリコン半導体基板部を製造する工程が、シリ
コン半導体基板を少なくとも研磨にて薄くする工程と、
前記シリコン半導体基板の裏面に第１の金属層を形成す
る工程と、前記第１の金属層が形成された前記シリコン
半導体基板に熱処理を施して金属シリサイド層を形成す
る工程と、前記金属シリサイド層上に第２の金属層を形
成する工程とからなっている。 A semiconductor device according to the present invention.
Manufacturing method is to ensure electrical conductivity with the silicon semiconductor substrate.
Laminating the tape containing the retained conductive layer,
Peeling the conductive layer from the silicon semiconductor substrate portion
Process for die bonding of semiconductor devices
The step of manufacturing the silicon semiconductor substrate portion comprises
A step of thinning the semiconductor substrate at least by polishing,
Forming a first metal layer on the back surface of the silicon semiconductor substrate;
And the silicon on which the first metal layer is formed.
Heat-treating a semiconductor substrate to form a metal silicide layer
Forming a second metal layer on the metal silicide layer.
And the process of forming.

【００１３】[0013]

【００１４】上記の如く、予め裏面に金属シリサイド層
及び金属層が形成され、かつその金属層上に導電性層を
有するテープが貼付されたシリコンウエハを半導体装置
の前処理で使用するとともに、そのテープの導電性層を
ダイボンディングの接着剤として組み立てることで、シ
リコンウエハの裏面からのオーミックコンタクトを確保
すると同時に、半導体基板を大型化するとともにその基
板の厚さを薄くしても、その半導体基板の割れや欠けを
減少させることが可能となる。As described above, a silicon wafer on which a metal silicide layer and a metal layer are previously formed on the back surface and a tape having a conductive layer is adhered on the metal layer is used for pretreatment of a semiconductor device. By assembling the conductive layer of the tape as an adhesive for die bonding, it is possible to secure ohmic contact from the backside of the silicon wafer, and at the same time to increase the size of the semiconductor substrate and reduce the thickness of the semiconductor substrate. Cracks and chips can be reduced.

【００１５】[0015]

【発明の実施の形態】次に、本発明の一実施例について
図面を参照して説明する。図１は本発明の一実施例の構
成を示す断面図である。図において、本発明の一実施例
による半導体基板はシリコン半導体基板１と、シリコン
半導体基板１の内部に形成された金シリサイド層２と、
シリコン半導体基板１の外部に形成されたＡｕ（金）薄
膜層３と、導電性テープの一部の銀入り接着剤層４と、
導電性テープのベーステープ５とから構成されている。
６はダイシング工程における切り離し溝である。Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing the configuration of one embodiment of the present invention. In the figure, a semiconductor substrate according to one embodiment of the present invention includes a silicon semiconductor substrate 1, a gold silicide layer 2 formed inside the silicon semiconductor substrate 1, and
An Au (gold) thin film layer 3 formed outside the silicon semiconductor substrate 1, a silver-containing adhesive layer 4 as a part of a conductive tape,
And a base tape 5 of a conductive tape.
Reference numeral 6 denotes a separation groove in the dicing step.

【００１６】図２は本発明の一実施例による半導体装置
の製造工程を示すフローチャートである。これら図１及
び図２を用いて本発明の一実施例による半導体装置の製
造工程について説明する。FIG. 2 is a flowchart showing the steps of manufacturing a semiconductor device according to one embodiment of the present invention. The manufacturing process of the semiconductor device according to one embodiment of the present invention will be described with reference to FIGS.

【００１７】まず、拡散済みのシリコン半導体基板１を
１８０μｍに研磨し（図２の工程Ｓ１，Ｓ２）、しかる
後にＡｕ薄膜（２０００Å）を蒸着し（図２の工程Ｓ
３）、４５０℃３０分の熱処理を施して基板裏面に金シ
リサイド層２を形成する（図２の工程Ｓ４）。さらに、
この金シリサイド層２の上にＡｕ薄膜（２０００Å）層
３を蒸着する（図２の工程Ｓ５）。First, the diffused silicon semiconductor substrate 1 is polished to 180 μm (steps S1 and S2 in FIG. 2), and then an Au thin film (2000 °) is deposited (step S2 in FIG. 2).
3) A heat treatment at 450 ° C. for 30 minutes is performed to form a gold silicide layer 2 on the back surface of the substrate (Step S4 in FIG. 2). further,
An Au thin film (2000 °) layer 3 is deposited on the gold silicide layer 2 (step S5 in FIG. 2).

【００１８】上記の処理を施したシリコン半導体基板１
のＡｕ薄膜層３の上にエポキシ樹脂製の導電性テープを
貼り付ける（図２の工程Ｓ６）。このエポキシ樹脂製の
導電性テープは厚さ５０μｍのエポキシ樹脂製の接着剤
層４と、厚さ１００μｍのエポキシ樹脂製のベーステー
プ５とからなる。The silicon semiconductor substrate 1 which has been subjected to the above processing
A conductive tape made of epoxy resin is attached on the Au thin film layer 3 (step S6 in FIG. 2). The epoxy resin conductive tape includes an epoxy resin adhesive layer 4 having a thickness of 50 μm, and an epoxy resin base tape 5 having a thickness of 100 μm.

【００１９】この接着剤層４には約５０ｗｔ％の銀（Ａ
ｇ）微粒子が含まれており、その銀微粒子で電気伝導性
を確保している。しかる後、シリコン半導体基板１とエ
ポキシ樹脂製の導電性テープとを強固に密着させるため
に、１２０℃で３０分熱処理を行う（図２の工程Ｓ
７）。その後、公知の技術であるダイシングを行って各
チップに分離し（図２の工程Ｓ８）、そのチップに対し
て公知の技術であるダイボンディング、ワイアボンディ
ング、樹脂封入、仕上げ工程を行うことで、半導体装置
を組立てる（図２の工程Ｓ９）。The adhesive layer 4 has about 50 wt% of silver (A
g) Fine particles are contained, and the silver fine particles ensure electrical conductivity. Thereafter, heat treatment is performed at 120 ° C. for 30 minutes in order to firmly adhere the silicon semiconductor substrate 1 and the conductive tape made of epoxy resin (Step S in FIG. 2).
7). Thereafter, dicing as a known technique is performed to separate each chip (step S8 in FIG. 2), and the chip is subjected to a known technique such as die bonding, wire bonding, resin encapsulation, and a finishing step. The semiconductor device is assembled (step S9 in FIG. 2).

【００２０】また、ダイシング工程ではエポキシ樹脂製
の接着剤層４（導電層）はチップとともに、つまりシリ
コン半導体基板１、金シリサイド層２、Ａｕ薄膜層３と
ともに完全に切り離すが、ベーステープ５は切り離さず
につなげたままとする（図１参照）。In the dicing step, the adhesive layer 4 (conductive layer) made of epoxy resin is completely separated together with the chip, that is, the silicon semiconductor substrate 1, the gold silicide layer 2, and the Au thin film layer 3, but the base tape 5 is separated. (See FIG. 1).

【００２１】また、その後のダイボンディング工程はチ
ップにエポキシ樹脂製の導電層４を貼り付けたまま行
い、公知の銀入りエポキシ樹脂接着剤を用いて半導体装
置が製造される。The subsequent die bonding step is performed with the conductive layer 4 made of epoxy resin adhered to the chip, and a semiconductor device is manufactured using a known silver-containing epoxy resin adhesive.

【００２２】図３は本発明の一実施例によって製造され
た半導体装置の一例を示す断面図である。図において、
本発明の一実施例による半導体装置はシリコン半導体基
板１と、金シリサイド層２と、Ａｕ薄膜層３と、接着剤
層４と、ダイボンディング用の導電性接着剤７と、リー
ド（フレーム）８，９と、金ワイア１０と、モールド樹
脂１１とから構成されている。FIG. 3 is a sectional view showing an example of a semiconductor device manufactured according to an embodiment of the present invention. In the figure,
A semiconductor device according to one embodiment of the present invention includes a silicon semiconductor substrate 1, a gold silicide layer 2, an Au thin film layer 3, an adhesive layer 4, a conductive adhesive 7 for die bonding, and a lead (frame) 8. , 9, a gold wire 10, and a mold resin 11.

【００２３】上記の説明ではシリコン半導体基板１の裏
面（Ａｕ薄膜層３上）に貼るテープとして銀微粒子入り
エポキシ層を含むエポキシ樹脂製の導電性テープを用い
ているが、塩化ビニール製等のある程度の強度を持った
ものであれば、ベーステープ５の種類は問わない。ま
た、接着剤層４についてもシリコンとの接着性がよけれ
ば、その種類は問わない。さらに、上記の例では導電性
を確保するために銀（Ａｇ）微粒子を使用しているが、
金（Ａｕ）や銅（Ｃｕ）のような他の金属でも有効であ
る。In the above description, a conductive tape made of an epoxy resin including an epoxy layer containing silver fine particles is used as a tape to be attached to the back surface (on the Au thin film layer 3) of the silicon semiconductor substrate 1. The type of the base tape 5 is not limited as long as the base tape 5 has the above strength. The type of the adhesive layer 4 is not limited as long as it has good adhesion to silicon. Further, in the above example, silver (Ag) fine particles are used in order to secure conductivity.
Other metals such as gold (Au) and copper (Cu) are also effective.

【００２４】さらにまた、シリコン半導体基板１の裏面
からのオーミックコンタクト性を確保するための金属と
して金（Ａｕ）を使用しているが、錫（Ｓｎ）やクロム
（Ｃｒ）等の他の金属を用いても有効である。その際、
金属シリサイド層を形成した後に再形成する金属につい
ても金（Ａｕ）や銀（Ａｇ）、及びニッケル（Ｎｉ）等
のあらゆる金属が有効である。Furthermore, although gold (Au) is used as a metal for ensuring ohmic contact from the back surface of the silicon semiconductor substrate 1, other metals such as tin (Sn) and chromium (Cr) are used. It is effective to use. that time,
As the metal to be re-formed after the formation of the metal silicide layer, any metal such as gold (Au), silver (Ag), and nickel (Ni) is effective.

【００２５】このように、薄いシリコン半導体基板１の
補強材及び緩衝材として補強用のテープ（エポキシ樹脂
製の導電性テープ）を使用するとともに、予めシリコン
半導体基板１の裏面に金シリサイド層２及びＡｕ薄膜層
３を形成し、そのＡｕ薄膜層３の上にエポキシ樹脂製の
導電性テープを貼付して組立て工程の前処理で使用し、
導電性テープの接着剤層４（導電層）をシリコン半導体
基板１から剥がすことなく半導体装置の組立て工程を実
行することによって、シリコン半導体基板１の割れや欠
けの発生を減少させることができる。As described above, a reinforcing tape (conductive tape made of epoxy resin) is used as a reinforcing material and a cushioning material for the thin silicon semiconductor substrate 1, and the gold silicide layer 2 and the An Au thin film layer 3 is formed, a conductive tape made of epoxy resin is adhered on the Au thin film layer 3 and used in a pretreatment of an assembly process,
By performing the assembling process of the semiconductor device without peeling the adhesive layer 4 (conductive layer) of the conductive tape from the silicon semiconductor substrate 1, it is possible to reduce the occurrence of cracks and chips in the silicon semiconductor substrate 1.

【００２６】よって、本発明の一実施例をシリコン半導
体基板１の裏面からのオーミックコンタクトの必要な半
導体装置、例えばトランジスタやダイオード等のディス
クリート素子にも適用できることが可能になる。その結
果、シリコンウエハの割れや欠けの減少による半導体装
置の歩留りを向上させることができる。また、ディスク
リート系半導体装置にも、１５０ｍｍφの大型シリコン
ウエハの適用が可能となる。Therefore, the embodiment of the present invention can be applied to a semiconductor device requiring an ohmic contact from the back surface of the silicon semiconductor substrate 1, for example, a discrete element such as a transistor or a diode. As a result, it is possible to improve the yield of semiconductor devices due to the reduction of cracks and chips in the silicon wafer. Further, a large silicon wafer of 150 mmφ can be applied to a discrete semiconductor device.

【００２７】[0027]

【発明の効果】以上説明したように本発明によれば、シ
リコンウエハの裏面に金属シリサイド層と金属層とを形
成し、その金属層上に電気伝導性が確保された導電層を
含むテープを貼付して組立て工程の前処理において使用
し、その導電層をシリコンウエハから剥がすことなく組
立て工程を実行することによって、大型のシリコンウエ
ハを使用する際のシリコンウエハの割れや欠けを低減す
ることができ、シリコンウエハの裏面から良好なオーミ
ックコンタクトを得ることができるという効果がある。As described above, according to the present invention, a metal silicide layer and a metal layer are formed on the back surface of a silicon wafer, and a tape including a conductive layer having a high electrical conductivity is formed on the metal layer. It is possible to reduce the cracking or chipping of a silicon wafer when using a large silicon wafer by performing the assembly process without sticking the conductive layer from the silicon wafer by using it in the pretreatment of the assembling process. Thus, there is an effect that a good ohmic contact can be obtained from the back surface of the silicon wafer.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施例の構成を示す断面図である。FIG. 1 is a cross-sectional view showing a configuration of an embodiment of the present invention.

【図２】本発明の一実施例による半導体装置の製造工程
を示すフローチャートである。FIG. 2 is a flowchart showing a manufacturing process of a semiconductor device according to one embodiment of the present invention.

【図３】本発明の一実施例によって製造された半導体装
置の一例を示す断面図である。FIG. 3 is a sectional view showing an example of a semiconductor device manufactured according to one embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１ シリコン半導体基板 ２ 金シリサイド層 ３ Ａｕ薄膜層 ４ 接着剤層 ５ ベーステープ５ ６ 切り離し溝 ７ ダイボンディング用の導電性接着剤 ８，９ リード １０ 金ワイア １１ モールド樹脂 DESCRIPTION OF SYMBOLS 1 Silicon semiconductor substrate 2 Gold silicide layer 3 Au thin film layer 4 Adhesive layer 5 Base tape 5 6 Separation groove 7 Conductive adhesive for die bonding 8, 9 Lead 10 Gold wire 11 Mold resin

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/301 H01L 21/52 ──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 21/301 H01L 21/52

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 シリコン半導体基板部と電気伝導性が確
保された導電層を含むテープとを張り合わせる工程と、
前記導電層を前記シリコン半導体基板部から剥がすこと
なく半導体装置のダイボンディングを行う工程とを有
し、前記シリコン半導体基板部を製造する工程が、シリコン
半導体基板を少なくとも研磨にて薄くする工程と、前記
シリコン半導体基板の裏面に第１の金属層を形成する工
程と、前記第１の金属層が形成された前記シリコン半導
体基板に熱処理を施して金属シリサイド層を形成する工
程と、前記金属シリサイド層上に第２の金属層を形成す
る工程とからなることを特徴とする半導体装置の製造方
法。 (1)Electrical conductivity is confirmed with the silicon semiconductor substrate
Laminating the tape containing the retained conductive layer,
Peeling the conductive layer from the silicon semiconductor substrate portion
Process for die bonding of semiconductor devices
AndThe step of manufacturing the silicon semiconductor substrate portion comprises silicon
A step of thinning at least a semiconductor substrate by polishing;
Forming a first metal layer on the back surface of a silicon semiconductor substrate;
And the silicon semiconductor on which the first metal layer is formed.
To form a metal silicide layer by applying heat treatment to the substrate
Forming a second metal layer on the metal silicide layer.
Semiconductor device manufacturing method characterized by the following steps:
Law. 【請求項２】 前記半導体装置を組立てる工程は、前記
導電層をダイボンディングの接着剤として用いるように
したことを特徴とする請求項１記載の半導体装置の製造
方法。 2. The method of assembling the semiconductor device according to claim 1 , wherein
Use conductive layer as die bonding adhesive
2. The manufacturing of a semiconductor device according to claim 1, wherein
Method. 【請求項３】 前記テープは、前記導電層と、前記導電
層を保持しかつ前記前処理において前記シリコン半導体
基板を補強するベーステープとから構成され、前記シリ
コン半導体基板のダイシング時に前記ベーステープ以外
を切離しかつ前記半導体装置を組立てる工程の実行前に
前記ベーステープを前記シリコン半導体基板から剥がす
ようにしたことを特徴とする請求項１または請求項２記
載の半導体装置の製造方法。 3. The tape according to claim 2 , wherein the conductive layer and the conductive layer
Holding the layer and in the pretreatment the silicon semiconductor
And a base tape for reinforcing the substrate.
Other than the base tape when dicing semiconductor substrates
Before the step of disconnecting and assembling the semiconductor device
Peeling the base tape from the silicon semiconductor substrate
3. The method as claimed in claim 1, wherein:
Manufacturing method of the semiconductor device described above.
JP23962796A 1996-09-11 1996-09-11 Method for manufacturing semiconductor device Expired - Lifetime JP3013786B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23962796A JP3013786B2 (en) 1996-09-11 1996-09-11 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23962796A JP3013786B2 (en) 1996-09-11 1996-09-11 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH1092778A JPH1092778A (en) 1998-04-10
JP3013786B2 true JP3013786B2 (en) 2000-02-28

Family

ID=17047542

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23962796A Expired - Lifetime JP3013786B2 (en) 1996-09-11 1996-09-11 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3013786B2 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4617559B2 (en) * 2000-10-30 2011-01-26 富士電機システムズ株式会社 Method for manufacturing power semiconductor device
JP4497737B2 (en) * 2001-03-12 2010-07-07 株式会社ルネサステクノロジ Manufacturing method of semiconductor device
KR20030079560A (en) * 2002-04-04 2003-10-10 이성민 Semiconductor wafer on which FRP is coated and semiconductor chip using the same, and fabricating method thereof
JP2005322738A (en) 2004-05-07 2005-11-17 Toshiba Corp Manufacturing method of semiconductor device
JP4406329B2 (en) 2004-07-14 2010-01-27 株式会社東芝 Semiconductor device and manufacturing method thereof
JP2006147623A (en) 2004-11-16 2006-06-08 Tdk Corp Cutting process of wafer
WO2007060837A1 (en) * 2005-11-22 2007-05-31 Success International Corporation Method of manufacturing semiconductor device
JP2010010447A (en) * 2008-06-27 2010-01-14 Disco Abrasive Syst Ltd Method for forming electrode of semiconductor device
JP2015015442A (en) 2013-07-08 2015-01-22 三菱電機株式会社 Semiconductor device
JP6289104B2 (en) * 2014-01-08 2018-03-07 日東電工株式会社 Film adhesive, dicing tape with film adhesive, semiconductor device manufacturing method, and semiconductor device
JP6955977B2 (en) * 2017-11-24 2021-10-27 株式会社ディスコ How to form chips

Also Published As

Publication number Publication date
JPH1092778A (en) 1998-04-10

Similar Documents

Publication Publication Date Title
US5770468A (en) Process for mounting a semiconductor chip to a chip carrier by exposing a solder layer to a reducing atmosphere
JP3621093B2 (en) Method and apparatus for manufacturing an integrated circuit device
KR940001149B1 (en) Chip bonding method of semiconductor device
TWI229435B (en) Manufacture of semiconductor device
JP3559432B2 (en) Method of forming a semiconductor metallization system and its structure
CN101432846B (en) Method for bonding a semiconductor substrate to a metal substrate
JP3013786B2 (en) Method for manufacturing semiconductor device
US11594504B2 (en) Nickel alloy for semiconductor packaging
JP4049035B2 (en) Manufacturing method of semiconductor device
JP3459234B2 (en) Semiconductor device and manufacturing method thereof
US9520380B2 (en) Wafer process for molded chip scale package (MCSP) with thick backside metallization
US3986251A (en) Germanium doped light emitting diode bonding process
JPS63213943A (en) Three-dimensional semiconductor integrated circuit
CN106328545A (en) Ultrathin chip double-surface exposed package structure of and manufacturing method thereof
US20210249306A1 (en) Semiconductor die singulation
JP2004103919A (en) Semiconductor wafer and its manufacturing method, and semiconductor device
JPH05291186A (en) Formation of metal contact on surface of semiconductor chip
JPH09330992A (en) Semiconductor device mounting body and its manufacture
CN117672964A (en) Ultrathin preparation and packaging method of power device chip
JP2833335B2 (en) Semiconductor device
JPH0870069A (en) Semiconductor device
TWI557813B (en) Dual-side exposed package and a manufacturing method
JPS6177369A (en) Manufacture of semiconductor device
JP2003068674A (en) Semiconductor device and production method therefor
JP2005217012A (en) Semiconductor device and manufacturing method therefor