JP2003068674A - Semiconductor device and production method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the process for gold foil spread (SPB) as a post-process in a production method for semiconductor device, a process for inspecting the presence/absence of an oxide film, and to provide a process for removing oxides, when the oxide is attached. SOLUTION: In the semiconductor device, having an electrode on the surface (rear side) of a semiconductor wafer facing a circuit element forming surface (front side), the rear electrode is a multilayer electrode, with which an NiSi alloy layer, Ti or V layer, Ni layer, AuGe alloy layer and Au layer are successively laminated from the rear side of the semiconductor wafer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface (hereinafter, referred to as a surface) of a semiconductor substrate opposite to a surface on which a circuit element is formed (hereinafter referred to as a surface).
The present invention relates to a semiconductor device having an electrode on the back surface) and a method for manufacturing the same, and particularly to a technique effectively applied to a transistor having an electrode on the back surface.

[0002]

2. Description of the Related Art A conventional transistor having a small driving current,
For example, the back electrode of an NPN transistor is formed by depositing an Au layer of 2000 liters and performing GBA (Gold Back Alloy, alloy temperature 385 ° C.) to form an AuSi layer.
In the back electrode of the conventional NPN transistor, S
Since it is a b-doped N-type Si substrate, pure A is used for the back electrode.
When u is used, the ohmic contact of the electrode cannot be obtained. To prevent this, an alloy of Au and Sb is used.

[0003]

The present inventor has found the following problems as a result of examining the above-mentioned prior art. For the back electrode of AuSb, a pelletizing step in a later step,
In the bonding process, gold foil laying (SPB) and scrubbing (pellet bonding) operations are required, and there is a problem that the throughput of the pelleting process and the bonding process becomes low. In the back electrode of AuSb, since Sb is oxidized by sintering and ohmic characteristics are deteriorated to increase the potential, the step of inspecting the presence or absence of the oxide film and the oxide when the oxide is attached There is a problem in that a process for removing is necessary.

An object of the present invention is to provide a technique capable of reducing the gold foil laying (SPB) step which is a post-step in the method of manufacturing a semiconductor device. Another object of the present invention is to provide a technique capable of reducing the step of inspecting the presence or absence of an oxide film and the step of removing the oxide when the oxide is attached. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows. A first invention is a surface (hereinafter, referred to as a surface) opposite to a circuit element formation surface (hereinafter referred to as a surface) of a semiconductor substrate.
In the semiconductor device having an electrode on the backside), the backside electrode is a NiSi alloy layer on the backside of the semiconductor substrate,
This is a multi-layer electrode in which a Ti layer, a Ni layer, an AuGe alloy layer, and an Au layer are stacked in the above order.

A second invention is a semiconductor device having an electrode on the back surface of a semiconductor substrate, wherein the back electrode is a NiSi alloy layer, V layer, Ni layer, AuG on the back surface of the semiconductor substrate.
The e-alloy layer and the Au layer are multilayer electrodes laminated in the above order.

A third invention is a method of manufacturing a semiconductor device having an electrode on the back surface of a semiconductor substrate, wherein the step of forming the back surface electrode comprises forming a Ni layer on the back surface of the semiconductor substrate,
Manufacturing in which a NiSi alloy (silicide) layer is formed while heating the Ni layer, and a Ti layer or a V layer, a Ni layer, an AuGe alloy layer, and an Au layer are sequentially laminated on the NiSi alloy layer to form a multilayer electrode. Is the way.

According to the means of the invention, it is possible to reduce the gold foil laying (SPB) step which is a post-step. Further, the step of inspecting the presence or absence of the oxide film and the step of removing the oxide when the oxide is attached can be omitted.

Hereinafter, the present invention will be described in detail with reference to the drawings together with embodiments (embodiments). In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and repeated description thereof will be omitted.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 1 is a sectional view showing a schematic configuration of an NPN type transistor according to a first embodiment of the present invention.

The NPN type transistor of the first embodiment is
As shown in FIG. 1, a P-type semiconductor layer (base layer) 2 is formed on an N-type semiconductor Si substrate (collector layer) 1,
A base electrode 3 is provided from the P-type semiconductor layer (base layer) 2 via an Al wiring or the like.

A high-concentration N-type semiconductor layer (emitter layer) 4 is formed in the P-type semiconductor layer 2 and a base electrode is formed from the high-concentration N-type semiconductor layer (emitter layer) 4 through an Al wiring or the like. 5 are provided.

On the surface (rear surface) of the Si substrate (collector layer) 1 opposite to the surface on which the circuit elements are formed, a collector electrode (hereinafter, referred to as
A backside electrode) 6 is provided. As shown in FIG. 2, the back surface electrode (multilayer electrode) 6 is formed on the Si substrate 1
NiSi layer, Ti layer, Ni layer, AuGe
It is composed of a multilayer electrode in which an alloy layer and an Au layer are laminated.

The above NiSi alloy layer, Ti layer, Ni layer, A
As shown in FIG. 2, the thickness of each of the uGe alloy layer and the Au layer is, for example, 100 Å to 4000 Å for the NiSi layer and Ti.
Layer is 500Å to 2000Å, Ni layer is 1000Å to 80
00Å, AuGe alloy layer is 5000Å ~ 15000Å,
The Au layer has a thickness of 500Å to 2000Å.

The NiSi alloy layer is formed by forming a silicide, and the Ni layer is formed while heating the Si substrate 1 at 300 ° C. to 450 ° C. In addition, the Ti layer, Ni
The layers, AuGe alloy layer, and Au layer are formed by a sputtering method or a vapor deposition method.

As shown in FIG. 3, the NPN-type transistor element of the first embodiment forms a circuit element in a semiconductor wafer state, and the surface (back surface) opposite to the circuit element forming surface (front surface) is formed. For example, grinding is performed until the thickness of the wafer becomes 200 μm (step 101). Since this grinding is still a rough surface, chemical etching (spin etching) is performed while rotating the wafer to make the surface smoother.
For example, until the thickness of the wafer reaches 160 μm (step 102). The backside electrode 6 is formed by film deposition on the backside of the semiconductor wafer having a thickness of 160 μm (step 103), and the first embodiment is formed on the semiconductor wafer.
NPN type transistor device is manufactured. Details of the spin etching are described in, for example, JP-A-11-25.
It is described in Japanese Patent No. 1287.

Next, the manufacturing process of the NPN type transistor of the first embodiment will be described. As shown in FIG. 4, the manufacturing process of the NPN-type transistor of the first embodiment includes Ag
A lead frame which is not plated (without Ag plating) is prepared (step 201), and the semiconductor chip with the back electrode is pellet-bonded (scrubless) on the lead frame (step 202). Next, the leads are electrically connected to the external electrodes (pads) of the semiconductor chip by wire bonding (step 20).
3), mold with a sealing material (resin) (step 20)
4). The completed NPN type transistor is cut into individual frames and separated (step 205).

As described above, the back electrode (collector electrode) 6
When the temperature of the back surface electrode (collector electrode) 6 is increased (for example, the heat treatment temperature may be increased to 385 ° C. to form an AuSi eutectic) by using a multi-layered electrode, the Au layer is made of AuGe alloy. As a result, the adhesion between the Cu of the wiring material and the Au layer is improved. That is, A
Since the uGe alloy layer is vapor-deposited on the back surface electrode 6 in advance, Au / Ge / Cu interdiffuses to generate a ternary metal, thereby improving the adhesiveness.

As a result, the following effects can be obtained. That is, in the first embodiment, as shown in FIG. 4, (1) Au spot bonding is conventionally performed in a post-process assembly (SPB: see step 201A of the conventional process in FIG. 5).
However, the Au spot bonding (SPB) is unnecessary. Thereby, the Au foil material cost can be reduced. (2) Since the scrubbing process is unnecessary, the throughput can be improved. (3) Since the lead is not plated with Ag, the material cost of the lead frame can be reduced. (4) Since the crack margin of the semiconductor chip becomes large, it can be applied to a large semiconductor chip.

(Embodiment 2) FIG. 6 is a diagram showing a schematic structure of a back surface electrode in an NPN transistor according to Embodiment 2 of the present invention. The back surface electrode of the second embodiment is made of high-concentration Si.
The present invention is applied to a substrate, and as shown in FIG. 6, a Ti layer, a Ni layer, and an Au layer are sequentially formed from the back surface of the Si substrate.
It is composed of a multilayer electrode in which a Ge alloy layer and an Au layer are laminated.

The Ti layer, Ni layer, AuGe alloy layer, A
The thickness of each u layer is, for example, Ti as shown in FIG.
Layer is 500Å to 2000Å, Ni layer is 1000Å to 80
00Å, AuGe alloy layer is 5000Å ~ 15000Å,
The Au layer has a thickness of 500Å to 2000Å.

Since the high-concentration Si substrate can reduce the connection resistance with the Ti layer, the electrode structure can be used as the back electrode 6. The present invention can be applied as a new back surface electrode (collector electrode) to all semiconductor devices having a back surface electrode as shown in FIG. 7.

Although the present invention has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

[0024]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. According to the present invention, it is possible to reduce the gold foil laying (SPB) step that is a post-step in the manufacturing of a semiconductor device. Further, the step of inspecting the presence or absence of the oxide film and the step of removing the oxide when the oxide is attached can be omitted.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a schematic configuration of an NPN transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a configuration of a back surface electrode (multilayer electrode) according to the first embodiment.

FIG. 3 is a flowchart showing a manufacturing process of a back surface electrode (multilayer electrode) according to the first embodiment.

FIG. 4 is a flowchart showing a manufacturing process of an NPN (PNP) type transistor of the first embodiment.

FIG. 5 is a flowchart showing manufacturing steps of a conventional NPN (PNP) type transistor.

FIG. 6 is a cross-sectional view showing a configuration of a back surface electrode (multilayer electrode) according to a second embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a schematic configuration of a transistor to which the present invention is applied.

[Explanation of symbols]

1 ... N-type Si substrate (collector layer) 2 ... P-type semiconductor layer (base layer) 3 ... Base electrode 4 ... High-concentration N-type semiconductor layer (emitter layer) 5 ... Emitter electrode 6 ... Collector electrode (backside electrode)

Continued front page    (72) Inventor Takashi Ihayasaka             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Yasuo Maruyama             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Kazuo Hatori             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group F-term (reference) 4M104 AA01 BB02 BB14 BB21 CC01                       DD34 DD37 DD78 DD84 FF02                       GG06 HH20

Claims (3)

[Claims] 1. A semiconductor device having an electrode on a surface (hereinafter referred to as a back surface) opposite to a circuit element formation surface (hereinafter referred to as a front surface) of a semiconductor substrate, wherein the back surface electrode is provided on a back surface of the semiconductor substrate. NiSi alloy layer, Ti layer, Ni layer, Au
A semiconductor device comprising a Ge alloy layer and an Au layer, which are multilayer electrodes laminated in the above order. 2. A semiconductor device having an electrode on a surface (hereinafter referred to as a back surface) opposite to a circuit element formation surface (hereinafter referred to as a front surface) of a semiconductor substrate, wherein the back surface electrode is provided on a back surface of the semiconductor substrate. NiSi alloy layer, V layer, Ni layer, AuG
A semiconductor device comprising an e-alloy layer and an Au layer, which are multilayer electrodes laminated in the above-described order. 3. A method of manufacturing a semiconductor device having an electrode on a surface (hereinafter, referred to as a back surface) opposite to a circuit element formation surface (hereinafter, referred to as a front surface) of a semiconductor substrate, wherein the step of forming the back surface electrode includes: Forming a Ni layer on the back surface of the semiconductor substrate,
A NiSi alloy layer is formed while heating the Ni layer,
On top of the iSi alloy layer, Ti layer or V layer, Ni sequentially
A method for manufacturing a semiconductor device, which comprises laminating a layer, an AuGe alloy layer, and an Au layer to form a multilayer electrode.