JP4104506B2 - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein the concentration of Sb contained in a backside metal is reduced by the reaction between a conductive pattern and the backside metal, contact resistance in a silicon substrate is increased, and hence characteristics vary in a chip-size package for mounting a semiconductor chip onto an insulating substrate on which a gold-plated conductive pattern is provided conventionally. <P>SOLUTION: A deposition process is made three times. In the deposition process, a first Au layer, an Au-Sb layer, and a second Au layer are deposited onto the backside of the substrate each. In the Au-Sb layer, the amount of Sb contained in the Au-Sb layer is set to be approximately 1% and deposition is made to a film thickness of 5,000&angst;, thus ensuring at least 0.1% Sb concentration after assembly and hence ensuring satisfactory characteristics without reducing the contact resistance in the silicon substrate. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device for stabilizing characteristics of a chip-sized package in which a substrate is made of an insulating material such as ceramic or glass and the surface of the material is plated with tungsten and Au. About.

  In order to reduce the size, thin film, and weight of electronic components, and to streamline the assembly process, semiconductor products in a chip size package are widely used.

  A conventional method for manufacturing a chip size package will be described with reference to FIGS. FIG. 4 is a process flow diagram for explaining a conventional manufacturing method, and FIG. 5 is a sectional view of a semiconductor device.

  First, a predetermined element diffusion region 22 constituting, for example, a MOSFET or a bipolar transistor is formed on the N + type silicon semiconductor substrate 21 by a known method (FIG. 4: S11 and FIG. 5A).

  The wafer is carried into a vacuum vapor deposition apparatus, and first vapor deposition is performed to form an alloy layer 24 on the back surface of the high concentration substrate. Two evaporation sources are used, Au and Au-Sb (or Au-As), and these are vapor-deposited simultaneously. Note that the Sb concentration in Au—Sb is about 0.4%.

  The reason for depositing Au and Au—Sb simultaneously will be described. When Au—Sb is directly deposited on the silicon substrate, the impurity (Sb) concentration is increased at the interface between the silicon substrate and the deposited metal, and the eutectic reaction between silicon and Au becomes insufficient. For this reason, Au and Au—Sb are vapor-deposited at the same time to increase the amount of Au and reduce the proportion of Sb in the total Au. At this time, the Au layer is 50 nm and the Au—Sb layer is simultaneously deposited by about 50 nm, so that the total thickness of the alloy layer 24 is about 100 nm (FIG. 4: S 12 and FIG. 5B).

  Thereafter, second deposition is performed using an Au deposition source to form an Au layer 25 having a thickness of about 500 nm, and a back metal layer 33 having a total thickness of about 600 nm is formed (FIG. 4: S13 and FIG. 5 (C)).

  Further, the semiconductor chip 26 is formed by dicing at a portion indicated by a broken line in FIG. Next, the semiconductor chip 26 is welded to the insulating substrate 27 in the assembly process. An insulating substrate 27 such as ceramic is provided with tungsten 34, and conductive patterns 28A and 28B are formed thereon by an Au plating layer. The back surface metal layer 33 of the semiconductor chip 26 and the conductive pattern 28A are welded, and the surface of the substrate 21 is adhered. The element diffusion region 22 is also electrically connected to the conductive pattern 28B by a thin metal wire 31 or the like. The insulating substrate 27 and the semiconductor chip 26 are covered with a resin layer 32 and integrated. A through hole 29 filled with tungsten 34 is provided in the insulating substrate 27, and an external electrode 30 is connected (FIG. 4: S14 and FIG. 5D).

Also, a hollow package in which a semiconductor chip is sealed by a columnar part on the insulating substrate 27 in place of the resin layer 32, a glass substrate supported by the columnar part and the columnar part and arranged to face the insulating substrate, etc. is also employed. (For example, refer to Patent Document 1).
Japanese Patent Laid-Open No. 2002-118191 (second page, FIGS. 1 and 2)

  In the chip size package in which the tungsten 34 is provided on the insulating substrate 27 and the conductive pattern 28A is provided thereon as described above, the conductive pattern 28A is an Au plating layer. In addition, when the semiconductor chip 26 of the N + type silicon substrate 21 is welded to the chip size package as described above, a heat treatment at about 400 ° C. is performed. In this heat treatment, the Si of the substrate diffuses into Au of the back surface metal layer 33 to form a dissolved Au—Si eutectic, and Si enters the eutectic from the interface, thereby further lowering the eutectic temperature. As a result, the Au layer 25 deposited on the back surface and the Au plating as the conductive pattern 28A and Si are gradually dissolved to be eutectic. Thereafter, the chip 26 is fixed by lowering the substrate temperature.

  However, the Sb particles of the Au—Sb layer constituting the back surface metal layer 33 also flow into the Au of the conductive pattern 28A together with the dissolved Si. Sb is used to suppress the interface level of the substrate. In order to lower this level, the concentration in the total Au is preferably 0.1% or more.

  For example, when a semiconductor chip is fixed to a Cu punching frame, Ag plating is generally performed on the Cu frame, and Sb does not flow out during Ag plating. That is, in order to finally secure the Sb concentration of 0.1%, as described above, the amount of Sb in Au—Sb is about 0.4%.

  However, in the chip size package of this embodiment, since the conductive pattern of the insulating substrate is also formed by Au plating, the final Au amount increases. For example, when a semiconductor chip of 0.35 mm or more is welded to an insulating substrate having an Au plating thickness of 1 μm and an area size of 0.6 mm square, the Sb concentration in Au—Sb is 0. If it is 4%, the Sb concentration in the total Au decreases to 0.03%. That is, the Sb concentration in the entire Au layer after chip welding becomes 0.1% or less, the interface state of the substrate becomes large, and the characteristics vary.

  As a countermeasure for this, the Sb concentration in the total Au may be increased to ensure the Sb concentration after assembly to be 0.1% or more. For example, the alloy layer (Au layer, Au—Sb) deposited on the back surface may be used. In order to secure the Sb concentration of 0.1% or more after assembling by thickening the layer 24), the back surface metal layer is required to be 1.7 times the conventional thickness, resulting in an increase in cost.

  In addition, there is a limit to the amount of Sb that can be contained in Au / Sb as a material in production. Moreover, even if it increases, it is difficult to increase only the Sb content because the eutectic reaction deteriorates.

  Further, in order to reduce the amount of Au, the Au-Sb layer is vapor-deposited by removing Au from the first vapor-deposited layer, and the Au layer is vapor-deposited by the second vapor-deposition, as described above, impurities ( Sb) increases, Au-Si eutectic formation is hindered, and there is a problem that die bond welding failure occurs during assembly.

  The present invention has been made in view of such problems, and includes a step of forming an element diffusion region on the surface of an n-type silicon semiconductor substrate, and a step of performing a first vapor deposition of forming a first Au layer on the back surface of the semiconductor substrate. A second vapor deposition step of forming an impurity-containing metal layer on the first Au layer; a third vapor deposition step of forming a second Au layer on the impurity-containing metal layer; A step of forming a metal layer, and a step of dividing the semiconductor substrate to form a semiconductor chip and welding the semiconductor chip onto a conductive pattern made of a third Au layer provided on an insulating substrate. It is a solution.

  Further, the first to third vapor depositions are performed in the same vacuum apparatus.

  Further, the conductive pattern on the insulating substrate is connected to an external electrode on the back surface of the insulating substrate through a through hole provided in the insulating substrate.

  In addition, after the semiconductor chip is welded, the concentration of the impurity contained in all the Au layers is 0.1% or more.

  The impurity-containing metal layer is deposited to a thickness of about 500 nm.

  The impurity concentration in the metal layer containing impurities is about 0.1% to 1.2%.

  The metal layer containing impurities is Au-Sb or Au-As.

  The first Au layer is formed to a thickness of about 50 nm.

  The back metal layer of the substrate is formed to a thickness of about 600 nm.

  According to the present invention, even when a semiconductor chip of an N-type silicon substrate is welded onto Au plating such as a conductive pattern of a chip size package, a decrease in impurity concentration at the silicon interface can be suppressed. Since the interface state on the back surface of the chip can be reduced, good characteristics can be secured.

  Moreover, since the film thickness of the back surface metal layer can be made equal to the conventional one, the Sb concentration in Au can be secured at a predetermined concentration without increasing the cost.

  Furthermore, since a thin Au layer is formed by the first vapor deposition, the Au—Si eutectic is promoted, and even if the Sb concentration of the Au—Sb layer deposited thereafter is higher than the conventional one, the eutectic is not hindered. The chip and the conductive pattern can be welded.

  The embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 shows a process chart of the production method of the present invention.

  As shown in FIG. 1, the semiconductor device manufacturing method of the present invention includes a step (S1) of forming an element diffusion region on the surface of an n-type silicon semiconductor substrate and a first Au layer on the back surface of the semiconductor substrate. A step (S2) of performing a first vapor deposition, a step (S3) of performing a second vapor deposition for forming an impurity-containing metal layer on the first Au layer, and a second Au layer on the alloy layer. A step (S4) of forming a third metal layer to form a back surface metal layer; and a third Au layer in which the semiconductor substrate is divided to form a semiconductor chip and the semiconductor chip is provided on the insulating substrate. And a step (S5) of welding on the conductive pattern.

  Moreover, FIG. 2 is sectional drawing which shows the manufacturing method of this embodiment. The manufacturing method will be described below with reference to FIGS.

  First step (see FIG. 2A, FIG. 1: S1): a step of forming an element diffusion region on the surface of the n-type silicon semiconductor substrate.

  First, a predetermined element diffusion region 2 constituting, for example, a MOSFET or a bipolar transistor is formed on an N + type silicon semiconductor substrate 1 by a known method. The present embodiment is a semiconductor discrete device having a so-called vertical structure in which a diffusion region constituting one or more elements is provided on a high concentration substrate.

  Second step (see FIG. 2B, FIG. 1: S2): A step of performing first vapor deposition for forming a first Au layer on the back surface of the semiconductor substrate.

  The wafer is carried into a vacuum deposition apparatus, and first deposition for forming a first Au layer 3 on the back surface of the N + type silicon semiconductor substrate 1 is performed. The deposition source is only Au, and the film thickness of the first Au layer 3 is about 50 nm. Since the back surface of the silicon semiconductor substrate 1 is in contact with the Au layer 3 containing no impurities by the heat treatment during the die bonding operation in the assembly process, Au—Si eutectic can be promoted.

  Third step (see FIG. 2C, FIG. 1: S3): a step of performing second vapor deposition for forming an impurity-containing metal layer on the first Au layer.

  In the same deposition apparatus, the deposition source is changed to an impurity-containing metal, for example, Au—Sb, and second deposition is performed to form the Au—Sb layer 4 with a thickness of about 500 nm.

  In the assembly process, when a semiconductor chip is fixed to the conductive pattern of Au, there is a method in which a gold foil is applied before the chip is bonded, and the chip is pressed thereon to perform the reaction between Au and silicon. However, the gold foil cannot be made thinner than 7 μm in terms of handling, and the handling becomes difficult if the width is cut smaller than 0.5 mm. Therefore, when this gold foil is adopted as the back metal of a 0.35 mm square semiconductor chip, the size is 0.5 mm × 0.4 mm × 7 μm, and the amount of gold is 10 compared to the case where metal deposition is performed on the back surface. The cost is very high because it is doubled. Therefore, the thickness of the back surface metal layer of the silicon substrate 1 is made thick, for example, about 600 nm, thereby omitting the gold foil and reducing the cost in the assembly process.

  Here, in the present embodiment, the Sb concentration in the Au—Sb layer 4 is, for example, about 1%. Thus, by depositing the Au—Sb layer 4 having a higher Sb concentration than the conventional one so as to have a film thickness about 10 times that of the conventional one, the Sb concentration (amount) is increased, and the final Au in the Au is increased. This ensures an Sb concentration of 0.1% or more.

  As described above, there is a limit to the increase in the amount of Sb of Au—Sb in the production of the material. However, if it is up to about 1% as in the present embodiment, there is no problem in including Sb in Au. However, when the film thickness is about the same as the conventional film (50 nm), the ratio of Sb to the final Au amount is low. Therefore, in the present embodiment, the thickness of the Au—Sb layer 4 is also increased to about 10 times that of the conventional one to prevent the Sb ratio from being reduced.

  Further, since the amount of Sb in the Au—Sb layer 4 is larger than the conventional (0.4%), when this is directly deposited on the silicon substrate 1, the Sb concentration at the interface between the silicon substrate 1 and the Au—Sb layer is high, There is a problem that the eutectic reaction with silicon becomes insufficient. Therefore, by forming the thin first Au layer 3 in advance in the first step, it is easy to react with silicon by the Au—Si eutectic, and the thick Au—Sb layer 4 is deposited in that state. .

  That is, in the case where welding is performed by a heat treatment of about 400 ° C. in the subsequent process, first, the first Au layer 3 directly deposited on the silicon substrate becomes liquid Au—Si by eutectic with Si of the substrate, When Si further enters the eutectic from the interface, the melting temperature decreases. Thereafter, since the Au—Sb layer 4 is dissolved, even if the amount of Sb is large, sufficient dissolution at a low temperature is possible.

  Fourth step (FIG. 2D) A step of forming a back metal layer by performing third vapor deposition for forming a second Au layer on the alloy layer (see FIG. 1: S4).

  Further, in the same vapor deposition apparatus, third vapor deposition using only the Au layer as a vapor deposition source is performed, and the second Au layer 5 is vapor-deposited on the Au—Sb layer 4 by about 50 nm. The purpose of the second Au layer 5 is to prevent oxidation of Sb until die bonding in the assembly process. By this step, the back metal layer 13 of the silicon substrate 1 is formed to a thickness of about 600 nm.

  Fifth step (FIG. 2E): a step in which the semiconductor substrate is welded onto a conductive pattern made of a third Au layer provided on an insulating substrate and resin-molded (see FIG. 1: S5).

  Thereafter, dicing is performed as indicated by broken lines in FIG. 2D, and the semiconductor chip 6 is formed by being separated into individual element regions. The semiconductor chip 6 is welded to the insulating substrate 7 in the assembly process. A conductive pattern 8 (8A, 8B) is formed on an insulating substrate 7 made of ceramic or the like on a tungsten layer 14 by using an Au plating layer as a third Au layer.

  Further, a through hole 9 filled with tungsten 14 and an external electrode 10 connected to the through hole 9 are formed in the insulating substrate 7. The semiconductor chip 6 is mounted on the conductive pattern 8A, and a heat treatment at about 400 ° C. is performed.

  In this embodiment, no heat treatment is performed from the first vapor deposition up to the fourth vapor deposition until the third vapor deposition, and Au—Si is commonly used in the heat treatment for die bonding (approximately 400 ° C.) in this vapor phase. Crystallize and weld the chip and conductive pattern. That is, the Si of the substrate diffuses into the first Au layer 3 of the back surface metal layer 13 to form liquid Au—Si, and Si enters the interface to further reduce the eutectic reaction temperature. As a result, the Au—Sb layer 4 and the second Au layer 5 react in sequence, and finally the Au plating as the conductive pattern 8A and Si are dissolved and eutectic, whereby the chip 6 is fixed.

  The element diffusion region 2 on the surface of the substrate 1 is also electrically connected to the conductive pattern 8B through the metal thin wire 11 or the like. The insulating substrate 7 and the semiconductor chip 6 are covered with the resin layer 12 and integrated.

  FIG. 3 conceptually shows the amounts of Au and Sb of the back surface metal layer 33 (a) having the conventional structure and the back surface metal layer 13 (b) of the present embodiment. Actually, Sb is in a state where the particles are mixed in dissolved Au, but here, the Sb amount in the same chip size is conceptually converted into a film thickness and compared. The chip size is 0.35 mm square.

  In the conventional structure (a), the Au layer and the Au—Sb layer are simultaneously deposited to 100 nm in the first deposition S12. At this time, since the amount of Sb in the Au—Sb layer is about 0.4%, the film thickness is about 1.5 nm. By depositing a thicker Au layer 25 and die-bonding it to a gold-plated substrate, the proportion of Sb in the total Au is reduced to 0.033%.

  On the other hand, in the structure (b) of the present embodiment, the first Au layer 3 is deposited by 50 nm, and then the Au—Sb layer 4 is deposited by 500 nm. The amount of Sb in the Au—Sb layer 4 is about 1%, but when converted to a film thickness by vapor deposition of 500 nm, it becomes 12 nm. Further, the second Au layer 6 is deposited by 50 nm to form the back metal layer 13 having a total of 600 nm. Thereby, the ratio of Sb in Au can be secured at 0.97%. By forming such a back surface metal layer 13, when the eutectic is formed with the conductive pattern 8B (Au plating thickness 1 μm, area size 0.6 mm square) on the insulating substrate 7 in the assembly process, the Sb concentration is 0.1%. Can be secured.

  In the present embodiment, Au—Sb has been described as an example of the impurity-containing metal layer. However, the present invention is not limited to this, and an Au—As layer or an alloy containing other pentavalent metals as impurities in Au is also the same. Can be implemented. N-type silicon is pentavalent, and if an alloy layer is formed of a metal other than pentavalent at this interface, a band cap is formed between the silicon and the alloy layer, which deteriorates the characteristics. For this reason, a pentavalent impurity is introduced so as not to generate a band cap.

  In the present embodiment, the package using the resin layer has been described as an example. However, the sealing material for the semiconductor chip 6 is not limited thereto. As long as the conductive pattern 8 by the Au plating layer is provided on the insulating substrate 7 and the chip 6 is welded, the same applies to, for example, a hollow package in which a columnar portion is provided on the insulating substrate and sealed with a glass substrate facing the insulating substrate. Can be implemented.

It is process drawing of the manufacturing method of the semiconductor device of this invention. It is explanatory drawing of the manufacturing method of the semiconductor device of this invention. It is explanatory drawing of the manufacturing method of this invention and the conventional semiconductor device. It is process drawing of the manufacturing method of the conventional semiconductor device. It is explanatory drawing of the manufacturing method of the conventional semiconductor device.

Explanation of symbols

1 N-type silicon semiconductor substrate 2 Element diffusion region 3 First Au layer 4 Au / Sb layer 5 Second Au layer 6 Semiconductor chip 7 Insulating substrate
8 Conductive pattern (third Au layer)
9 Through hole (tungsten)
DESCRIPTION OF SYMBOLS 10 External electrode 11 Bonding wire 12 Resin layer 13 Back surface metal layer 14 Tungsten 21 N type silicon semiconductor substrate 22 Element diffusion area 24 Alloy layer 25 Au layer 26 Semiconductor chip 27 Insulating substrate
28 Conductive pattern (third Au layer)
29 Through-hole 30 External electrode 31 Bonding wire 32 Resin layer 33 Back metal layer 34 Tungsten

Claims (8)

forming an element diffusion region on the surface of the n-type silicon semiconductor substrate;
Performing a first vapor deposition to form a first Au layer on the back surface of the semiconductor substrate;
And performing a second deposition of a metal layer containing impurities in said first continue the first Au layer on the deposition,
Performing a third vapor deposition for forming a second Au layer on the impurity-containing metal layer to form a back metal layer;
A semiconductor chip is formed by dividing the semiconductor substrate, and the first Au layer and Si of the semiconductor substrate are eutectic by heat treatment, and a third metal layer provided on the back metal layer and the insulating substrate of the semiconductor chip. And a step of welding a conductive pattern made of an Au layer ,
The method of manufacturing a semiconductor device, wherein the metal layer includes the impurity in an amount that causes the concentration of the impurity contained in all the Au layers to be 0.1% or more after the semiconductor chip is welded . 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first to third vapor depositions are performed in the same vacuum apparatus. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive pattern on the insulating substrate is connected to an external electrode on the back surface of the insulating substrate through a through hole provided in the insulating substrate. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity-containing metal layer is deposited to a thickness of about 500 nm. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity concentration in the impurity-containing metal layer is 0.1% to 1.2%. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity-containing metal layer is Au—Sb or Au—As. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first Au layer is formed to a thickness of about 50 nm. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the back metal layer of the substrate is formed to a thickness of about 600 nm.

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