JPS6014445A - Compound semiconductor device - Google Patents

Compound semiconductor device

Info

Publication number
JPS6014445A
JPS6014445A JP58121368A JP12136883A JPS6014445A JP S6014445 A JPS6014445 A JP S6014445A JP 58121368 A JP58121368 A JP 58121368A JP 12136883 A JP12136883 A JP 12136883A JP S6014445 A JPS6014445 A JP S6014445A
Authority
JP
Japan
Prior art keywords
layer
gold
film
thin
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58121368A
Other languages
Japanese (ja)
Inventor
Yoshio Iizuka
飯塚　佳男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58121368A priority Critical patent/JPS6014445A/en
Publication of JPS6014445A publication Critical patent/JPS6014445A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01042—Molybdenum [Mo]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Led Devices (AREA)

Abstract

PURPOSE:To enable die bonding, which has excellent ohmic contacting properties and reliability thereof is high, by forming an electrode, an intermediate section thereof consists of three-layer metallic thin-films with metallic thin-films of the high melting point, on the surface of a semiconductor element. CONSTITUTION:A first metallic thin-film 31 consisting of an alloy of beryllium or zinc and gold, a second metallic thin-film 32 composed of a high melting-point metal mainly comprising either of Ti, Ta, Mo, Ni or W and a third metallic thin-film 33 of the low melting point consisting of a eutectic alloy of germanium, silicon, tin or the like and gold are formed on the surface of a p type GaAlAs layer 22p. A chip can be die-bonded easily because the thin-film 33 is made of a low melting-point metal. An ohmic contact between the p type GaAlAs layer 22p and a metallic electrode 23 is not obstructed because the fine thin-film 32 composed of a layer 27 in Ti, etc. prevents a crossing over the thin-film 32 of germanium, etc. in the thin-film 33 and a diffusion into the layer 22p of germanium, etc. in heating at the time of die bonding of the thin-film 32.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、金共晶を用いてグイボンディングを行う化合
物半導体装置に係り、特にＧａＡｓ　（ガリウム・ひ素
）　、ＧａＡＬＡｓ　（ガリウム・アルミニウム・ひ素
）を結晶材料とする発光素子（ＬＥＤ　）等の化合物半
導体装置に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a compound semiconductor device that performs bonding using gold eutectic. The present invention relates to compound semiconductor devices such as light emitting devices (LEDs) using crystalline materials.

〔発明の技術的背景〕[Technical background of the invention]

従来より広く用いられているＧａＡｓ赤外発光素子では
、ｐｎ接合部を有する素子のグイポンディング面となる
ｎ　ｇ　ＧａＡｓ層表面にオーミック接触を得るだめの
金属膜として金に微量の例えばゲルマニウムを含む第１
の金属膜を被着し、この金属膜上に重量比で１２％程度
のグルマニウムを含む低融点の金の共晶合金からなる第
２の金属膜を積層形成した素子が用いられる場合がある
。このような素子では、素子基台となるリードフレーム
上に素子を載置し、４００℃程度に加熱することによシ
第２の金属膜が溶け、素子基台に素子が固定されるため
、導電性接着剤等を用いる必要なくグイボンディングを
簡単に行うことができる。In GaAs infrared light-emitting devices that have been widely used in the past, gold contains a small amount of germanium, for example, as a metal film to establish ohmic contact with the surface of the n g GaAs layer, which serves as the bonding surface of the device having a pn junction. 1st
In some cases, an element is used in which a second metal film made of a low melting point gold eutectic alloy containing approximately 12% glumanium by weight is laminated on the metal film. In such an element, the element is placed on a lead frame that serves as the element base, and the second metal film is melted by heating it to about 400°C and the element is fixed to the element base. Gui bonding can be easily performed without using a conductive adhesive or the like.

ところで、近年高出力の赤外発光素子として、Ｓｔを添
加したＧａＡｔＡｓ結晶からなるＬＥＤが使用されるよ
うになった。Incidentally, in recent years, LEDs made of GaAtAs crystal doped with St have come to be used as high-output infrared light emitting elements.

とのＧａＡｌ−Ａ　ｓによる素子は、液相成長中にＳｔ
添加層の導電型がｎ型からｐ型に変化することを利用し
た素子で、ＧａＡｓ基板を、Ｇａ　、　Ａｔ、Ａｓおよ
びＳｉの混合融液中に浸し、徐冷してＧ　ａＡ　ｓ基板
上にＳｔの添加されたＧａＡｔＡｓ液相成長層を成長さ
せたものである。このような液相成長を行うと、第１図
のグラフに示すように液相成長層の成長とともにＡｔＡ
ｓ混晶比Ｘが変化し、基板に近いＡｔＡｓ混晶が多量に
存在する高温成長領域（図の破線上部領域）ではシリコ
ンがｎ型不純物となｐ、ＡｔＡｓ混晶の少ない低温成長
領域（図の破線下部領域）ではシリコンがｐ型不純物と
なってｐｎ接合面を有するウェハが得られる′。その後
、ＧａＡＡＡｓ：Ｓｉの液相成長層のみが残るように、
上記ＧａＡｓ基板を例えば化学エツチングによシ除去し
て第２図に示すようなＬＥＤチッ７０１０を形成する。GaAl-As devices with St
This device utilizes the fact that the conductivity type of the additive layer changes from n-type to p-type. A GaAs substrate is immersed in a mixed melt of Ga, At, As, and Si, slowly cooled, and then placed on the GaAs substrate. A GaAtAs liquid phase growth layer doped with St is grown. When such liquid phase growth is performed, AtA is produced as the liquid phase growth layer grows as shown in the graph of Figure 1.
The s mixed crystal ratio In the region below the broken line), silicon becomes a p-type impurity and a wafer having a p-n junction is obtained. After that, so that only the liquid phase growth layer of GaAAAs:Si remains,
The GaAs substrate is removed, for example, by chemical etching to form an LED chip 7010 as shown in FIG.

〔背景技術の問題点〕[Problems with background technology]

ところで、上記のようなＬＥＩ）チッ７”１０ではＡｔ
Ａ　ｓ混晶比の大きい領域では禁制帯幅が大きく、光が
吸収されにくいため、ｐｎ接合面で発生した光はｎ型Ｇ
ａＡｔＡｓ層１１ｎから取り出され、ｐ型ＧａＡＡＡｓ
　４１１　ｐがグイボンディング面として使用される。By the way, in the above LEI) chip 7"10, At
In the region with a large A s mixed crystal ratio, the forbidden band width is large and light is difficult to be absorbed, so the light generated at the pn junction is an n-type G
The p-type GaAAAs is taken out from the aAtAs layer 11n.
411p is used as the Gui bonding surface.

ここで、ｐ型ＧａＡｔＡ　ｓ層１１ｐ」二にオーミック
接触を得るための金とベリリウムの合金薄膜を形成し、
この薄膜上に前述のＧ　ａＡ　ｓ系のＬＥＤで使用した
ようなゲルマニウム等の共晶合金をグイボンディング剤
として使用すると、グイボンディング時の加熱によシダ
ルマニウム（或いはすす、シリコン等）が半導体表面に
拡散して金属電極のオーミック性を肌性することになる
。これはＧａＡｔＡｓ結晶に対しダルマニウムがｎ型不
純物となるからで、同様に、すす、シリコン等もｎ型不
純物となる／こめ、これらの元素を含む金共晶技術を用
いた１）（１便なグイボンディング法を用いることがで
きない。Here, an alloy thin film of gold and beryllium is formed on the p-type GaAtAs layer 11p to obtain ohmic contact.
If a eutectic alloy such as germanium, such as that used in the GaAs-based LED described above, is used as a bonding agent on this thin film, sidermanium (or soot, silicon, etc.) will be deposited on the semiconductor surface due to the heating during bonding. It diffuses and changes the ohmic properties of the metal electrode to skin-like properties. This is because dalmanium becomes an n-type impurity for GaAtAs crystals, and similarly, soot, silicon, etc. also become n-type impurities. It is not possible to use a flexible bonding method.

このため、ＧａＡｓ基板　ＬＥＤでは、銀ペースト、銀
・すず半田等用いてダイボンデイングラ行っていたが、
銀ペーストを用いた場合には、製品完成後、素子に通電
中に銀がｐｎ接合部にｇ効してショートすることがあシ
、銀・すず半田の場合にはオーミック接触用に素子表面
に形成した金とすすが相互に拡散して素子が剥離しゃす
くなるという信頼性上の問題があった。For this reason, die bonding was performed using silver paste, silver/tin solder, etc. for GaAs substrate LEDs.
When silver paste is used, after the product is completed, while the device is energized, the silver may cause a g-effect on the pn junction, causing a short circuit.In the case of silver/tin solder, it may be necessary to apply a paste to the surface of the device for ohmic contact. There was a reliability problem in that the formed gold and soot diffused into each other, making it easy for the device to peel off.

〔発明の目的〕[Purpose of the invention]

この発明は上記のような点に鑑みなされたもので、例え
ばｐ型ＧａＡＡＡｓ等に対しても良好なオーミック接触
性を有し、信頼性が高く簡便なグイボンディングが可能
な金属電極を備えた化合物半導体装置を提供しようとす
るものである。This invention was made in view of the above points, and provides a compound having a metal electrode that has good ohmic contact properties even with p-type GaAAAs, etc., and allows for highly reliable and easy bonding. The purpose is to provide a semiconductor device.

〔発明の概要〕[Summary of the invention]

すなわち、この発明に係る化合物半導体装置では、例え
ばＧａＡｔＡｓ　ＬＥＤ等、一つの表面にｐ型化合物半
導体層を有する半導体素子のｐ型化合物半導体層表面に
、例えばベリリウム或いは亜鉛と金との合金からなる、
上記ｐ型化合物半導体層とオーミック接触が可能な第１
の金属薄膜を形成し、この第１の金属薄膜上に例えばＴ
ｉ。That is, in the compound semiconductor device according to the present invention, the surface of the p-type compound semiconductor layer of a semiconductor element having a p-type compound semiconductor layer on one surface, such as a GaAtAs LED, is made of, for example, beryllium or an alloy of zinc and gold.
A first layer capable of making ohmic contact with the p-type compound semiconductor layer.
A thin metal film of, for example, T is formed on this first metal thin film.
i.

Ｔａ　、　Ｍｏ　、　、Ｎｉ　、　Ｗ等を主成分とした
高融点金属からなる第２の金属薄膜を形成し、さらにこ
の第２の金属薄膜上に例えばダルマニウム、シリコン、
或いはすす等と金との共晶合金からなる低融点の第３の
朶属薄膜を形成したものであシ、上記第１０金桃薄膜に
よシ良好なオーミック接触を得るとともに、高融点の第
２の金属膜が、低融点の第３の金属薄膜中のダルマニウ
ム、シリコン或いはすす等がグイボンディングの加熱時
にｐ型化合物半導体層中に拡散する現象を防止するよう
にしたものである。A second metal thin film made of a high-melting point metal mainly composed of Ta, Mo, Ni, W, etc. is formed, and on this second metal thin film, for example, dalmanium, silicon, etc. are formed.
Alternatively, a third metal thin film with a low melting point made of a eutectic alloy of soot and gold is formed. The metal film No. 2 is designed to prevent dalmanium, silicon, soot, etc. in the third metal thin film having a low melting point from diffusing into the p-type compound semiconductor layer during heating for bonding.

〔発明の実施例〕[Embodiments of the invention]

以下図面を参照してこの発明の一実施例をＧａＡＡＡａ
　：　Ｓ　ｉ赤外ＬＥＤを例にとシ説明する。An embodiment of the present invention will be described below with reference to the drawings.
: This will be explained using Si infrared LED as an example.

壕ず第３図においてＧａＡｓ　（１００）基板２１上に
＼Ｇａ中にＡｓ　、　ＡＩ、およびＳｔを含む融液を接
触させて徐冷し、このＧａＡｓ　（１００）基板２１上
にＧａＡＡＡｓ層２２を形成する。この際、Ａｔの偏析
係数は極めて太きいため、融液中のＡｔ含有量に比らべ
ＧａＡｔＡ　ｓ層２２中に含まれるＡｔＡｓ混晶比は極
めて小さくなシ、例えば９００℃から徐冷成長を行って
ＧａＡｔＡｓ層２２の初期の混晶比Ｘを０３程度として
も、７００℃前後に温度が低下した時点で形成された成
長層におけるＡ７！、Ａｓ混晶比は殆んど０と々る。こ
の間温度の低下によって、導電型決定不純物としてのＳ
ｉの作用が変化し、ＧａＡＡＡｓ液相成長層は、成長方
向に沿ってｎ型からｐ型に変化し、結果として、ｎ型Ｇ
ａＡＡＡｓ　ＪｆＪ　２２　ｎ　。In FIG. 3, a GaAs (100) substrate 21 is brought into contact with a melt containing As, AI, and St in Ga and slowly cooled to form a GaAAAs layer 22 on the GaAs (100) substrate 21. do. At this time, since the segregation coefficient of At is extremely large, the AtAs mixed crystal ratio contained in the GaAtAs layer 22 is extremely small compared to the At content in the melt. Even if the initial mixed crystal ratio X of the GaAtAs layer 22 is set to about 0.03, A7! , the As mixed crystal ratio is almost 0. During this time, due to the decrease in temperature, S as a conductivity type determining impurity
The action of i changes, and the GaAAAs liquid phase growth layer changes from n-type to p-type along the growth direction, resulting in n-type G
aAAAs JfJ 22 n.

ｐ型ＧａＡ７Ａｓ層２２ｐが形成される。A p-type GaA7As layer 22p is formed.

次いで、前述したように、高い発光効率を得るために発
光なｎπすＧａｋｔＡＳＪ音２２ｎから取シ出す必要が
あるため、ｎ型ＧａＡｔＡｓ　）１５２２　ｎ側のＧａ
Ａｓ基板２１を除去する。Next, as mentioned above, in order to obtain high luminous efficiency, it is necessary to extract light from the n
The As substrate 21 is removed.

この後、第４図に示すように上記ｐ型ＧａＡｔＡ８）Ｎ
　２２　ｐ表面に１％のベリリウムを含む金ベリリウム
合金層２３を約０．５μｍ被着し、さらに、この金ベリ
リウム合金１缶２３上にこの金ベリリウム合金層２３の
変成（酸化等）防止の目的で、層厚が０．５μｍの純金
層２４を形成する。After this, as shown in FIG. 4, the p-type GaAtA8)N
22 A gold-beryllium alloy layer 23 containing 1% beryllium is deposited on the p surface to a thickness of approximately 0.5 μm, and a layer of gold-beryllium alloy 23 is deposited on the gold-beryllium alloy 1 can 23 for the purpose of preventing metamorphosis (oxidation, etc.) of the gold-beryllium alloy layer 23. Then, a pure gold layer 24 having a layer thickness of 0.5 μm is formed.

次いでｎ型ＧａＡｔＡｓ　Ｊ’ｉｊｉ　２２　ｎ　ｌに
０．５％のゲルマニウムを含む金ゲルマニウム合金層２
５を約０．５μ？ｎ″＄着し、さらにこの金ダルマニウ
ム合金層２５上にこの層の変成防止の目的で純金層２６
を約０，５μｍの層厚で積層被着する。Next, a gold-germanium alloy layer 2 containing 0.5% germanium in n-type GaAtAs 22nl is formed.
5 about 0.5 μ? Furthermore, a pure gold layer 26 is deposited on this gold-dalmanium alloy layer 25 for the purpose of preventing metamorphosis of this layer.
are applied in a layered manner with a layer thickness of approx. 0.5 μm.

次に４００℃程度の熱処理を行い、上記金ぺＩＪ　ＩＪ
ウム合金層２３および金ゲルマニウム合金層２５とそれ
ぞれの合金層に接する化合物半導体層とのオーミック接
触を得る。Next, heat treatment at about 400°C is performed to
Ohmic contact is obtained between the gold-germanium alloy layer 23 and the gold-germanium alloy layer 25 and the compound semiconductor layer in contact with each alloy layer.

続いて、ｐ型ＧａＡＡＡｓ層２２ｐ側の電極となる金ベ
リリウム合金層２３およびその上の純金層２４上にＴｉ
　（チタン）層ｊ２７を０．５μｍ（１）層厚で被着し
、さらにとのＴｉＪｉ２７上にこの層の変成防止の目的
で、純金を０．５μｍ被着し、さらにこの純金層２８上
にダルマニウムを１２条含む金合金からなるマウント用
金合金層２９を１．０μの層厚で形成する。Subsequently, Ti is deposited on the gold-beryllium alloy layer 23, which will become the electrode on the p-type GaAAAs layer 22p side, and on the pure gold layer 24 thereon.
A (titanium) layer j27 is deposited with a thickness of 0.5 μm (1), and pure gold is deposited with a thickness of 0.5 μm on top of the TiJi layer 27 for the purpose of preventing metamorphosis of this layer, and further on this pure gold layer 28. A mounting gold alloy layer 29 made of a gold alloy containing 12 dallmanium strips is formed with a layer thickness of 1.0 μm.

その後、光の取シ出し面となるｎ型ＧａＡＨＡｓ＠　２
２　ｎ側の金属電極層をフォトエツチングによって所定
の形状に・ぐターニングし、ウェハをグイシングしてＬ
ＥＤチッン°を児成する。この後、リードフレーム上に
チップを載置した状態でリードフレームおよびチップを
加熱し、上記マウント用合金層２９によシチップをダイ
ポンディングし、さらに外囲器への組み込みを行って製
品とする。After that, n-type GaAHAs @ 2 which becomes the light extraction surface
2 Turn the metal electrode layer on the n side into a predetermined shape by photo-etching, and guising the wafer to form an L
Generates ED Chin°. Thereafter, with the chip placed on the lead frame, the lead frame and the chip are heated, the chip is die-bonded onto the mounting alloy layer 29, and is further assembled into an envelope to produce a product.

ここで上記金ベリリウム合金層２３およびＴｉ層２７上
に形成した純金層２４．２８は、金べ１７１Ｊウム合金
層２３およびＴｉ層２７の変成防止のために設けたもの
で、オーミック接触を得るだめの熱処理や、グイポンデ
ィング時の加熱処理等の熱処理中に接する金合金層と混
じり合い、結果としてチップのｐ型ＧａＡＡＡｓ層２２
ｐ側には金べＩＪ　リウム合金層２３と純金層２４とが
ｕ１合した金とベリリウムの合金からなる第１の金属薄
膜３１と、高Ｆａ点金属のＴ１からなる第２の金属薄膜
３２と、純金層２８とマウント用金合金層２９とが融合
した金とゲルマニウムの合金からなる第３の金属薄膜３
３とが形成される。Here, the pure gold layers 24 and 28 formed on the gold beryllium alloy layer 23 and the Ti layer 27 are provided to prevent metamorphosis of the gold beryllium alloy layer 23 and the Ti layer 27, and are necessary to obtain ohmic contact. The p-type GaAAAs layer 22 of the chip mixes with the contacting gold alloy layer during the heat treatment such as the heat treatment of
On the p side, there is a first metal thin film 31 made of an alloy of gold and beryllium in which the beryllium alloy layer 23 and the pure gold layer 24 are combined, and a second metal thin film 32 made of T1, a high Fa point metal. , a third metal thin film 3 made of an alloy of gold and germanium in which a pure gold layer 28 and a mounting gold alloy layer 29 are fused.
3 is formed.

このような装置において、チップの裏面の第３の金属薄
膜３３は低融点金ＪＡであるため、素子基台となるリー
ドフレーム上にチップを載置した状態でリードフレーム
およびチップを加熱することにより、チップを容易にグ
イポンディングすることができる。In such a device, since the third metal thin film 33 on the back surface of the chip is low-melting gold JA, heating the lead frame and the chip while the chip is placed on the lead frame, which serves as the element base, , chips can be easily distributed.

一方、Ｔｉ層２７から々る微細な第２の金属薄膜３２が
ダイポンディング時の加熱において、第３の金属薄膜３
３中のダルマニウムが第２の金属薄膜３２を超えてｐ　
３ｊｌ　ＧａＡＡＡｓ　Ｊ脅２２　ｐに拡散することを
阻止するため、ｐ型ＧａＡｔＡｓ層２２ｐと金属電極と
のオーミックコンタクトを阻害せずに金とダルマニウム
の共晶合金による簡易で且つ信頼性の高いグイボンディ
ングを行うことができる。On the other hand, when the fine second metal thin film 32 falling from the Ti layer 27 is heated during die bonding, the third metal thin film 3
Dalmanium in 3 exceeds the second metal thin film 32 and p
In order to prevent GaAAAs from diffusing into the 3jl GaAAAs layer 22p, simple and highly reliable bonding using a eutectic alloy of gold and dahmanium is performed without inhibiting ohmic contact between the p-type GaAtAs layer 22p and the metal electrode. It can be performed.

尚、上記実施例の他に、ｐｍのオーミック電極となる第
１の金属層としては金と亜鉛との合金も使用可能であシ
、また、第２の金属層としては、チタンの代シにタンタ
ル、モリブデン。In addition to the above embodiments, an alloy of gold and zinc can be used as the first metal layer that becomes the pm ohmic electrode, and an alloy of gold and zinc can be used instead of titanium as the second metal layer. tantalum, molybdenum.

ニッケル、タングステン等緻折な構造の他の高融点金属
を用いてもよい。更に第３の金属層のマウント用共晶合
金としては、金とシリコン、金とすす等を主成分とする
共晶合金を用いても良い。Other high melting point metals with a fine structure such as nickel and tungsten may also be used. Further, as the eutectic alloy for mounting the third metal layer, a eutectic alloy containing gold and silicon, gold and soot, etc. as main components may be used.

また、上記第１．第２．第３の金Ｍ層３ノ。In addition, the above 1. Second. Third gold M layer 3 no.

３２．３３の被着される素子としては、シリコンを添加
したＧａＡｔＡｓ、　ＬＥＤに限られるものではなく、
ＧａＡｓ　（第１図のｘ　＝　Ｏとなる部位はＡｔの含
まれないＧａＡｓ結晶とみなせる）　、ＧａＰ或いはＩ
ｎＰ等との■■化合物等、他の化合物半導体を用いた素
子でもよい。The elements to be deposited in 32.33 are not limited to silicon-doped GaAtAs, LEDs, etc.
GaAs (the part where x = O in Figure 1 can be regarded as a GaAs crystal that does not contain At), GaP or I
Elements using other compound semiconductors such as ■■ compounds with nP etc. may also be used.

［発明の効果〕 以上のようにこの発明によれば、良好々オーミック接触
性を有し、金共晶によるｆｆｌｊ便で信頼性の高いグイ
ポンディングが可能な金ノ１４軍極を備えた化合物半導
体装置を提供することができる。[Effects of the Invention] As described above, according to the present invention, a compound is provided with a gold-plated metal pole that has good ohmic contact properties and is capable of highly reliable guiponding using gold eutectic fflj. A semiconductor device can be provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はＧａＡＡＡｓ液相成長層におけるＡｔＡｓ混晶
比を示すグラフ、第２図はＧａＡＡＡｓ　ＬＥＤチッゾ
を説明する断面図、第３図および第４図はそれぞれこの
発明の一実施例に係る化合物半導体装「を製造過程順に
示す断面図である。 ２２−−・ＧａＡＡＡｓ層、２２　ｐ−ｐ型ＧａＡＡＡ
ｓ層、２２ｎ・・・ｎ均ｉｑ　ＧａＡＡＡｓ層、２３・
・・金ベリリウム合金層、２４・・・純金層、２５・・
・金ダルマニウム合金層、２６・・・純金層、２７・・
・Ｔｉ層、２８・・・純金層、２９・・・マウント粗金
合金Ｊハ１、ｓ　１・・・第１の金属薄膜、３２・・・
第２の金属薄膜、３３・・・第３の金属薄膜。 第１図 ＡＩＡＳ　−ｚｐａｅｅｒし 第２　図 第３図FIG. 1 is a graph showing the AtAs mixed crystal ratio in a GaAAAs liquid phase growth layer, FIG. 2 is a cross-sectional view illustrating a GaAAAs LED chip, and FIGS. 3 and 4 are compound semiconductors according to an embodiment of the present invention. 22--GaAAAs layer, 22 p-p type GaAAA
s layer, 22n...n uniform iq GaAAAs layer, 23.
...Gold-beryllium alloy layer, 24...Pure gold layer, 25...
・Gold-dalmanium alloy layer, 26...Pure gold layer, 27...
・Ti layer, 28... Pure gold layer, 29... Mount coarse gold alloy Jc1, s 1... First metal thin film, 32...
second metal thin film, 33... third metal thin film; Figure 1 AIAS-zpaeer Figure 2 Figure 3

Claims (4)

【特許請求の範囲】[Claims] （１）　少なくとも一つの光面にｐ型化合物半導体層を
有する半導体素子と、上記ｐ型化合物半導体層表面に形
成されこのｐ型化合物半導体層とオーミック接触が可能
な第１の金属薄膜と、この第１の金属薄膜上に形成され
た高融点金属からなる第２の金属薄膜と、上記第２の金
属薄膜上に形成され金と共晶をなす金属と金との合金よ
シなる低融点の第３の金属薄膜とを具備していることを
特徴とする化合物半導体装置。(1) a semiconductor element having a p-type compound semiconductor layer on at least one optical surface; a first metal thin film formed on the surface of the p-type compound semiconductor layer and capable of making ohmic contact with the p-type compound semiconductor layer; A second metal thin film made of a high melting point metal formed on the first metal thin film, and a low melting point metal thin film made of a metal and gold alloy formed on the second metal thin film and forming a eutectic with gold. A compound semiconductor device comprising: a third metal thin film. （２）上記第１の金属薄膜がぺＩＪ　ＩＪウムおよび亜
鉛のいずれかと金との合金であることを特徴とする特許
請求の範囲第１項記載の化合物半導体装置。(2) The compound semiconductor device according to claim 1, wherein the first metal thin film is an alloy of gold and any one of aluminum and zinc. （３）上記第２の金属薄ｊ漠が’Ｅｌ’）　＋　Ｔａ　
＋　Ｍｏ　ｒＮｉ、Ｗのいずれかを主成分としているこ
とを特徴とする特許請求の範囲第１項まだは第２項記載
の化合物半導体装置。(3) The second metal layer is 'El') + Ta
+ Mor The compound semiconductor device according to claim 1 or claim 2, characterized in that the main component is either Ni or W. （４）上記第３の金属薄膜がゲルマニウムおよびシリコ
ンおよびすすのいずれか一つ以上と金との共晶合金であ
ることを特徴とする特許請求の範囲第１項乃至第３項い
ずれか記載の化合物半導体装置。(4) The third metal thin film is a eutectic alloy of gold and one or more of germanium, silicon, and soot. Compound semiconductor device.
JP58121368A 1983-07-04 1983-07-04 Compound semiconductor device Pending JPS6014445A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58121368A JPS6014445A (en) 1983-07-04 1983-07-04 Compound semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58121368A JPS6014445A (en) 1983-07-04 1983-07-04 Compound semiconductor device

Publications (1)

Publication Number Publication Date
JPS6014445A true JPS6014445A (en) 1985-01-25

Family

ID=14809509

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58121368A Pending JPS6014445A (en) 1983-07-04 1983-07-04 Compound semiconductor device

Country Status (1)

Country Link
JP (1) JPS6014445A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05234434A (en) * 1992-02-24 1993-09-10 Showa Electric Wire & Cable Co Ltd Manufacturing device for tape-shaped cable

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05234434A (en) * 1992-02-24 1993-09-10 Showa Electric Wire & Cable Co Ltd Manufacturing device for tape-shaped cable

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