JP3854467B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP3854467B2
JP3854467B2 JP2001026255A JP2001026255A JP3854467B2 JP 3854467 B2 JP3854467 B2 JP 3854467B2 JP 2001026255 A JP2001026255 A JP 2001026255A JP 2001026255 A JP2001026255 A JP 2001026255A JP 3854467 B2 JP3854467 B2 JP 3854467B2
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conductive layer
semiconductor
semiconductor substrate
semiconductor chip
layer
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JP2002231735A (en
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隆史 佐藤
浩二郎 池田
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Renesas Technology Corp
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Renesas Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Abstract

PROBLEM TO BE SOLVED: To enhance bonding strength between a lead and a pellet on which a semiconductor element is formed. SOLUTION: On the rear surface of a semiconductor substrate 1, a conductive film 2 of Au and a eutectic layer 3 of Si contained in the semiconductor substrate are formed followed by formation of a conductive film 4 of AuSb and a conductive film 5 of Au. The semiconductor substrate 1 is then diced to form a pellet having a unit diode element and that pellet is mounted such that the conductive film 5 touches a lead 6A. Subsequently, it is heat treated to form a brazing material containing materials forming the conductive film 2, the eutectic layer 3, the conductive film 4 and the conductive film 5.

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置の製造技術に関し、リードにペレットを搭載し、その外側を封止してなる半導体装置の製造方法に適用して有効な技術に関するものである。
【０００２】
【従来の技術】
たとえばダイオード素子の形成されたペレットをリードの端部（タブ）に搭載し、その外側を封止してなるパッケージにおいては、陽極側と陰極側とが対となったリードを用意し、ペレットの裏面電極を、陽極側もしくは陰極側のリードのタブに接着し、ペレットの表面電極と他方のリードのタブとをボンディングワイヤ（以下、単にワイヤという）を用いて接続し、ペレット、ワイヤおよびリードをレジン材料で覆ったパッケージとなっている。
【０００３】
ここで、上記したペレットの裏面電極となり、ペレットとリードとを接着する蝋材は、ＡｕとＳｉ（シリコン）とからなるＡｕ−Ｓｉ共晶層であり、ペレットとリードとを熱圧着する際に、そのＡｕ−Ｓｉ共晶層が液状化したものである。この蝋材の量が多いと接着強度が確保できるので、Ａｕからなる裏面電極の厚さを厚くしたり、ペレットが接着する部分のリードにＡｕ箔を載せることにより、接着強度の向上を図る場合がある。
【０００４】
ここで、種々のパッケージの構造および機能については、たとえば、２０００年７月２８日、株式会社工業調査会発行、「エレクトロニクス実装大辞典」に記載があり、中でもダイオードのパッケージについては、ｐ５２２〜ｐ５２３に記載がある。
【０００５】
【発明が解決しようとする課題】
しかしながら、上記したパッケージの構造およびその製造方法においては、以下のような問題があることを本発明者らは見出した。
【０００６】
すなわち、たとえばダイオード素子の形成されたペレットにおいては、Ａｓ（ヒ素）またはＳｂ（アンチモン）が導入されたｎ型のシリコン基板が用いられる。そのため、ペレットの裏面電極はｎ型のシリコン基板とオーミックを取るために、Ａｕに１％程度のＳｂが入ったＡｕＳｂが用いられる。個々のペレット（半導体チップ）に分割する前の半導体ウェハの状況下でこのＡｕＳｂを形成し、上記した蝋材となるＡｕ−Ｓｉ共晶層を形成するための約３７０℃以上の熱処理を施すと、ＡｕＳｂの融点が約３６０℃であることからＡｕＳｂが液状化してしまうことになる。液状化したＡｕＳｂは、表面張力により半導体ウェハ面内に島状に点在することになり、半導体ウェハ面内にはＡｕ−Ｓｉ共晶層が形成される領域と形成されない領域とが出来上がってしまうことになる。そのため、半導体ウェハを分割し、個々のペレットを形成した際に、裏面電極（蝋材）の形成されていないペレットが形成されてしまう問題がある。
【０００７】
一方、上記したＡｕ−Ｓｉ共晶層を形成するための熱処理を、個々のペレットに分割した後のペレットとリードとを熱圧着する際に行う場合においては、ペレットとリードとを押さえつける力が働くことから、その押圧力によって液状化したＡｕＳｂがペレットとリードとの界面において伸びる結果、島状に点在してしまう問題を防ぐことができる。しかしながら、上記熱圧着はペレットに形成された半導体素子の特性の変化を防ぐために、できるだけ短時間で行わなければならないために、上記したペレットとリードとを押さえつける力の調整を熱圧着工程中に行うことが困難になっている。そのため、所望のＡｕ−Ｓｉ共晶層が形成されない場合があり、ペレットとリードとの接着強度が低下する問題がある。また、ペレットとリードとの接着強度が低下すると、実装基板にパッケージを実装する際のはんだ熱により、ペレットとリードとが剥離するという問題がある。
【０００８】
また、実装基板にパッケージを実装する際のはんだとしては、環境保全の観点から鉛を含まないはんだを用いることが注目されている。しかしながら、この鉛を含まないはんだは鉛を含むはんだの融点に比べて高いことから、上記したパッケージに伝わる熱が高くなる。そのため、さらにペレットとリードとの接着強度が低下し、ペレットとリードとが剥離しやすくなるという問題がある。
【０００９】
本発明の目的は、半導体装置が有するペレットとリードとの接着強度を向上することにある。
【００１０】
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。
【００１１】
【課題を解決するための手段】
本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。
【００１２】
すなわち、本発明は、半導体基板の裏面に第１導電層を形成する工程と、前記半導体基板と前記第１導電層との界面に前記半導体基板および前記第１導電層の共晶層を形成する工程と、前記第１導電層の表面に第２導電層を形成する工程と、前記第２導電層形成後に前記半導体基板を個々の半導体チップに分割する工程と、前記半導体チップの裏面と半導体チップ搭載部材とが接触するように前記半導体チップを前記半導体チップ搭載部材に搭載する工程と、前記半導体チップを前記半導体チップ搭載部材に搭載後に前記共晶層および前記第２導電層を溶融し、前記共晶層および前記第２導電層の混在する第１電極を形成することにより、前記半導体チップと前記半導体チップ搭載部材とを接着する工程とを含むものである。
【００１３】
また、本発明は、半導体基板の裏面に第１導電層を形成する工程と、前記半導体基板と前記第１導電層との界面に前記半導体基板および前記第１導電層の化合物層を形成する工程と、前記第１導電層の表面に第２導電層を形成する工程と、前記第２導電層形成後に前記半導体基板を個々の半導体チップに分割する工程と、前記半導体チップの裏面と半導体チップ搭載部材とが接触するように前記半導体チップを前記半導体チップ搭載部材に搭載する工程と、前記半導体チップを前記半導体チップ搭載部材に搭載後に前記化合物層および前記第２導電層を溶融し、前記化合物層および前記第２導電層の混在する第１電極を形成することにより、前記半導体チップと前記半導体チップ搭載部材とを接着する工程とを含むものである。
【００１４】
上記の本発明によれば、半導体基板の裏面全面において確実に共晶層または化合物層を形成することができるので、その共晶層または化合物層によって半導体基板と半導体チップ搭載部材との接着強度を向上することが可能となる。
【００１５】
【発明の実施の形態】
以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。
【００１６】
次に、図１〜図９を用いて、本実施の形態の半導体装置の製造方法をその工程順に説明する。
【００１７】
まず、図１に示すように、ダイオード素子（半導体素子（図示は省略））およびそのダイオード素子と電気的に接続された表面電極（図示は省略）が形成された半導体基板１を用意する。この半導体基板１は、ｎ型の不純物（たとえばＡｓ（ヒ素））が導入され、複数のダイオード用の半導体チップ領域が形成されたＳｉ（シリコン）ウェハからなり、裏面がグラインディングによる研削とウェットエッチングが施され、最終的なダイオードのパッケージ形態に合わせて薄くされているものである。
【００１８】
次に、図２に示すように、半導体基板１の裏面に、たとえば膜厚約０．３μｍのＡｕ膜を蒸着することにより、導電性膜２（第１導電層）を形成する。続いて、図３に示すように、半導体基板１に約３７０℃〜４９０℃の熱処理を施すことにより、ＡｕおよびＳｉの共晶層３を形成する。上記熱処理においては、その温度を約３７０℃とした場合においては、その時間を約２０分とすることを例示できる。
【００１９】
本実施の形態においては、熱処理により共晶層３を形成する際に導電性膜２はＳｂを含んでいないことから、導電性膜２の融点が熱処理時の温度より低下することを防ぐことができる。すなわち、熱処理により導電性膜２が液状化し、液状化した導電性膜２が表面張力により半導体基板１の裏面に島状に点在することを防ぐことができる。それにより、半導体基板１の裏面全面において確実に共晶層３を形成することが可能となる。この共晶層３を用いることにより、後の工程でペレットとリードとを接着することが可能となる。
【００２０】
また、本実施の形態では、導電性膜２としてＡｕ膜を蒸着し、そのＡｕ膜と半導体基板１が含むＳｉとの共晶層３を形成する場合について例示したが、導電性膜２としてシリサイド膜を形成することが可能な金属膜（たとえばＰｄ（パラジウム）膜）を形成し、その金属膜と半導体基板１が含むＳｉとを反応させて、共晶層３の代わりにシリサイド膜を形成してもよい。このシリサイド膜を用いても、共晶層３を用いた場合と同様に後の工程でペレットとリードとを接着することが可能となる。
【００２１】
次に、図４に示すように、たとえば膜厚約０．３μｍのＡｕＳｂ膜を蒸着することにより、導電性膜４（第２導電層）を形成する。導電性膜４が含むＳｂは、後の工程で形成される裏面電極に含まれることにより、その裏面電極が半導体基板１とオーミックを取ることが可能となる。また、導電性膜４としては、半導体基板１とオーミックを取ることができる他の金属（たとえばＮｉ（ニッケル））膜を形成してもよい。
【００２２】
続いて、図５に示すように、たとえば膜厚約０．３μｍのＡｕ膜を蒸着することにより、導電性膜５（第３導電層）を形成する。Ａｕ膜は化学反応を起こしにくい材質であることから、この導電性膜５を形成することにより、導電性膜４が酸化してしまうことを防ぐことができる。また、導電性膜５としては、導電性膜４の酸化を防ぐ他の金属（たとえばＡｇ（銀））膜を形成してもよい。
【００２３】
次に、半導体基板１をダイシングにより分割することで、単位素子のダイオード素子を有するペレット（半導体チップ）を形成した後、図６に示すように、半導体基板１の裏面に形成された導電性膜５がリード６Ａ（半導体チップ搭載部材）に接触するようにそのペレットをリード６Ａに搭載する。リード６Ａは、たとえばＣｕ（銅）からなり、その表面には膜厚が約３μｍ〜１０μｍのＡｇ膜７が予めめっき法にて形成されている。
【００２４】
次に、図７に示すように、約３７０℃〜４９０℃の熱処理により、半導体基板１の裏面に形成された導電性膜２、共晶層３、導電性膜４および導電性膜５を溶融させることにより、導電性膜２、共晶層３、導電性膜４および導電性膜５のそれぞれを形成していた材料（Ａｕ−Ｓｉ−Ｓｂ合金）を含む蝋材８を形成し、半導体基板１の裏面とリード６Ａとを接着する。この蝋材８を形成する際の熱処理は、その温度を約３７０℃とした場合においては、その時間を約２０分とすることを例示できる。
【００２５】
蝋材８が形成される前においては、図３を用いて前述したように、半導体基板１の裏面全面においてＡｕおよびＳｉからなる共晶層３が確実に形成されているので、溶融した共晶層３を含む蝋材８により、半導体基板１の裏面とリード６Ａとの接着強度を向上することができる。
【００２６】
また、蝋材８においては、上記熱処理時の熱によって、導電性膜４が含んでいたＳｂと共晶層３が含んでいたＳｉとが反応物を生成するので、半導体基板１と蝋材８との間でオーミックを取ることができる。すなわち、蝋材８を単位素子のダイオード素子を有するペレットの裏面電極として用いることができる。
【００２７】
次に、図８に示すように、半導体基板１に形成された表面電極９と上記ペレットが搭載されたリード６Ａの対極側のリード６Ｂとを、たとえばＡｕワイヤ１０を用いてワイヤボンディングする。
【００２８】
次に、リード６Ａ、６Ｂ、ペレットおよびＡｕワイヤ１０を、たとえばレジン１１により封止することにより、リード６Ａ、６Ｂの外端部を実装用に外部に露出させたレジンパッケージを形成する。続いて、図９に示すように、レジン１１の外周面に、カラーバンド等の極性識別マーク１２を形成し、本実施の形態の半導体装置を製造する。
【００２９】
上記のように製造した半導体装置は、たとえばリード６Ａ、６Ｂの外端部を実装基板にはんだを用いて接続することにより実装することができる。この時、Ｐｂ（鉛）を含まないはんだ（以下、鉛フリーはんだとする）を用いた場合においては、鉛フリーはんだの融点はＰｂを含むはんだの融点に比べて高いことから、本実施の形態の半導体装置に伝わる熱が高くなる。上記したように、本実施の形態の半導体装置においては、共晶層３を含む蝋材８により、半導体基板１の裏面とリード６Ａとの接着強度が向上できるので、鉛フリーはんだを用いて半導体装置を実装する場合の熱により、半導体基板１とリード６Ａとが剥離することを防ぐことができる。
【００３０】
以上、本発明者によってなされた発明を発明の実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。
【００３１】
たとえば、前記実施の形態における蝋材（裏面電極）の形成方法は、ペレットとリードとを接着して形成する三端子素子（トランジスタ）において適用してもよい。
【００３２】
【発明の効果】
本願によって開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下の通りである。
（１）たとえばＳｂを含まないＡｕ膜と半導体基板が含むＳｉとの共晶層を形成するので、半導体基板の裏面全面において確実にその共晶層を形成することができる。
（２）たとえば半導体基板の裏面全面において確実にＡｕ膜とＳｉとの共晶層を形成することができるので、半導体基板とリードとの接着強度を向上することができる。
【図面の簡単な説明】
【図１】本発明の一実施の形態である半導体装置の製造工程中の要部断面図である。
【図２】図１に続く半導体装置の製造工程中の要部断面図である。
【図３】図２に続く半導体装置の製造工程中の要部断面図である。
【図４】図３に続く半導体装置の製造工程中の要部断面図である。
【図５】図４に続く半導体装置の製造工程中の要部断面図である。
【図６】図５に続く半導体装置の製造工程中の要部断面図である。
【図７】図６に続く半導体装置の製造工程中の要部断面図である。
【図８】図７に続く半導体装置の製造工程中の要部断面図である。
【図９】図８に続く半導体装置の製造工程中の要部断面図である。
【符号の説明】
１ 半導体基板
２ 導電性膜（第１導電層）
３ 共晶層
４ 導電性膜（第２導電層）
５ 導電性膜（第３導電層）
６Ａ リード（半導体チップ搭載部材）
６Ｂ リード
７ Ａｇ膜
８ 蝋材（裏面電極）
９ 表面電極
１０ Ａｕワイヤ
１１ レジン
１２ 極性識別マーク[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a manufacturing technique of a semiconductor device, and relates to a technique effective when applied to a manufacturing method of a semiconductor device in which pellets are mounted on leads and the outside thereof is sealed.
[0002]
[Prior art]
For example, in a package in which a pellet in which a diode element is formed is mounted on an end (tab) of a lead and the outside is sealed, a lead in which the anode side and the cathode side are paired is prepared. The back electrode is bonded to the anode or cathode lead tab, the pellet surface electrode and the other lead tab are connected using a bonding wire (hereinafter simply referred to as a wire), and the pellet, wire and lead are connected. The package is covered with resin material.
[0003]
Here, the wax material that becomes the back electrode of the pellet and bonds the pellet and the lead is an Au-Si eutectic layer composed of Au and Si (silicon). When the pellet and the lead are thermocompression bonded, The Au—Si eutectic layer is liquefied. When the amount of this wax material is large, the adhesive strength can be secured. Therefore, when the thickness of the back electrode made of Au is increased or the Au foil is placed on the lead where the pellet adheres, the adhesive strength is improved. There is.
[0004]
Here, the structures and functions of various packages are described, for example, in “Industrial Electronics Encyclopedia” issued on July 28, 2000, published by Industrial Research Co., Ltd. Among them, the diode packages are p522 to p523. There is a description.
[0005]
[Problems to be solved by the invention]
However, the present inventors have found that the above-described package structure and manufacturing method have the following problems.
[0006]
That is, for example, in a pellet formed with a diode element, an n-type silicon substrate into which As (arsenic) or Sb (antimony) is introduced is used. Therefore, AuSb containing about 1% of Sb in Au is used for the back electrode of the pellet to make ohmic contact with the n-type silicon substrate. When this AuSb is formed under the condition of the semiconductor wafer before being divided into individual pellets (semiconductor chips), and a heat treatment of about 370 ° C. or higher is performed to form the Au—Si eutectic layer that becomes the above-described wax material. Since the melting point of AuSb is about 360 ° C., AuSb is liquefied. The liquefied AuSb is scattered in an island shape in the semiconductor wafer surface due to the surface tension, and an area where the Au—Si eutectic layer is formed and an area where the Au—Si eutectic layer is not formed are formed in the semiconductor wafer surface. It will be. Therefore, when a semiconductor wafer is divided | segmented and each pellet is formed, there exists a problem that the pellet in which the back surface electrode (wax material) is not formed will be formed.
[0007]
On the other hand, when the heat treatment for forming the Au—Si eutectic layer is performed when the pellets and leads after being divided into individual pellets are thermocompression-bonded, a force for pressing the pellets and the leads works. Therefore, the problem that the AuSb liquefied by the pressing force extends at the interface between the pellet and the lead and is scattered in an island shape can be prevented. However, since the thermocompression bonding must be performed in as short a time as possible in order to prevent changes in the characteristics of the semiconductor elements formed in the pellets, the force for pressing the pellets and the leads is adjusted during the thermocompression bonding process. It has become difficult. Therefore, a desired Au—Si eutectic layer may not be formed, and there is a problem that the adhesive strength between the pellet and the lead is lowered. Further, when the adhesive strength between the pellet and the lead is lowered, there is a problem that the pellet and the lead are peeled off by soldering heat when the package is mounted on the mounting substrate.
[0008]
In addition, as a solder for mounting a package on a mounting board, attention is focused on using a solder containing no lead from the viewpoint of environmental protection. However, since the solder containing no lead is higher than the melting point of the solder containing lead, the heat transmitted to the above-described package is increased. For this reason, there is a problem that the adhesive strength between the pellet and the lead is further lowered, and the pellet and the lead are easily separated.
[0009]
An object of the present invention is to improve the adhesive strength between pellets and leads of a semiconductor device.
[0010]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0011]
[Means for Solving the Problems]
Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
[0012]
That is, the present invention forms a first conductive layer on the back surface of a semiconductor substrate, and forms a eutectic layer of the semiconductor substrate and the first conductive layer at an interface between the semiconductor substrate and the first conductive layer. A step, a step of forming a second conductive layer on the surface of the first conductive layer, a step of dividing the semiconductor substrate into individual semiconductor chips after the formation of the second conductive layer, a back surface of the semiconductor chip, and a semiconductor chip Mounting the semiconductor chip on the semiconductor chip mounting member so that the mounting member comes into contact; and melting the eutectic layer and the second conductive layer after mounting the semiconductor chip on the semiconductor chip mounting member; Forming a first electrode in which a eutectic layer and the second conductive layer are mixed, thereby bonding the semiconductor chip and the semiconductor chip mounting member.
[0013]
The present invention also includes a step of forming a first conductive layer on a back surface of a semiconductor substrate, and a step of forming a compound layer of the semiconductor substrate and the first conductive layer at an interface between the semiconductor substrate and the first conductive layer. A step of forming a second conductive layer on the surface of the first conductive layer, a step of dividing the semiconductor substrate into individual semiconductor chips after the formation of the second conductive layer, a back surface of the semiconductor chip, and a semiconductor chip mounting A step of mounting the semiconductor chip on the semiconductor chip mounting member so as to contact the member; and a step of melting the compound layer and the second conductive layer after mounting the semiconductor chip on the semiconductor chip mounting member, And a step of bonding the semiconductor chip and the semiconductor chip mounting member by forming a first electrode in which the second conductive layer is mixed.
[0014]
According to the present invention, since the eutectic layer or the compound layer can be reliably formed on the entire back surface of the semiconductor substrate, the adhesion strength between the semiconductor substrate and the semiconductor chip mounting member can be increased by the eutectic layer or the compound layer. It becomes possible to improve.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.
[0016]
Next, the manufacturing method of the semiconductor device of this embodiment will be described in the order of steps with reference to FIGS.
[0017]
First, as shown in FIG. 1, a semiconductor substrate 1 on which a diode element (semiconductor element (not shown)) and a surface electrode (not shown) electrically connected to the diode element are prepared. The semiconductor substrate 1 is made of an Si (silicon) wafer into which n-type impurities (for example, As (arsenic)) are introduced and a plurality of semiconductor chip regions for diodes are formed, and the back surface is ground by grinding and wet etching. Is thinned to match the final diode package configuration.
[0018]
Next, as shown in FIG. 2, a conductive film 2 (first conductive layer) is formed on the back surface of the semiconductor substrate 1 by evaporating, for example, an Au film having a thickness of about 0.3 μm. Subsequently, as shown in FIG. 3, the eutectic layer 3 of Au and Si is formed by subjecting the semiconductor substrate 1 to heat treatment at about 370 ° C. to 490 ° C. In the heat treatment, when the temperature is about 370 ° C., the time can be exemplified as about 20 minutes.
[0019]
In the present embodiment, since the conductive film 2 does not contain Sb when the eutectic layer 3 is formed by heat treatment, it is possible to prevent the melting point of the conductive film 2 from lowering than the temperature at the time of heat treatment. it can. That is, the conductive film 2 is liquefied by the heat treatment, and the liquefied conductive film 2 can be prevented from being scattered in islands on the back surface of the semiconductor substrate 1 due to surface tension. Thereby, the eutectic layer 3 can be reliably formed on the entire back surface of the semiconductor substrate 1. By using this eutectic layer 3, it is possible to bond the pellet and the lead in a later step.
[0020]
In the present embodiment, the case where an Au film is deposited as the conductive film 2 and the eutectic layer 3 of Si included in the semiconductor substrate 1 is formed is exemplified. A metal film capable of forming a film (for example, a Pd (palladium) film) is formed, and the metal film and Si included in the semiconductor substrate 1 are reacted to form a silicide film instead of the eutectic layer 3. May be. Even when this silicide film is used, it is possible to bond the pellet and the lead in a later step, as in the case where the eutectic layer 3 is used.
[0021]
Next, as shown in FIG. 4, a conductive film 4 (second conductive layer) is formed by evaporating an AuSb film having a thickness of about 0.3 μm, for example. The Sb included in the conductive film 4 is included in a back electrode formed in a later process, so that the back electrode can take ohmic contact with the semiconductor substrate 1. Further, as the conductive film 4, another metal (for example, Ni (nickel)) film that can be ohmic with the semiconductor substrate 1 may be formed.
[0022]
Subsequently, as shown in FIG. 5, a conductive film 5 (third conductive layer) is formed, for example, by vapor-depositing an Au film having a thickness of about 0.3 μm. Since the Au film is a material that does not easily cause a chemical reaction, the formation of the conductive film 5 can prevent the conductive film 4 from being oxidized. As the conductive film 5, another metal (for example, Ag (silver)) film that prevents oxidation of the conductive film 4 may be formed.
[0023]
Next, after the semiconductor substrate 1 is divided by dicing to form pellets (semiconductor chips) having diode elements as unit elements, a conductive film formed on the back surface of the semiconductor substrate 1 as shown in FIG. The pellet is mounted on the lead 6A so that 5 contacts the lead 6A (semiconductor chip mounting member). The lead 6A is made of, for example, Cu (copper), and an Ag film 7 having a film thickness of about 3 μm to 10 μm is formed in advance on the surface thereof by a plating method.
[0024]
Next, as shown in FIG. 7, the conductive film 2, the eutectic layer 3, the conductive film 4, and the conductive film 5 formed on the back surface of the semiconductor substrate 1 are melted by heat treatment at about 370 ° C. to 490 ° C. As a result, a wax material 8 containing a material (Au—Si—Sb alloy) that has formed each of the conductive film 2, the eutectic layer 3, the conductive film 4, and the conductive film 5 is formed. 1 is bonded to the lead 6A. The heat treatment for forming the wax material 8 can be exemplified by setting the time to about 20 minutes when the temperature is about 370 ° C.
[0025]
Before the brazing material 8 is formed, the eutectic layer 3 made of Au and Si is reliably formed on the entire back surface of the semiconductor substrate 1 as described above with reference to FIG. The bonding strength between the back surface of the semiconductor substrate 1 and the lead 6A can be improved by the brazing material 8 including the layer 3.
[0026]
Further, in the brazing material 8, Sb contained in the conductive film 4 and Si contained in the eutectic layer 3 generate a reaction product due to the heat during the heat treatment, and thus the semiconductor substrate 1 and the brazing material 8. Can take ohmic between. That is, the wax material 8 can be used as a back electrode of a pellet having a diode element as a unit element.
[0027]
Next, as shown in FIG. 8, the surface electrode 9 formed on the semiconductor substrate 1 and the lead 6 </ b> B on the counter electrode side of the lead 6 </ b> A on which the pellet is mounted are wire-bonded using, for example, an Au wire 10.
[0028]
Next, the leads 6A and 6B, the pellets, and the Au wire 10 are sealed with, for example, the resin 11 to form a resin package in which the outer ends of the leads 6A and 6B are exposed to the outside for mounting. Subsequently, as shown in FIG. 9, polarity identification marks 12 such as color bands are formed on the outer peripheral surface of the resin 11 to manufacture the semiconductor device of the present embodiment.
[0029]
The semiconductor device manufactured as described above can be mounted, for example, by connecting the outer ends of the leads 6A and 6B to the mounting board using solder. At this time, in the case where solder containing no Pb (lead) (hereinafter referred to as lead-free solder) is used, the melting point of lead-free solder is higher than the melting point of solder containing Pb. The heat transmitted to the semiconductor device increases. As described above, in the semiconductor device of the present embodiment, the bonding strength between the back surface of the semiconductor substrate 1 and the lead 6A can be improved by the brazing material 8 including the eutectic layer 3, so that the semiconductor can be formed using lead-free solder. It is possible to prevent the semiconductor substrate 1 and the lead 6A from being peeled off by heat when the device is mounted.
[0030]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0031]
For example, the method of forming the brazing material (back electrode) in the above embodiment may be applied to a three-terminal element (transistor) formed by bonding a pellet and a lead.
[0032]
【The invention's effect】
Among the inventions disclosed by the present application, effects obtained by typical ones will be briefly described as follows.
(1) For example, since the eutectic layer of the Au film not containing Sb and Si included in the semiconductor substrate is formed, the eutectic layer can be reliably formed on the entire back surface of the semiconductor substrate.
(2) For example, since the eutectic layer of Au film and Si can be reliably formed on the entire back surface of the semiconductor substrate, the adhesive strength between the semiconductor substrate and the leads can be improved.
[Brief description of the drawings]
FIG. 1 is a fragmentary sectional view in a manufacturing process of a semiconductor device in an embodiment of the invention;
FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1;
3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2; FIG.
4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3; FIG.
5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; FIG.
6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG.
7 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6; FIG.
FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7;
9 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8; FIG.
[Explanation of symbols]
1 Semiconductor substrate 2 Conductive film (first conductive layer)
3 Eutectic layer 4 Conductive film (second conductive layer)
5 Conductive film (3rd conductive layer)
6A Lead (semiconductor chip mounting member)
6B Lead 7 Ag film 8 Wax material (Back electrode)
9 Surface electrode 10 Au wire 11 Resin 12 Polarity identification mark

Claims (3)

（ａ）半導体素子が形成され、シリコンを主成分とする半導体基板を用意する工程、
（ｂ）前記半導体基板の裏面に金からなる第１導電層を形成する工程、
（ｃ）前記半導体基板と前記第１導電層との界面に前記半導体基板および前記第１導電層の共晶層を形成する工程、
（ｄ）前記第１導電層の表面に金を主成分としアンチモンを含む第２導電層を形成する工程、
（ｅ）前記（ｄ）工程後、前記半導体基板を個々の半導体チップに分割する工程、
（ｆ）前記半導体チップの裏面と半導体チップ搭載部材とが接触するように前記半導体チップを前記半導体チップ搭載部材に搭載する工程、
（ｇ）前記（ｆ）工程後、前記共晶層および前記第２導電層を溶融し、前記共晶層および前記第２導電層の混在する第１電極を形成することにより、前記半導体チップと前記半導体チップ搭載部材とを接着する工程、
を含むことを特徴とする半導体装置の製造方法。(A) a step of preparing a semiconductor substrate on which a semiconductor element is formed and having silicon as a main component;
(B) forming a first conductive layer Ru Tona gold on the back surface of the semiconductor substrate,
(C) forming a eutectic layer of the semiconductor substrate and the first conductive layer at an interface between the semiconductor substrate and the first conductive layer;
(D) forming a second conductive layer containing gold as a main component and containing antimony on the surface of the first conductive layer;
(E) After the step (d), dividing the semiconductor substrate into individual semiconductor chips;
(F) mounting the semiconductor chip on the semiconductor chip mounting member such that the back surface of the semiconductor chip and the semiconductor chip mounting member are in contact with each other;
(G) After the step (f), the eutectic layer and the second conductive layer are melted to form a first electrode in which the eutectic layer and the second conductive layer are mixed, thereby forming the semiconductor chip and Bonding the semiconductor chip mounting member;
A method for manufacturing a semiconductor device, comprising: （ａ）半導体素子が形成され、シリコンを主成分とする半導体基板を用意する工程、
（ｂ）前記半導体基板の裏面に金からなる第１導電層を形成する工程、
（ｃ）前記半導体基板と前記第１導電層との界面に前記半導体基板および前記第１導電層の共晶層を形成する工程、
（ｄ）前記第１導電層の表面に第２導電層を形成する工程、
（ｅ）前記第２導電層の表面に第３導電層を形成する工程、
（ｆ）前記（ｅ）工程後、前記半導体基板を個々の半導体チップに分割する工程、
（ｇ）前記半導体チップの裏面と半導体チップ搭載部材とが接触するように前記半導体チップを前記半導体チップ搭載部材に搭載する工程、
（ｈ）前記（ｇ）工程後、前記共晶層、前記第２導電層および前記第３導電層を溶融し、前記共晶層、前記第２導電層および前記第３導電層の混在する第１電極を形成することにより、前記半導体チップと前記半導体チップ搭載部材とを接着する工程、
を含むことを特徴とする半導体装置の製造方法。(A) a step of preparing a semiconductor substrate on which a semiconductor element is formed and having silicon as a main component ;
(B) forming a first conductive layer made of gold on the back surface of the semiconductor substrate;
(C) forming a eutectic layer of the semiconductor substrate and the first conductive layer at an interface between the semiconductor substrate and the first conductive layer;
(D) forming a second conductive layer on the surface of the first conductive layer;
(E) forming a third conductive layer on the surface of the second conductive layer;
(F) After the step (e), the step of dividing the semiconductor substrate into individual semiconductor chips;
(G) mounting the semiconductor chip on the semiconductor chip mounting member such that the back surface of the semiconductor chip and the semiconductor chip mounting member are in contact with each other;
(H) After the step (g), the eutectic layer, the second conductive layer, and the third conductive layer are melted, and the eutectic layer, the second conductive layer, and the third conductive layer are mixed. Bonding the semiconductor chip and the semiconductor chip mounting member by forming one electrode;
A method for manufacturing a semiconductor device, comprising: （ａ）半導体素子が形成され、シリコンを主成分とする半導体基板を用意する工程、
（ｂ）前記半導体基板の裏面に金からなる第１導電層を形成する工程、
（ｃ）前記半導体基板と前記第１導電層との界面に前記半導体基板および前記第１導電層の共晶層を形成する工程、
（ｄ）前記第１導電層の表面に金を主成分としアンチモンを含む第２導電層を形成する工程、
（ｅ）前記第２導電層の表面に金を主成分とする第３導電層を形成する工程、
（ｆ）前記（ｅ）工程後、前記半導体基板を個々の半導体チップに分割する工程、
（ｇ）前記半導体チップの裏面と半導体チップ搭載部材とが接触するように前記半導体チップを前記半導体チップ搭載部材に搭載する工程、
（ｈ）前記（ｇ）工程後、前記共晶層、前記第２導電層および前記第３導電層を溶融し、前記共晶層、前記第２導電層および前記第３導電層の混在する第１電極を形成することにより、前記半導体チップと前記半導体チップ搭載部材とを接着する工程、
を含むことを特徴とする半導体装置の製造方法。(A) a step of preparing a semiconductor substrate on which a semiconductor element is formed and having silicon as a main component;
(B) forming a first conductive layer Ru Tona gold on the back surface of the semiconductor substrate,
(C) forming a eutectic layer of the semiconductor substrate and the first conductive layer at an interface between the semiconductor substrate and the first conductive layer;
(D) forming a second conductive layer containing gold as a main component and containing antimony on the surface of the first conductive layer;
(E) forming a third conductive layer mainly composed of gold on the surface of the second conductive layer;
(F) After the step (e), the step of dividing the semiconductor substrate into individual semiconductor chips;
(G) mounting the semiconductor chip on the semiconductor chip mounting member such that the back surface of the semiconductor chip and the semiconductor chip mounting member are in contact with each other;
(H) After the step (g), the eutectic layer, the second conductive layer, and the third conductive layer are melted, and the eutectic layer, the second conductive layer, and the third conductive layer are mixed. Bonding the semiconductor chip and the semiconductor chip mounting member by forming one electrode;
A method for manufacturing a semiconductor device, comprising:
JP2001026255A 2001-02-02 2001-02-02 Manufacturing method of semiconductor device Expired - Fee Related JP3854467B2 (en)

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