JP2009049144A - Semiconductor substrate and manufacturing method therefor - Google Patents
Semiconductor substrate and manufacturing method therefor Download PDFInfo
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- JP2009049144A JP2009049144A JP2007213092A JP2007213092A JP2009049144A JP 2009049144 A JP2009049144 A JP 2009049144A JP 2007213092 A JP2007213092 A JP 2007213092A JP 2007213092 A JP2007213092 A JP 2007213092A JP 2009049144 A JP2009049144 A JP 2009049144A
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- 239000000758 substrate Substances 0.000 title claims abstract description 97
- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910021334 nickel silicide Inorganic materials 0.000 claims abstract description 21
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 238000010438 heat treatment Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 7
- 238000010030 laminating Methods 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 abstract description 7
- 239000000956 alloy Substances 0.000 abstract description 7
- 239000000853 adhesive Substances 0.000 abstract description 5
- 229910001000 nickel titanium Inorganic materials 0.000 abstract description 5
- 239000000470 constituent Substances 0.000 abstract 1
- 231100000989 no adverse effect Toxicity 0.000 abstract 1
- 239000010936 titanium Substances 0.000 description 18
- 230000000052 comparative effect Effects 0.000 description 9
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- -1 composed of Si Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
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Abstract
Description
本発明は、回路素子を表面に備え、電極をその裏面に備えた半導体基板及びその製造方法に関するものである。 The present invention relates to a semiconductor substrate having a circuit element on its front surface and electrodes on its back surface, and a method for manufacturing the same.
従来、図１に示すように、Ｓｉを主体として構成される半導体基板の表面にMOSFET(Metal Oxide Semiconductor Field Effect Transistor)を設け、その裏面に、Ｔｉ層（厚さ１００ｎｍ〜２００ｎｍ）、Ｎｉ層（１００ｎｍ〜８００ｎｍ）及びＡｕ層（３０ｎｍ〜２００ｎｍ）を積層し、その後、６００〜９００℃程度で加熱して、チタンシリサイド層を形成し、この層を介してオーミックコンタクトを得るようにしていた。
しかしながら、裏面電極を形成する前の工程において、基板の表面に回路素子を備えているために、上記温度域による加熱で回路素子等に変化や破損が生じることが問題となっていた。
Conventionally, as shown in FIG. 1, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is provided on the surface of a semiconductor substrate mainly composed of Si, and a Ti layer (thickness: 100 nm to 200 nm), Ni layer ( 100 nm to 800 nm) and an Au layer (30 nm to 200 nm) are stacked, and then heated at about 600 to 900 ° C. to form a titanium silicide layer, and an ohmic contact is obtained through this layer.
However, since the circuit element is provided on the surface of the substrate in the step before forming the back electrode, there is a problem that the circuit element or the like is changed or damaged by heating in the above temperature range.
また、近年、半導体基板自体の抵抗を低減するために、基板の薄型化が進められているが、機械的強度が低下するという問題があった。
このため、通常、WSS(Wafer Support System)等の基板にガラスや樹脂からなる支持部材を設けて搬送するようにしているが、このWSSの場合半導体基板と支持部材との間に接着剤を使用するが、この接着剤には耐熱温度の制限があるため、上記のような温度にて加熱することが困難であるという問題があった。
In recent years, in order to reduce the resistance of the semiconductor substrate itself, the thickness of the substrate has been reduced, but there has been a problem that the mechanical strength is lowered.
For this reason, normally, a support member made of glass or resin is provided on a substrate such as WSS (Wafer Support System), but in the case of this WSS, an adhesive is used between the semiconductor substrate and the support member. However, this adhesive has a problem that it is difficult to heat at such a temperature because of the limitation of the heat-resistant temperature.
この種の電極として、特許文献１において、ニッケルシリサイド層（厚さ１０ｎｍ〜４００ｎｍ）、Ｔｉ層（厚さ５０ｎｍ〜２００ｎｍ）、Ｎｉ層（厚さ１００ｎｍ〜８００ｎｍ）、ＡｕＧｅ合金層（厚さ５００ｎｍ〜１５００ｎｍ）、Ａｕ層（厚さ５０ｎｍ〜２００ｎｍ）を積層してなる多層電極が開示されている。前記ニッケルシリサイド層は、Ｓｉ基板を３００℃〜４５０℃で加熱しながらＮｉ層を成膜することにより形成されるものである。
しかしながら、前記ニッケルシリサイド層には、温度によって、高い応力が発生することがあり剥がれやすく、しかも、Ｎｉ層に積層されるＴｉ層が、高抵抗のＮｉＴｉ合金となるという問題があった。
As an electrode of this type, in Patent Document 1, a nickel silicide layer (thickness 10 nm to 400 nm), a Ti layer (thickness 50 nm to 200 nm), a Ni layer (thickness 100 nm to 800 nm), an AuGe alloy layer (thickness 500 nm to (1500 nm) and a multilayer electrode formed by stacking Au layers (thickness: 50 nm to 200 nm). The nickel silicide layer is formed by forming a Ni layer while heating the Si substrate at 300 ° C. to 450 ° C.
However, the nickel silicide layer has a problem that high stress may be generated depending on the temperature and is easily peeled off, and the Ti layer laminated on the Ni layer becomes a high resistance NiTi alloy.
そこで、本発明は、ニッケルシリサイド層が剥離しにくく、ＮｉＴｉ合金層を有しない半導体基板を提供することを目的とする。また、半導体基板の表面の回路素子やＷＳＳの際に使用する接着剤に悪影響を与えることない半導体基板の製造方法を提供することを目的とする。 Therefore, an object of the present invention is to provide a semiconductor substrate in which the nickel silicide layer is difficult to peel off and does not have a NiTi alloy layer. It is another object of the present invention to provide a method for manufacturing a semiconductor substrate that does not adversely affect circuit elements on the surface of the semiconductor substrate and an adhesive used in WSS.
上記課題を解決すべく、本発明者等は鋭意検討の結果、以下の解決手段を見いだした。
即ち、本発明の半導体基板は、請求項１に記載の通り、半導体基板の表面に回路素子を備え、裏面に積層構造の電極を備えた半導体基板であって、前記半導体基板としてＳｉを主体とする基板を使用し、前記基板の裏面側の何れかの層に、少なくともＮｉ層を積層した後に、１００℃以上３００℃以下で加熱処理することにより前記基板上にニッケルシリサイド層を形成したことを特徴とする。
また、請求項２に記載の本発明は、請求項１に記載の半導体基板において、前記基板の裏面に、第１のＮｉ層、Ｔｉ層、第２のＮｉ層及びＡｕ層を順に積層したことを特徴とする。
また、請求項３に記載の本発明は、請求項２に記載の半導体基板において、前記第１のＮｉ層の厚さを１０ｎｍ〜５０ｎｍ、Ｔｉ層を厚さ１００ｎｍ〜３００ｎｍ、前記第２のＮｉ層の厚さを１００ｎｍ〜８００ｎｍとしたことを特徴とする。
また、請求項４に記載の本発明は、請求項１に記載の半導体基板において、前記基板の裏面に、厚さ１０ｎｍ〜１００ｎｍのＴｉ層を積層した後、Ｎｉ層を積層したことを特徴とする。
また、本発明の半導体基板の製造方法は、請求項５に記載の通り、半導体基板の表面に回路素子を備え、裏面に積層構造の電極を備えた半導体基板の製造方法であって、前記半導体基板としてＳｉを主体とする基板を使用し、前記基板の裏面側に、少なくともＮｉ層を積層した後に、１００℃以上３００℃以下で加熱処理することにより前記基板上にニッケルシリサイド層を形成することを特徴とする。
また、請求項６に記載の本発明は、請求項５に記載の半導体基板の製造方法において、前記基板の裏面に、第１のＮｉ層、Ｔｉ層、第２のＮｉ層及びＡｕ層を順に積層することを特徴とする。
また、請求項７に記載の本発明は、請求項６に記載の半導体基板の製造方法において、前記第１のＮｉ層の厚さを１０ｎｍ〜５０ｎｍ、Ｔｉ層を厚さ１０ｎｍ〜１００ｎｍ、前記第２のＮｉ層の厚さを１００ｎｍ〜８００ｎｍとすることを特徴とする。
また、請求項８に記載の本発明は、請求項５に記載の半導体基板の製造方法において、前記基板の裏面に、Ｔｉ層を積層した後、Ｎｉ層を積層することを特徴とする。
In order to solve the above-mentioned problems, the present inventors have intensively studied and found the following solution.
That is, the semiconductor substrate according to the present invention is a semiconductor substrate comprising a circuit element on the front surface of the semiconductor substrate and an electrode having a laminated structure on the back surface, as defined in claim 1, wherein the semiconductor substrate is mainly composed of Si. A nickel silicide layer is formed on the substrate by laminating at least a Ni layer on any layer on the back side of the substrate and then performing a heat treatment at 100 ° C. or more and 300 ° C. or less. Features.
According to a second aspect of the present invention, in the semiconductor substrate according to the first aspect, a first Ni layer, a Ti layer, a second Ni layer, and an Au layer are sequentially stacked on the back surface of the substrate. It is characterized by.
According to a third aspect of the present invention, in the semiconductor substrate according to the second aspect, the first Ni layer has a thickness of 10 nm to 50 nm, the Ti layer has a thickness of 100 nm to 300 nm, and the second Ni layer The thickness of the layer is 100 nm to 800 nm.
According to a fourth aspect of the present invention, in the semiconductor substrate according to the first aspect, a Ti layer having a thickness of 10 nm to 100 nm is laminated on the back surface of the substrate, and then a Ni layer is laminated. To do.
According to a fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor substrate, comprising: a semiconductor substrate including a circuit element on a front surface of the semiconductor substrate; and a stacked structure electrode on a back surface. A substrate mainly composed of Si is used as a substrate, and at least a Ni layer is laminated on the back side of the substrate, and then a nickel silicide layer is formed on the substrate by heat treatment at 100 ° C. or more and 300 ° C. or less. It is characterized by.
The present invention according to claim 6 is the method for manufacturing a semiconductor substrate according to claim 5, wherein the first Ni layer, the Ti layer, the second Ni layer, and the Au layer are sequentially formed on the back surface of the substrate. It is characterized by being laminated.
According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor substrate according to the sixth aspect, the first Ni layer has a thickness of 10 nm to 50 nm, the Ti layer has a thickness of 10 nm to 100 nm, and the first The thickness of the Ni layer 2 is 100 nm to 800 nm.
The present invention according to claim 8 is characterized in that, in the method for manufacturing a semiconductor substrate according to claim 5, after a Ti layer is laminated on the back surface of the substrate, a Ni layer is laminated.
本発明の半導体基板は、ニッケルシリサイド層の剥離がなく、高抵抗のＮｉＴｉ合金層を備えるものではないので、高電流の場合に熱の発生を防ぐことができる。
また、本発明の半導体基板の製造方法によれば、低温においてニッケルシリサイド層を形成することができる。その結果、基板の薄型化による搬送の際の補強支持部材に接着剤を使用して接着した場合であっても、高温のために接着剤が剥離することがない。また、高抵抗のＮｉＴｉ合金層が形成することがない。
Since the semiconductor substrate of the present invention does not peel off the nickel silicide layer and does not include a high-resistance NiTi alloy layer, heat generation can be prevented in the case of a high current.
Further, according to the method for manufacturing a semiconductor substrate of the present invention, a nickel silicide layer can be formed at a low temperature. As a result, the adhesive does not peel off due to the high temperature even when the reinforcing support member is bonded to the reinforcing support member during conveyance due to the thinning of the substrate. Moreover, a high resistance NiTi alloy layer is not formed.
上述の通り、本発明は、Ｓｉを主体とする半導体基板の表面に回路素子を備え、その裏面に多層電極を形成するものである。
前記多層電極は、Ｓｉを主体とする基板の裏面側に少なくともＮｉ層を積層した後に、１００℃以上３００℃以下で加熱処理することにより基板上にニッケルシリサイド層を形成したものである。これにより、ニッケルシリサイド層の基板とは反対側にＮｉ層を残すことができ、その上に金属層を積層する際に密着力を高めることができる。また、本発明のＮｉ層を残存させたニッケルシリサイド層に対して、同じ膜厚でニッケルシリサイド層を形成した場合と比べると抵抗値を下げることができる。前記温度域とした理由は、１００℃未満であると、ニッケルシリサイド層が形成されず、３００℃を超えると、Ｎｉ層上に積層される金属層と反応して高い抵抗値の合金層が形成されるとともに、Ｎｉ層の応力が大きくなり、膜剥がれが発生するからである。
具体的には、前記Ｓｉ基板の裏面側の多層電極の構造の例を挙げると、例えば、第１のＮｉ層、Ｔｉ層、第２のＮｉ層及びＡｕ層の順に積層した構造とすることができる。また、各層の膜厚として、前記第１のＮｉ層の厚さを１０ｎｍ〜５０ｎｍ、Ｔｉ層を厚さ１００ｎｍ〜２００ｎｍ、前記第２のＮｉ層の厚さを１００ｎｍ〜８００ｎｍとすることができる。
また、前記Ｓｉを主体とする半導体基板の裏面側に、第１層として厚さ１０ｎｍ〜１００ｎｍのＴｉ層を積層した後にＮｉ層を積層してもよい。Ｎｉ層がＴｉ層を突き抜けてニッケルシリサイド層を形成してオーミックコンタクトが得られるからである。尚、Ｔｉ層の厚さが１０ｎｍ未満であるとバリアメタルとしての効果が低くなり、１００ｎｍを超えるとニッケルシリサイド層が形成されないためである。
尚、上記した各層は、スパッタ又は蒸着により形成することができるが、スパッタの場合、蒸着にくらべ緻密な膜が形成されやすく、その為に高い応力が生じるため、密着力を高めることが可能な本発明は、スパッタにより各層を形成する場合により有効である。
As described above, in the present invention, a circuit element is provided on the surface of a semiconductor substrate mainly composed of Si, and a multilayer electrode is formed on the back surface thereof.
The multilayer electrode is obtained by forming a nickel silicide layer on a substrate by laminating at least a Ni layer on the back side of a substrate mainly composed of Si and then performing heat treatment at 100 ° C. or more and 300 ° C. or less. As a result, the Ni layer can be left on the opposite side of the nickel silicide layer from the substrate, and the adhesion can be increased when the metal layer is laminated thereon. Also, the resistance value can be lowered compared to the case where the nickel silicide layer having the same thickness is formed on the nickel silicide layer in which the Ni layer of the present invention remains. The reason for the temperature range is that when the temperature is lower than 100 ° C., the nickel silicide layer is not formed, and when the temperature exceeds 300 ° C., an alloy layer having a high resistance value is formed by reacting with the metal layer laminated on the Ni layer. This is because the stress of the Ni layer increases and film peeling occurs.
Specifically, an example of the structure of the multilayer electrode on the back side of the Si substrate is, for example, a structure in which a first Ni layer, a Ti layer, a second Ni layer, and an Au layer are stacked in this order. it can. In addition, the thickness of each layer may be 10 nm to 50 nm for the first Ni layer, 100 nm to 200 nm for the Ti layer, and 100 nm to 800 nm for the second Ni layer.
Further, a Ni layer may be stacked after a Ti layer having a thickness of 10 nm to 100 nm is stacked as the first layer on the back surface side of the semiconductor substrate mainly composed of Si. This is because the Ni layer penetrates the Ti layer to form a nickel silicide layer and an ohmic contact is obtained. If the thickness of the Ti layer is less than 10 nm, the effect as a barrier metal is lowered, and if it exceeds 100 nm, the nickel silicide layer is not formed.
Each of the above-mentioned layers can be formed by sputtering or vapor deposition, but in the case of sputtering, a dense film is easily formed as compared with vapor deposition, and thus high stress is generated, so that the adhesion can be increased. The present invention is more effective when each layer is formed by sputtering.
次に、本発明の実施例について、図面及び比較例を参照して説明する。
本実施例において使用する装置の概略構成は、図３に示すように、Ｓｉを主体とし、その表面に電子回路を形成した半導体基板を搬送するための移載機２と、半導体基板の裏面に成膜するための搬送室３とを備えている。搬送室３内には、半導体基板を載置するためのロボットアーム等が配置され、搬送室３の半導体基板を、ＩＣＰプラズマ等により半導体基板の裏面の自然酸化膜を除去するためのエッチングソース５、Ｔｉ及びＡｕを成膜するためのマルチカソード６、Ｎｉを成膜するためのシングルカソード７、半導体基板を加熱するためのランプを備えたロード・アンロード室８に搬送できるようになっている。
Next, examples of the present invention will be described with reference to the drawings and comparative examples.
As shown in FIG. 3, the schematic configuration of the apparatus used in the present embodiment is a transfer machine 2 for transporting a semiconductor substrate mainly composed of Si and having an electronic circuit formed on the surface thereof, and a back surface of the semiconductor substrate. And a transfer chamber 3 for film formation. A robot arm or the like for placing a semiconductor substrate is disposed in the transfer chamber 3, and an etching source 5 for removing the natural oxide film on the back surface of the semiconductor substrate from the semiconductor substrate in the transfer chamber 3 by ICP plasma or the like. , A multi-cathode 6 for depositing Ti and Au, a single cathode 7 for depositing Ni, and a load / unload chamber 8 equipped with a lamp for heating the semiconductor substrate. .
（実施例１）
前記装置において、直径１５０ｍｍ、厚さ６２５μｍの円形状の半導体基板を移載機２から搬送室３内に搬送し、エッチングソース５により半導体基板の裏面についた自然酸化膜を除去する。次に、シングルカソード７により、第１のＮｉ層を１０ｎｍ成膜し、マルチカソード６により、Ｔｉ層を２００ｎｍ成膜し、シングルカソード７により第２のＮｉ層を４００ｎｍ成膜し、マルチカソード６により、Ａｕ層を３０ｎｍ成膜して、図４に示す積層構造体とした。そして、ロード・アンロード室８において、半導体基板を２００℃で２０分間加熱して、半導体基板上にニッケルシリサイド層を形成した。
(Example 1)
In the apparatus, a circular semiconductor substrate having a diameter of 150 mm and a thickness of 625 μm is transferred from the transfer machine 2 into the transfer chamber 3, and the natural oxide film on the back surface of the semiconductor substrate is removed by the etching source 5. Next, a 10 nm first Ni layer is formed by the single cathode 7, a 200 nm Ti layer is formed by the multi-cathode 6, a 400 nm second Ni layer is formed by the single cathode 7, and the multi-cathode 6 is formed. As a result, an Au layer was formed to a thickness of 30 nm to obtain a laminated structure shown in FIG. In the load / unload chamber 8, the semiconductor substrate was heated at 200 ° C. for 20 minutes to form a nickel silicide layer on the semiconductor substrate.
（実施例２）
実施例１で使用した装置により、直径１５０ｍｍ、厚さ６２５ｍｍの円形状の半導体基板を移載機２から搬送室３内に搬送し、エッチングソース５により半導体基板の裏面についた自然酸化膜を除去する。次に、マルチカソード６により、Ｔｉ層を１０ｎｍ成膜し、シングルカソード７により第２のＮｉ層を４００ｎｍ成膜し、マルチカソード６により、Ａｕ層を３０ｎｍ成膜した。そして、ロード・アンロード室８において、半導体基板を３００℃で２０分間加熱して、半導体基板上にニッケルシリサイド層を形成した。
(Example 2)
With the apparatus used in Example 1, a circular semiconductor substrate having a diameter of 150 mm and a thickness of 625 mm is transferred from the transfer machine 2 into the transfer chamber 3, and the natural oxide film on the back surface of the semiconductor substrate is removed by the etching source 5. To do. Next, a Ti layer was formed to a thickness of 10 nm using the multi-cathode 6, a second Ni layer was formed to a thickness of 400 nm using the single cathode 7, and an Au layer was formed to a thickness of 30 nm using the multi-cathode 6. In the load / unload chamber 8, the semiconductor substrate was heated at 300 ° C. for 20 minutes to form a nickel silicide layer on the semiconductor substrate.
（比較例１）
加熱処理をしなかったこと以外は実施例１と同様にして半導体基板を作成した。
(Comparative Example 1)
A semiconductor substrate was prepared in the same manner as in Example 1 except that the heat treatment was not performed.
（比較例２）
４５０℃で加熱処理した以外は実施例１と同様にして半導体基板を作成した。
(Comparative Example 2)
A semiconductor substrate was prepared in the same manner as in Example 1 except that the heat treatment was performed at 450 ° C.
上記各実施例及び各比較例の半導体基板の裏面電極に対して１ｍｍ角となるようにカッターナイフにより切れ目を入れ、粘着テープを使用して剥離試験を行ったところ、４５０℃で加熱を行った比較例２の半導体基板の多層電極のみ剥離を確認した。 A cut was made with a cutter knife so as to be 1 mm square with respect to the back electrode of the semiconductor substrate of each of the above Examples and Comparative Examples, and a peel test was performed using an adhesive tape. Only the multilayer electrode of the semiconductor substrate of Comparative Example 2 was confirmed to be peeled.
次に、各実施例及び比較例１について、積層された電極方向の電圧−電流特性を測定した。その結果を、図５（実施例１）、図６（実施例２）及び図７（比較例１）に示す。
図５〜図７から、実施例１及び２では電圧−電流の直線性があり、即ち、半導体基板とオーミックコンタクトしており、コンタクト抵抗についても、実施例１では１５．２Ω／ｃｍ２、実施例２では０．１８６Ω／ｃｍ２と低い値が得られた。これに対して、比較例１では、実施例１及び２と比べて、電流値が低く、直線性が得られておらず、半導体基板とオーミックコンタクトしていないと考えられる。
Next, for each example and comparative example 1, voltage-current characteristics in the direction of the stacked electrodes were measured. The results are shown in FIG. 5 (Example 1), FIG. 6 (Example 2) and FIG. 7 (Comparative Example 1).
From FIG. 5 to FIG. 7, the first and second embodiments have voltage-current linearity, that is, ohmic contact with the semiconductor substrate, and the contact resistance is 15.2 Ω / cm 2 in the first embodiment. In Example 2, a low value of 0.186 Ω / cm 2 was obtained. On the other hand, in Comparative Example 1, the current value is lower than that of Examples 1 and 2, linearity is not obtained, and it is considered that the semiconductor substrate is not in ohmic contact.
２ 移載機
３ 搬送室
５ エッチングソース
６ マルチカソード
７ シングルカソード
８ ロード・アンロード室
2 Transfer machine 3 Transfer chamber 5 Etching source 6 Multi-cathode 7 Single cathode 8 Load / unload chamber
Claims (8)
6. The method of manufacturing a semiconductor substrate according to claim 5, wherein a Ni layer is laminated after a Ti layer is laminated on the back surface of the substrate.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2011138976A (en) * | 2009-12-29 | 2011-07-14 | Renesas Electronics Corp | Method of manufacturing semiconductor device |
| DE112011103782T5 (en) | 2010-11-16 | 2013-08-22 | Mitsubishi Electric Corporation | Semiconductor element, semiconductor device and method of manufacturing a semiconductor element |
| JP2014236043A (en) * | 2013-05-31 | 2014-12-15 | 三菱電機株式会社 | Semiconductor device and manufacturing method of the same |
| WO2017032771A1 (en) * | 2015-08-25 | 2017-03-02 | Osram Opto Semiconductors Gmbh | Device and method for producing a device |
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| JP2003068674A (en) * | 2001-08-30 | 2003-03-07 | Hitachi Ltd | Semiconductor device and production method therefor |
| JP2006237374A (en) * | 2005-02-25 | 2006-09-07 | Toshiba Corp | Semiconductor integrated circuit device and manufacturing method thereof |
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| JPH08255769A (en) * | 1995-03-17 | 1996-10-01 | Hitachi Ltd | Method of manufacturing semiconductor device |
| JP2003068674A (en) * | 2001-08-30 | 2003-03-07 | Hitachi Ltd | Semiconductor device and production method therefor |
| JP2006237374A (en) * | 2005-02-25 | 2006-09-07 | Toshiba Corp | Semiconductor integrated circuit device and manufacturing method thereof |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011138976A (en) * | 2009-12-29 | 2011-07-14 | Renesas Electronics Corp | Method of manufacturing semiconductor device |
| DE112011103782T5 (en) | 2010-11-16 | 2013-08-22 | Mitsubishi Electric Corporation | Semiconductor element, semiconductor device and method of manufacturing a semiconductor element |
| US9553063B2 (en) | 2010-11-16 | 2017-01-24 | Mitsubishi Electric Corporation | Semiconductor element, semiconductor device and method for manufacturing semiconductor element |
| DE112011103782B4 (en) | 2010-11-16 | 2019-05-09 | Mitsubishi Electric Corporation | Semiconductor element, semiconductor device and method of manufacturing a semiconductor element |
| JP2014236043A (en) * | 2013-05-31 | 2014-12-15 | 三菱電機株式会社 | Semiconductor device and manufacturing method of the same |
| WO2017032771A1 (en) * | 2015-08-25 | 2017-03-02 | Osram Opto Semiconductors Gmbh | Device and method for producing a device |
| CN108352373A (en) * | 2015-08-25 | 2018-07-31 | 奥斯兰姆奥普托半导体有限责任公司 | Device and method for manufacturing device |
| US10204880B2 (en) | 2015-08-25 | 2019-02-12 | Osram Opto Semiconductors Gmbh | Device and method for producing a device |
| CN108352373B (en) * | 2015-08-25 | 2022-04-08 | 奥斯兰姆奥普托半导体有限责任公司 | Device and method for manufacturing a device |
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