JP2011138976A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problem: although a single-chamber and multi-film-deposition-site type device is widely used for a recent multilayer metal sputtering film deposition process in place of a conventional multi-chamber type device, such a single-chamber and multi-film-deposition-site type sputtering film deposition device greatly reduces throughput since a wafer to be processed needs to be transferred to a different film deposition site to form a film when a magnetic metal film and a nonmagnetic metal film are deposited laminated. <P>SOLUTION: A method of manufacturing a semiconductor device which uses the single-chamber and multi-film-deposition-site type sputtering film deposition device is characterized by changing over and using both magnetic and nonmagnetic targets at least at one film deposition site to form both the magnetic and nonmagnetic films. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a technique effective when applied to a sputtering film forming technique in a method for manufacturing a semiconductor device (or a semiconductor integrated circuit device).

  International Publication No. 2001/44534 pamphlet (Patent Document 1) discloses a magnetron method in which a single wafer is moved in the same chamber to switch a magnetic and non-magnetic target to form a plurality of films by sputtering. A sputtering deposition technique is disclosed.

  In Japanese Unexamined Patent Publication No. 2009-135559 (Patent Document 2), a single wafer is fixedly placed in the same chamber, and a plurality of films are switched by switching magnetic and nonmagnetic targets installed in an oblique direction. A magnetron type sputtering film forming technique for forming a film by sputtering is disclosed.

International Publication No. 2001/44534 Pamphlet JP 2009-135559 A

  In recent multi-layer metal sputtering deposition process, single chamber & multi deposition site type equipment (however, load lock chamber is a separate room) is widely used instead of conventional multi-chamber type equipment. It has become so. However, according to a study by the inventors of the present application, such a single chamber & multi film formation site type sputtering film formation apparatus has a magnetic metal film (where “magnetic” is ferromagnetic including ferrimagnetism) and non-magnetic. In the case of laminating and forming magnetic metal films (non-ferromagnetic), it has become clear that it is necessary to transfer the wafer to be processed to another film formation site for film formation, which greatly reduces the throughput.

  The present invention has been made to solve these problems.

  An object of the present invention is to provide a manufacturing process of a semiconductor device with high productivity.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, according to one aspect of the present invention, in a method of manufacturing a semiconductor device using a single chamber & multi-deposition site type multilayer sputtering deposition apparatus, at least one deposition site is switched between a magnetic and a non-magnetic target. Used to form both magnetic and non-magnetic films.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in a method for manufacturing a semiconductor device using a single chamber & multi film formation site type multilayer sputtering film formation apparatus, at least one film formation site is used by switching both magnetic and nonmagnetic targets, and magnetic and nonmagnetic. Since both films are deposited, the efficiency of the multilayer deposition process can be greatly improved.

It is a top view of the wafer back surface multilayer metal film-forming apparatus used for the manufacturing method of the semiconductor device of one embodiment of this application. 1 is a top view of a wafer back surface multilayer metal film forming apparatus used in a method for manufacturing a semiconductor device according to an embodiment of the present application (the target switching mechanism in FIG. 1 is made transparent so that the lower part can be easily seen). FIG. 3 is a perspective view of an internal transfer robot, each wafer stage, a wafer on a stage, and a wafer susceptor for explaining how a wafer moves in the wafer backside multilayer metal film forming apparatus shown in FIGS. 1 and 2. FIG. 4 is a top view of the wafer susceptor of FIG. 3. FIG. 5 is a cross-sectional view of the wafer susceptor corresponding to the X-X ′ cross section of FIG. 4 (when held by the internal transfer robot). FIG. 3 is a front sectional structural view of cooling wafer stages 63b and 63c of the wafer back surface multilayer metal film forming apparatus shown in FIGS. 1 and 2; FIG. 3 is a front sectional structural view of a lamp heating wafer stage 63a of the wafer back surface multilayer metal film forming apparatus shown in FIGS. 1 and 2; FIG. 3 is a front sectional structural view (during a degassing process) of a load lock chamber 61 of the wafer back surface multilayer metal film forming apparatus shown in FIGS. 1 and 2. FIG. 3 is a schematic cross-sectional view when the wafer back surface multilayer metal film forming apparatus shown in FIGS. FIG. 10 is an enlarged cross-sectional view of the periphery of a multi-target film forming region 62b in the wafer back surface multilayer metal film forming apparatus of FIG. It is a lower surface enlarged view of the magnetron magnet group shown to FIG. 9 and FIG. It is an expanded sectional view of the target switching mechanism 59 shown in FIG. 9 and FIG. It is a process block flow diagram of a wafer back surface multilayer metal layer film forming process in the manufacturing method of the semiconductor device of one embodiment of the present application. It is a device top view which shows an example of power MOSFET manufactured by the manufacturing method of the semiconductor device of one embodiment of this application. It is a device cross section flow figure (resist pattern formation process for source contact groove formation) of a trench gate cell part in a manufacturing method of a semiconductor device of one embodiment of this application. It is a device section flow figure (source contact groove formation process) of a trench gate cell part in a manufacturing method of a semiconductor device of one embodiment of this application. It is a device cross section flow figure (resist pattern removal process for source contact groove formation) of a trench gate cell part in a manufacturing method of a semiconductor device of one embodiment of this application. It is a device cross section flow figure (source contact groove extension process) of a trench gate cell part in a manufacturing method of a semiconductor device of one embodiment of this application. It is a device top view (p + body contact region introduction process) of a trench gate cell part in a manufacturing method of a semiconductor device of one embodiment of this application. FIG. 20 is a device cross-sectional flow diagram (p + body contact region introduction step) of a trench gate cell portion (corresponding to the X-X ′ cross section of FIG. 19) in the method for manufacturing a semiconductor device of one embodiment of the present application; It is a device section flow figure (barrier metal film formation process) of a trench gate cell part in a manufacturing method of a semiconductor device of one embodiment of this application. FIG. 5 is a device cross-sectional flow diagram (aluminum-based metal film forming step) of a trench gate cell portion in the method for manufacturing a semiconductor device of one embodiment of the present application. It is a device cross section flow figure (back grinding process) of a trench gate cell part in a manufacturing method of a semiconductor device of one embodiment of this application. It is a device section flow figure (back surface multilayer metal film formation process) of a trench gate cell part in a manufacturing method of a semiconductor device of one embodiment of this application.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. A method of manufacturing a semiconductor device using the following wafer processing apparatus, wherein the wafer processing apparatus includes:
(X1) a load lock room that is spatially independent from the outside;
(X2) Sputtering deposition processing chamber that is spatially independent of the outside and the load lock chamber and is spatially integrated;
(X3) first and second sputtering film forming regions provided in the sputtering film forming chamber;
(X4) a target switching mechanism in the first sputtering film forming region;
(X5) a magnetic target and a non-magnetic target held by the target switching mechanism,
Here, the manufacturing method of the semiconductor device includes the following steps:
(A) introducing a wafer into the load lock chamber and performing a vacuum treatment;
(B) After the step (a), in the first sputtering film forming region, the first sputtering film forming process using the magnetic target and the first sputtering film forming process using the non-magnetic target are performed on the wafer. Performing the sputtering film forming process of 2;
(C) A step of performing a third sputtering film forming process on the wafer in the second sputtering film forming region after the step (a);
(D) A step of repeatedly and continuously executing the processes including the steps (a), (b) and (c) on another wafer as soon as the load lock chamber is empty.

  2. In the method of manufacturing a semiconductor device according to the item 1, the evacuation system is common to the first sputtering film formation region and the second sputtering film formation region.

  3. In the method for manufacturing a semiconductor device according to the item 1 or 2, a set of magnetron magnet groups is installed in the first sputtering film forming region.

  4). 4. In the method for manufacturing a semiconductor device according to any one of items 1 to 3, the vacuum process in the step (a) is a degassing process.

  5. In the method of manufacturing a semiconductor device according to any one of 1 to 4, the switching of the target in the first sputtering film formation region is performed by moving the magnetic target and the nonmagnetic target.

  6). 6. The method of manufacturing a semiconductor device according to any one of 1 to 5, wherein the first sputtering film forming process, the second sputtering film forming process, and the third sputtering film forming process are performed on the wafer and the other. Is performed on the backside of the wafer.

  7). 7. In the method of manufacturing a semiconductor device according to any one of 1 to 6, the thickness of the wafer and the other wafer is less than 300 micrometers.

8). 8. The method of manufacturing a semiconductor device according to any one of 1 to 7, wherein the wafer processing apparatus further includes:
(X6) a first wafer stage provided so as to form the bottom of the load lock chamber;
(X7) a second wafer stage provided in the first sputtering film formation region;
(X8) A third wafer stage provided in the second sputtering film forming region.

9. 9. The method for manufacturing a semiconductor device according to any one of 1 to 8, wherein the wafer processing apparatus further includes:
(X9) a set of first film adhesion preventing shields provided in the first sputtering film formation region;
(X10) A pair of second film adhesion preventing shields provided in the second sputtering film forming region.

  10. In the method for manufacturing a semiconductor device according to the item 8 or 9, the first wafer stage, the second wafer stage, and the third wafer stage are substantially on the same circumference in plan view.

  11. 11. In the method of manufacturing a semiconductor device as described above in any one of 1 to 10, the processing on the wafer and the other wafer in the wafer processing apparatus is performed on each wafer of the wafer and the other wafer and a ring-shaped wafer, respectively. It is executed with the susceptor in close proximity.

  12 12. In the method of manufacturing a semiconductor device according to any one of 1 to 11, the first sputtering film formation process is a titanium film sputtering film formation process, and the second sputtering film formation process is a first nickel film. The third sputtering film forming process is a gold film sputtering film forming process.

  13. In the method of manufacturing a semiconductor device according to any one of 1 to 12, the diameter of the magnetic target is smaller than the diameter of the nonmagnetic target.

14 14. The method of manufacturing a semiconductor device according to any one of 1 to 13, wherein the wafer processing apparatus further includes:
(X11) a first backing plate provided on the back surface of the magnetic target;
(X12) a second backing plate provided on the back surface of the nonmagnetic target;
(X13) A spacer plate provided between the nonmagnetic target and the second backing plate.

15. 15. The method of manufacturing a semiconductor device according to any one of 1 to 14, wherein the evacuation system includes:
(Y1) dry pump;
(Y2) A cryopump.

16. 16. The method for manufacturing a semiconductor device according to the item 15, wherein the load pump chamber evacuation system includes
(Y3) the dry pump;
(Y4) Molecular pump.

17. 13. The method for manufacturing a semiconductor device according to any one of 9 to 12, wherein the wafer processing apparatus further includes:
(X14) a third sputtering film forming region provided in the sputtering film forming chamber;
(X15) a fourth wafer stage provided in the third sputtering film forming region;
(X16) A set of third film adhesion preventing shields provided in the third sputtering film forming region.

  18. In the method for manufacturing a semiconductor device according to the item 17, the third sputtering film formation region is for sputtering film formation of the second nickel film.

  19. In the method for manufacturing a semiconductor device according to the item 17 or 18, the first wafer stage, the second wafer stage, the third wafer stage, and the fourth wafer stage are substantially in a plane. On the same circumference.

  20. 20. In the method for manufacturing a semiconductor device according to any one of 1 to 19, the step (b) is performed before the step (c).

  21. 21. In the method for manufacturing a semiconductor device according to any one of 1 to 20, the semiconductor device includes a power MOSFET, an IGBT, or an LDMOSFET.

  22. 21. In the method for manufacturing a semiconductor device according to any one of 1 to 20, the semiconductor device includes a power MOSFET.

  23. 21. In the method for manufacturing a semiconductor device according to any one of 1 to 20, the semiconductor device includes an IGBT.

  24. 21. In the method for manufacturing a semiconductor device according to any one of 1 to 20, the semiconductor device includes an LDMOSFET.

  25. 25. In the method of manufacturing a semiconductor device according to any one of 1 to 24, the second sputtering film formation process is performed before the first sputtering film formation process.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Furthermore, in the present application, the term “semiconductor device” mainly refers to a single device such as various transistors (active elements), and mainly a resistor, a capacitor, etc. on a semiconductor chip or the like (for example, a single crystal silicon substrate). It is a collection. In addition, even if it is called a single unit, there are actually a plurality of small elements integrated. Here, as a typical example of various transistors, a MISFET (Metal Insulator Semiconductor Transistor which can be a MISFET represented by a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or a transistor, an IGB transistor which can be an IGBT transistor, an IBB transistor, an IGB transistor, an IBB transistor, an IGB transistor, an IGB transistor, an IB transistor, an IGB transistor, an IGBT, and an IGBT. . Also, “MOS” does not limit the insulating film to oxide.

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, “silicon oxide film”, “silicon oxide insulating film”, etc. are not only relatively pure undoped silicon oxide (FS), but also FSG (Fluorosilicate Glass), TEOS-based silicon oxide ( Thermal oxide films such as TEOS-based silicon oxide), SiOC (Silicon Oxicarbide) or Carbon-doped Silicon oxide or OSG (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass), CVD Oxide film, SOG (Spin ON Glass), nano-clustering silica (Nano-Clustering Silica: NSC), etc., coating system silicon oxide, and silica-based low-k insulating film (porous insulation) with holes introduced in the same material Needless to say, a film) and a composite film with other silicon-based insulating films including these as main constituent elements are included.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like. Here, “silicon nitride” includes both SiN and SiNH unless otherwise specified. Similarly, “SiCN” includes both SiCN and SiCNH, unless otherwise specified.

  Note that SiC has similar properties to SiN, but SiON is often rather classified as a silicon oxide insulating film.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor device (same as a semiconductor integrated circuit device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate, and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

  6). In the present application, “continuously executing” the processing for wafers means that, for example, if batch processing is performed with 25 batches, the first wafer moves from the load lock chamber to the sputtering film formation chamber. Simultaneously or subsequently, the second wafer is introduced into the load lock chamber and the second wafer moves from the load lock chamber to the sputtering deposition chamber. In other words, the treatment is performed continuously or intermittently so as to increase the utilization rate of each film formation region of the load lock chamber and the sputtering film formation chamber as much as possible. Note that a processing gap, a waiting time, and the like may be provided as appropriate for various reasons.

  7). In the present application, regarding a processing chamber, a load lock chamber, and the like, “spatial independence” means being independent when a vacuum chamber is used, and geometrically, the chamber (spatial region 1) and the chamber. It means that there is no space passage (referred to as “macro space passage”) having a macro sectional area between other regions (space region 2). In addition, “spatial integration” means that when a vacuum chamber is formed, a substantially connected vacuum chamber is formed, and the entire atmospheric pressure is substantially uniform in a steady state. Means that any two points in the space region can be connected by a macro space passage that passes only through the interior. However, in these cases, it is a condition that there is no element that causes a significant pressure difference between both ends of the vacuum pump or the like in the middle of the macro space passage.

  8). In the present application, “power semiconductor device” refers to, for example, a power MOSFET, IGBT, LDMOSFET (Laterally Diffused MOSFET), and the like, and an integrated circuit having at least one of them. The same applies to “power MOS semiconductor device”, “IGBT semiconductor device”, “LDMOS semiconductor device”, and the like.

  9. In this application, “the state where the wafer and the wafer susceptor are close to each other” means a state where the wafer is held in contact with the wafer susceptor and a state where the wafer is not in contact with the wafer susceptor but the wafer is in the wafer susceptor. To tell.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

  An example of a prior patent application that discloses sputtering film deposition on a power MOSFET or the like is, for example, Japanese Patent Application No. 2009-92973 (Japan application date April 7, 2009).

1. Description of an example of a power MOSFET manufactured by a method of manufacturing a semiconductor device according to an embodiment of the present application (mainly FIG. 14)
FIG. 14 is a device top view showing an example of a power MOSFET manufactured by the method of manufacturing a semiconductor device according to the embodiment of the present application. As shown in FIG. 14, a power MOSFET element chip 8 (trench gate power MOS type semiconductor device) in which elements are formed on a square or rectangular plate-like silicon-based semiconductor substrate (wafer before being divided into individual chips). ) Occupies the main area of the source pad region 11 (aluminum-based pad) in the center. Below that, a strip-shaped repetitive device pattern region R (linear cell region) in which a strip-shaped gate electrode (corresponding to a columnar trench gate electrode) extending sufficiently longer than the width (or pitch) and a number of strip-shaped source contact regions are alternately formed. There is. More precisely, the linear cell region R extends almost entirely below the source pad region 11, and a portion surrounded by a broken line is a part thereof. In the periphery of the linear cell region R, there is a gate pad region 13 for leading the gate electrode from the periphery to the outside. Further, an aluminum guard ring 19 is provided therearound. The outermost peripheral portion of the chip 8 is an area when the wafer is divided by dicing or the like, that is, a scribe area 14.

2. Outline of related device cross-section process flow in manufacturing method of semiconductor device of one embodiment of the present application (mainly FIGS. 15 to 22)
In this section, an example of a 0.15-micrometer process linear trench gate type power MOSFET corresponds to the strip-like repetitive device pattern region cutout portion (linear cell region) R in FIG. 14 in section 2 based on FIGS. A process flow will be described with respect to a device cross section and the like.

  FIG. 15 is a device cross-sectional flow diagram (source contact groove forming resist pattern forming step) of the trench gate cell portion in the method of manufacturing a semiconductor device according to the embodiment of the present application. Here, an n-type epitaxial wafer 1 in which an n-type epitaxial layer (for example, the thickness of the epitaxial layer is about 4 micrometers) is formed on a 200 phi n + -type silicon single crystal wafer (silicon-based wafer) is used as a raw material wafer. As an example, the diameter of the wafer may be 300 phi, 450 phi, or other (for example, an n + type may be formed on the back surface after back-grinding an n-type silicon single crystal wafer). Further, the conductivity type of the wafer may be p-type. Further, the type of wafer is not limited to an epitaxial wafer, and may be another semiconductor substrate or an insulating substrate. Further, if necessary, it may be a semiconductor wafer or substrate other than silicon.

  As shown in FIG. 15, the semiconductor wafer 1 is mainly composed of an n + silicon substrate portion 1s and an epitaxial layer 1e. In the epitaxial layer 1e, there is an n-type drift region 2 which is an original n-type epitaxial layer. In the upper part, a p-type channel region (p-type base region) 3, an n + source region 4 and the like are formed. A plurality of trench gate electrodes (polysilicon electrodes) 6 are periodically provided so that the upper portion protrudes from the epitaxial layer 1e, and a gate insulating film 7 is provided around the middle and lower portions of each trench gate electrode 6. ing. An interlayer insulating film 21 is formed on the device surface side 1 a of the semiconductor wafer 1 to completely cover each trench gate electrode 6. As the interlayer insulating film 21, from the lower layer, for example, a silicon nitride film (silicon nitride insulating film) having a thickness of approximately 60 nm, a PSG film (silicon oxide insulating film) having a thickness of approximately 300 nm, A multilayer insulating film composed of a thick SOG film (silicon oxide insulating film) or the like can be exemplified.

  A resist film 9 for processing is formed on the interlayer insulating film 21. When dry etching is performed using the resist film 9 as an etching mask, a recess (source contact groove) 22 is formed as shown in FIG. Next, when the resist film 9 that is no longer needed is removed, the state is as shown in FIG.

  Next, when dry etching is further performed using the patterned interlayer insulating film 21 as an etching mask, the recess (source contact groove) 22 is extended to the upper end of the p-type channel region 3 as shown in FIG.

  FIG. 19 shows a device upper surface (wafer upper surface) corresponding to FIG. 18 (corresponding to FIG. 20) at this time. In FIG. 19, the cell repetition unit region G is also shown corresponding to FIG.

  Following FIG. 18, as shown in FIG. 20, the source contact groove 22 (for example, the groove bottom width is about 300 nm, the depth is about 850 nm, the aspect ratio is about 2 or more and about 5 or less, and the average is about 2.8. P + body contact region 5 is introduced into the surface region of p-type channel region 3 by ion implantation.

  Next, as shown in FIG. 21, a barrier metal film 23 is formed on substantially the entire device surface side 1 a of the semiconductor wafer 1. The barrier metal film 23 is composed of, for example, a lower barrier metal film, an upper barrier metal film, or the like. As the lower barrier metal film (partially silicided metal), in addition to titanium, TiW, Ta, W, WSi Etc. can be used. As the upper barrier metal film, TiW, TaN, etc. can be used in addition to titanium nitride.

  Subsequently, silicidation annealing is performed. When silicidation annealing is performed, the titanium film portion in contact with the silicon member is converted into titanium silicide over the entire thickness, but the illustration becomes complicated, so these changes are not displayed.

  Next, as shown in FIG. 22, an aluminum-based metal film 24 to be a source electrode is formed on almost the entire surface of the barrier metal film 23. As a source electrode material, AlCu, pure Al, a copper metal member, etc. can be used in addition to the silicon-added aluminum metal (AlSi) described here.

  Thereafter, the aluminum-based metal film 24 is patterned, and a final passivation insulating film (for example, an organic insulating film such as a coating-based polyimide resin film having a thickness of about 2 micrometers) is formed on the aluminum-based metal film 24. Form.

  Next, as shown in FIG. 23, a back grinding process is performed to reduce the original wafer thickness (for example, about 750 micrometers) to, for example, about 120 to 280 micrometers (that is, less than 300 micrometers).

  Next, as shown in FIG. 24, a multilayer metal film 15 (back metal electrode film) is formed on the back surface 1b of the wafer 1 by sputtering. The back metal electrode film 15 is formed from the side close to the wafer 1, for example, a back titanium film 15a (gold and nickel diffusion prevention layer), a back nickel film 15b (adhesive layer with a chip bonding material), and a back gold film 15c (nickel). For example, an antioxidant layer). Then, when divided into individual chips, a device as shown in FIG. 14 is obtained.

  This wafer backside multilayer metal deposition process will be described in detail in the next section.

3. Description of a metal film forming apparatus and the like used in the method of manufacturing a semiconductor device according to an embodiment of the present application (mainly described with reference to FIGS. 1 to 12, and further refer to FIG. 24)
In this section, a wafer processing apparatus (multilayer sputtering film forming apparatus) used in the wafer back surface multilayer metal film forming process described in FIG. 24 in the previous section will be further described. An example of a commercially available suitable apparatus for a 200φ wafer is a multilayer sputtering film forming apparatus SRH-420 manufactured by ULVAC, Inc.

  FIG. 1 is a top view of a wafer back surface multilayer metal film forming apparatus used in a method for manufacturing a semiconductor device according to an embodiment of the present application. FIG. 2 is a top view of a wafer back surface multilayer metal film forming apparatus used in the method for manufacturing a semiconductor device according to an embodiment of the present application (in FIG. 1, the target switching mechanism is made transparent so that the lower part can be easily seen). is there. FIG. 3 is a perspective view of the internal transfer robot, each wafer stage, the wafer on the stage, and the wafer susceptor for explaining how to move the wafer in the wafer backside multilayer metal film forming apparatus shown in FIGS. FIG. 4 is a top view of the wafer susceptor of FIG. FIG. 5 is a cross-sectional view of the wafer susceptor corresponding to the X-X ′ cross section of FIG. 4 (when held by the internal transfer robot). FIG. 6 is a front sectional view of the cooling wafer stages 63b and 63c of the wafer backside multilayer metal film forming apparatus shown in FIGS. FIG. 7 is a front sectional structural view of the lamp heating wafer stage 63a of the wafer back surface multilayer metal film forming apparatus shown in FIGS. FIG. 8 is a front sectional structural view (during degassing processing) of the load lock chamber 61 of the wafer backside multilayer metal film forming apparatus shown in FIGS. FIG. 9 is a schematic cross-sectional view when the wafer back surface multilayer metal film forming apparatus shown in FIGS. FIG. 10 is an enlarged cross-sectional view of the periphery of the multi-target film forming region 62b in the wafer back surface multilayer metal film forming apparatus of FIG. FIG. 11 is an enlarged bottom view of the magnetron magnet group shown in FIGS. 9 and 10. FIG. 12 is an enlarged sectional view of the target switching mechanism 59 shown in FIGS. 9 and 10. FIG. 13 is a process block flow diagram of a wafer back surface multilayer metal layer deposition process in the method for manufacturing a semiconductor device according to an embodiment of the present application. Based on these, a metal film forming apparatus used in the method of manufacturing a semiconductor device according to an embodiment of the present application, a wafer back surface multilayer metal layer forming process using the metal film forming apparatus, and the like will be described.

  First, the structure and the like of a single chamber type multilayer sputtering film forming apparatus 51 used in the wafer back surface multilayer metal film forming process will be described with reference to FIGS. As shown in FIG. 1 or 2, the single chamber type multilayer sputtering film forming apparatus 51 includes a load port unit 52 and a film forming unit 53. A wafer transfer container or wafer cassette 54 that accommodates the wafer 1 to be processed can be placed in the load port portion 52. The wafer 1 to be processed 1 has a tip 56a of the external robot 56 (the upper surface is an elastic pad). The device surface 1a is held and placed on the lift stage 50, and then the lift stage 50 is lowered to set the wafer 1 on the wafer susceptor 65 (metal or heat-resistant insulator). Here, if necessary, the orientation (direction of notch or orientation flat) of the wafer 1 is aligned.

  A load lock chamber 61 and a sputtering film formation processing chamber 57 are provided in the film formation processing unit 53, and the load lock chamber 61 can be spatially independent from the outside. In the sputtering film forming chamber 57, single target film forming regions 62a and 62c and a multi-target film forming region 62b are provided. Corresponding to these, the lamp heating wafer stage 63a and the cooling wafer stage 63b are provided. , 63c. In addition, a wafer stage 63d with a vacuum flange is provided in the sputtering film forming chamber 57 corresponding to the load lock chamber 61, and between the wafer stage 63d with a vacuum flange and the wafer stages 63a, 63b, 63c. An internal transfer robot 58 that transfers the wafer 1 together with the wafer susceptor 65 is provided.

  Furthermore, the film forming unit 53 is provided with a target switching mechanism 59 (upper electrode or cathode) for switching the target in the multi-target film forming region 62b, and includes, for example, a titanium target 64t (nonmagnetic target). ), Nickel target 64n (magnetic target) and the like are set. Normally, three targets can be set on the target switching mechanism 59, that is, the target holding rotary table, and here, there is one empty position 64x.

  Next, the internal transfer robot 58, the wafer susceptor 65, the wafer stages 63a, 63b, 63c, etc. will be further described with reference to FIG. As shown in FIG. 3, the internal transfer robot 58 can move up and down and rotate in both directions, and can transfer four wafer susceptors 65 (with the wafer 1 set) simultaneously. At this time, the wafer 1 is accommodated in the wafer susceptor 65 with its back surface 1b facing up. The wafer stages 63a, 63b, 63c on each stage support base 55 have various structures as required. For example, the wafer stage 63d for the load lock chamber 61 (degas chamber) includes an O-ring 60. And a metal stage 99 or the like for raising the height of the wafer 1 is provided.

  Next, the detailed structure of the wafer susceptor 65 and the like will be described with reference to FIGS. As shown in FIG. 4, the wafer susceptor 65 is made of a ring-shaped metal (for example, stainless steel) or an insulator (for example, quartz), and is provided with a misalignment prevention notch 65n around the wafer susceptor 65. Misalignment during film processing is prevented. Here, when the multilayer film forming process involves processing of 250 degrees Celsius or more as a whole, for example, a susceptor 65 made of quartz wafer is used, and when processing of 250 degrees Celsius or more is not involved, for example, stainless steel is used. A susceptor 65 (for example, made of austenitic non-magnetic stainless steel) is used.

  FIG. 5 shows a cross section of the wafer susceptor 65 that holds the wafer 1 held by the internal transfer robot 58. As shown in FIG. 5, the periphery of the wafer 1 is held by the internal flat portion of the wafer susceptor 65 with the back surface 1b facing upward, and the wafer susceptor 65 holds the periphery of the internal transfer robot 58. Is held by the tip of the.

  Next, the sectional structure of the non-heating stages 63b and 63c will be described with reference to FIG. As shown in FIG. 6, for example, an electrostatic chuck 68 made of ceramic having an electrode inside through a metal spacer 67 made of copper, for example, on a water-cooled holder 66 made of copper (cooling base metal plate). A wafer surface protective layer 70 such as a polyimide film is provided thereon so as not to damage the device surface 1 a of the wafer 1. The wafer susceptor 65 is held on the cooling base metal plate 66 via the susceptor positioning insulating ring 69a. In this state, the wafer 1 is separated from the wafer susceptor 65 and supported by the wafer surface protective layer 70. .

  Next, the sectional structure of the lamp heating wafer stage 63a will be described with reference to FIG. As shown in FIG. 7, a reflector 73 is provided on a stage support base 55, a metal wafer holder base 71 is provided around the reflector 73, and a quartz window 98 is provided on the opening of the wafer holder base 71. ing. A lamp heater 72 is provided between the quartz window 98 and the reflection plate 73. A wafer susceptor 65 is placed on the wafer holder base 71 via a susceptor positioning insulating ring 69b, in which the wafer 1 is held with its back surface 1b facing up.

  Next, a cross-sectional structure of the load lock chamber 61 (a state in which it is blocked from the outside) will be described with reference to FIG. 8 (see FIG. 3). As shown in FIG. 8, the load lock chamber 61 is blocked by a wafer stage 63 d with a vacuum flange having an O-ring 60 in the same manner as the wafer gate 77 having the other portions and the O-ring 60. A gas supply line 76 (gas supply nozzle) is provided above the load lock chamber 61, and a wafer back surface heating mechanism 80 including a reflector 73, a lamp heater 72, a quartz window 98 and the like is also provided directly below the gas supply line 76. Is provided. A wafer susceptor 65 is placed on the wafer stage 63 d with a vacuum flange via a metal stage 99. At this time, the wafer 1 is held by the wafer susceptor 65, and the wafer 1 and the metal stage 99 are separated.

  Next, referring to FIG. 9, the vacuum system of the wafer processing apparatus 51 (multilayer sputtering film forming apparatus), the load lock chamber (degas chamber) 61, each sputtering film forming processing chamber 57, film forming processing regions 62a, 62b, 62c, etc. Will be further described. As shown in FIG. 9, the main part of each wafer stage 63a, 63b, 63c, 63d is in the sputtering film forming chamber 57 and can be moved up and down, and the load lock chamber 61 is moved upward by the wafer stage 63d. The film formation chamber 57 is spatially independent. On the other hand, the film processing regions 62a, 62b, and 62c also become ready to perform processing on the wafer 1 by raising the wafer stages 63a, 63b, and 63c. The other portions of the film forming chamber 57 are not spatially independent but basically have substantially the same atmospheric pressure.

  Next, the vacuum system will be described. As shown in FIG. 9 (for convenience of illustration, the wafer susceptor 65 is omitted in FIG. 9 and FIG. 10), the load lock chamber 61 includes a turbo molecular pump 81, a dry roughing pump 78, and the like. The vacuum system (load lock vacuum system) is evacuated. While this load lock vacuum system is operating, the load lock exhaust valve 87 and the molecular pump valve 82 are open. At this time, normally, the vacuum system of the film forming chamber 57 (film forming chamber vacuum system) is also in an operating state. The vacuum chamber of the film forming chamber is mainly composed of a cryopump 79. During operation of this pump, the main exhaust valve 86 is open, and the roughing valve 84, cryopump exhaust valve 85, dry pump valve 83 are open. Etc. are closed. In the roughing at the start of exhausting by the cryopump 79, the main exhaust valve 86 and the cryopump exhaust valve 85 are closed, the roughing valve 84, the dry pump valve 83, etc. are opened, and the exhaust pipe 88 (vacuum) Roughing is performed by the dry roughing pump 78 via the exhaust system. Here, in a normal state, the molecular pump valve 82 and the dry pump valve 83 are not simultaneously opened.

  Next, the structure of each film-forming process area 62a, 62b, 62c will be described. As shown in FIG. 9, the film forming regions 62a and 62c are formed into room-like compartments (room-like compartments or room-like compartments) in which the inner wall 91 of the film-forming treatment chamber 57 partially protrudes toward the outside and the cylindrical lower part is opened. The cylindrical section) is the main part. In this cylindrical section, a film adhesion preventing shield 75 (which is set to the ground potential when used) is provided, and another nickel target 64s (magnetic target), gold, for example, is disposed on the upper inner side of the cylindrical section. A target 64a (nonmagnetic target) or an upper electrode (cathode electrode) to which the target 64a is attached is provided. Further, magnetron magnet groups (magnet-mounted rotating plates) 74 are provided on the upper outer sides of the cylindrical sections.

  Similarly, as shown in FIG. 9, the film formation processing region 62b is a room-like section (room) in which the inner wall 91 of the film formation processing chamber 57 partially protrudes toward the outside and the cylindrical lower part is opened. The main part is a cylindrical section or a cylindrical section). In the cylindrical section, a film adhesion prevention shield 75 (which is set to the ground potential when used) is similarly provided. Here, since the film forming region 62b is used by switching a plurality of targets, there is an expansion section 90 spatially connected to the cylindrical section to accommodate the target switching mechanism 59 (upper electrode or cathode). Is provided. Here, as before, a magnetron magnet group (magnet mounting rotary plate) 74, a titanium target 64t (nonmagnetic target) and a nickel target (magnetic target) 64n constituting the cathode are installed. Is complicated, and will be described with reference to FIG.

  As shown in FIG. 10, the wall surface (for example, made of aluminum metal) of the film forming chamber 57 in this portion has a double structure of an inner wall 91 and an outer wall 89, and a target switching mechanism 59 is accommodated between them. It can be rotated horizontally. The target switching mechanism 59 includes a target holding plate that can rotate while holding a plurality of targets on its lower surface, a rotating mechanism, and the like. A magnetron magnet group 74 (magnet-mounted rotating plate) is provided outside the outer wall 89 via a magnet-target interval wall 92, and is rotated by a rotating mechanism during wafer processing. A gas supply nozzle 76 (gas supply line) is provided on the upper side surface of the cylindrical section of the multi-target film formation region 62b.

  Note that the structures of the other film forming regions 62a and 62c are substantially the same as the peripheral portion L of the single target film forming region in FIG. However, in the case of the other film forming regions 62a and 62c, the target does not move and is fixed. Other parts, that is, the film adhesion prevention shield 75, the gas supply nozzle 76, the magnetron magnet group 74, the magnet-target spacing wall 92 (for example, made of austenitic non-magnetic stainless steel), etc. have substantially the same structure. Yes.

  Next, the detailed structure of FIG. 10 and other magnetron magnet groups 74 (the same applies to each magnetron magnet group 74 of FIG. 9) will be described with reference to FIG. As shown in FIG. 11, circular permanent magnets 94n, 94n are formed in a letter "C" on two concentric circles sharing a rotation center 93, for example, on a metal plate 74 (for example, made of austenitic non-magnetic stainless steel). It is arranged. At this time, the permanent magnets 94n and 94n are arranged so as to form a containment magnetic field along the circumference of a concentric circle by alternately changing the surface to the north and south poles.

  Next, the detailed cross-sectional structure of the target mounting rotary plate, which is the main part of the target switching mechanism 59 in FIG. 10, will be described with reference to FIG. As shown in FIG. 12, the target mounting rotary plate 59 (for example, made of copper) is provided with, for example, three circular openings, and a target is attached thereto as necessary. Here, a nickel target 64n (for example, a diameter of about 290 millimeters and a thickness of about 5 millimeters) is attached as a magnetic target, and a titanium target 64t (for example, a diameter of about 304 millimeters and a thickness of about 12 millimeters) is attached as a nonmagnetic target. Each target is attached via a backing metal plate 95 (first and second backing plates, for example, made of copper, having a diameter of about 360 millimeters and a thickness of about 5 millimeters). The distance D between magnet targets (the distance from the lower end of the magnetron magnet group to the lower surface of the target) is, for example, about 22 millimeters for the nickel target 64n (magnetic target) and 29 for the titanium target 64t (nonmagnetic target), for example. A millimeter can be exemplified.

  In the magnetic target 64n, since the magnetic field may be weak in the periphery, such a problem can be avoided by making the diameter of the target smaller than the diameter of the backing plate. In addition, since an undesired film may adhere to the periphery of the target having such a small diameter, in this case, an adhesion preventing ring 97 (for example, made of austenitic non-magnetic stainless steel) is used to prevent film adhesion. If provided, such a problem can be avoided. Of course, these measures are not essential.

  Further, if a sufficient magnetic field is to be secured on the lower surface on the magnetic target 64n side, the magnetic field may become too strong on the lower surface on the nonmagnetic target 64t side. In that case, the backing plate 95 and the nonmagnetic target 64t If a spacer plate 96 (a spacer plate, for example, made of copper, having a diameter of about 304 millimeters and a thickness of about 0.5 millimeters) is interposed therebetween, such a problem can be avoided. Of course, these measures are not essential.

4). Description of wafer back surface multilayer metal layer film forming process (example of power MOS device) in the method of manufacturing a semiconductor device according to an embodiment of the present application (mainly referring to FIG. 13, FIGS. 1 to 12, 23, and 24) See
In this section, the wafer back surface multilayer metal layer film forming process using the multilayer sputtering film forming apparatus 51 described in section 3 will be described taking a power MOS device (the back electrode structure is shown in FIG. 24) as an example.

  FIG. 13 is a process block flow diagram of a wafer back surface multilayer metal layer deposition process in the method for manufacturing a semiconductor device according to an embodiment of the present application. Based on this, a wafer back surface multilayer metal layer film forming process and the like in the method of manufacturing a semiconductor device according to an embodiment of the present application will be described.

  As shown in FIGS. 13 and 1, the processed wafer 1 in the state of FIG. 23 is stored in a wafer transfer container 54 (for example, stored with the back surface 1 b of the wafer 1 facing upward) in a multilayer state. When the wafer 1 is received by the load port unit 52 of the sputtering film forming apparatus 51, the wafer 1 to be processed is taken out of the wafer transfer container 54 by the external robot 56 and placed on the lift stage 50 with the back surface thereof facing up. . Thereafter, the lift stage 50 is lowered and the wafer 1 is accommodated in the wafer susceptor 65 (mounting process 101 on the susceptor).

  Next, as shown in FIG. 8, the wafer susceptor 65 on which the wafer 1 is placed is introduced into the load lock chamber 61 by the external robot 56 through the wafer gate 77, and the back surface 1 b of the wafer 1 is turned upward. In this state, it is placed on the wafer stage 63d (introduction process 102 to the load lock chamber). At this time, when there is another wafer processed in advance in the load lock chamber 61, the other wafer is taken out first. The time required for setting to the susceptor and load lock chamber and for taking out from the susceptor and load lock chamber is, for example, about 1 minute and 40 seconds.

Next, the wafer gate 77 is closed and evacuation of the load lock chamber 61 is started, whereby the degassing process 103 is executed. Specifically, first, the degree of vacuum is raised to, for example, about 5 × 10 ⁻³ Pascal or more by vacuuming (required time is about 30 seconds). Subsequently, the lamp 72 is turned on to raise the temperature of the wafer 1 to about 200 degrees Celsius. In this state (lamp heating and evacuation are continued), a degassing process (a process for removing moisture on the wafer) is performed for about 50 seconds, for example. When the degassing process 103 is completed, the lamp 72 is turned off. Thus, the processing time for the load lock chamber 61 is, for example, about 3 minutes per wafer (referred to as “load lock related unit processing time”).

  Next, in FIG. 8, the wafer stage 63d is lowered (at this time, the other stages 63a, 63b, 63c are also lowered simultaneously), and the wafer on which the wafer 1 is placed by the internal transfer robot 58 in the manner shown in FIG. The susceptor 65 is transferred to the wafer stage 63a (in this case, a standby stage). At this time, if there is a wafer susceptor 65 on which another wafer is placed on each wafer stage 63a, 63b, 63c, they are also transferred to the next stage at the same time. The sputtering film forming chamber 57 is maintained at a degree of vacuum (for example, an argon gas atmosphere) of about 0.5 Pascal (the range is, for example, about 0.2 to 0.8 Pascal). The wafer stage 63a is set to room temperature (room temperature) when used as a standby stage. With the wafer 1 placed on the wafer susceptor 65, the wafer 1 waits until the processing in the other stages 63b, 63c, 63d is completed (standby step 104 in FIG. 13). This waiting time is generally rate-determined or determined by the load lock related unit processing time. When the standby step 104 is completed, the wafer 1 is transferred onto the cooling wafer stage 63b by the internal transfer robot 58 while being placed on the wafer susceptor 65 simultaneously with the transfer of the wafer being processed in the same manner as before. The

  Next, the cooling wafer stage 63b shown in FIG. 9 is raised, and a titanium film is formed by sputtering film formation in the multi-target film formation region 62b (titanium film formation step 105 in FIG. 13). Examples of film formation conditions include a film thickness of about 100 nm, a processing time of about 15 seconds, a DC power of about 8 kilowatts, an argon flow rate of about 15 sccm, and a gas pressure of about 0.3 Pascal. Here, the setting of the wafer stage and the like is an electrostatic chuck off and a water cooling state at room temperature. When the titanium film forming step 105 is completed, the DC power is turned off once.

  Subsequently, while setting the wafer stage and the like in a water-cooled state at room temperature, the electrostatic chuck is turned on (applied voltage is, for example, about 2 kilovolts), the target is switched to the nickel target 64n, and the titanium film formed by sputtering film formation is used. Are formed (nickel film forming step 106 in FIG. 13). Examples of film forming conditions include a film thickness of about 200 nm, a processing time of about 35 seconds, a DC power of about 4 kilowatts, an argon flow rate of about 10 sccm, and a gas pressure of about 0.4 Pascal. When the nickel film forming process 106 is completed, the DC power and the applied voltage of the electrostatic chuck are turned off, and the process waits for the completion of processing of another wafer in this state (referred to as “preliminary standby process”). If the process gas such as argon gas is stopped during the preliminary standby process, the vacuum degree of the entire sputtering film forming chamber 57 may increase. In such a case, although it is not essential, if a process gas such as an argon gas (for example, an argon flow rate of about 15 sccm in this case) is kept flowing, the problem can be avoided. Can do. This point is the same in the standby step 104 in the previous single target film formation processing region 62a (standby region). For example, if an argon flow rate of about 10 sccm is kept flowing, such a problem can be similarly avoided. . When the preliminary standby process in the multi-target film formation processing region 62b is completed, the wafer 1 is placed on the wafer susceptor 65 simultaneously with the transfer of the wafer being processed in the same manner as before, by the internal transfer robot 58. It is transferred onto the cooling wafer stage 63c.

  Next, as shown in FIG. 9, the cooling wafer stage 63c is raised, and the gold film formation step 107 (FIG. 13) is performed by sputtering film formation in the single target film formation region 62c. Examples of film formation conditions include a film thickness of about 100 nm, a processing time of about 15 seconds, a DC power of about 2 kilowatts, an argon flow rate of about 15 sccm, and a gas pressure of about 0.6 Pascal. When the gold film forming step 107 is completed, the DC power is turned off, and the process waits for the processing of another wafer to be completed in this state (referred to as “preliminary standby step”). If the process gas such as argon gas is stopped during the preliminary standby process, the vacuum degree of the entire sputtering film forming chamber 57 may increase. In such a case, although it is not essential, if a process gas such as an argon gas (for example, an argon flow rate of about 15 sccm in this case) continues to flow as in the film forming process, The problem can be avoided. When the preliminary standby process in the single target film formation processing region 62c is completed, the wafer 1 is placed on the wafer susceptor 65 at the same time as the transfer of the wafer being processed in the same manner as described above, by the internal transfer robot 58. Then, the wafer is transferred onto the wafer stage 63d used in the load lock chamber 61.

  Next, as shown in FIG. 8, when the wafer stage 63 d is raised and the load lock chamber 61 is spatially independent from the outside, air is supplied from the gas supply line 76 to the same atmospheric pressure as the outside air. Become. Therefore, the wafer gate 77 is opened, and the external robot 56 shown in FIG. 1 discharges the wafer susceptor 65 on which the wafer 1 is placed onto the load port portion 52 (discharge process 108 from the load lock chamber in FIG. 13). Therefore, with the lift stage 50 raised and the wafer 1 lifted, the external robot 56 transfers the wafer 1 to the wafer transfer container 54 (step 109 for removing from the susceptor in FIG. 13). This completes the cycle of the multilayer plating unit cycle 100 (FIG. 13) and returns to the susceptor before the start of the mounting step 101.

  In a normal mass production process, such a cycle is sequentially repeated, and a large number of wafers are continuously processed so that the free time of each stage 63a, 63b, 63c, 63d is as short as possible.

5. Description of wafer back surface multilayer metal layer film forming process (example of IGBT-based device) in the method of manufacturing a semiconductor device according to an embodiment of the present application (mainly referring to FIG. 13, FIG. 1 to FIG. 12, FIG. 23 and FIG. 24) reference)
In Section 4, the case where the wafer back surface multilayer metal layer film forming process in the method of manufacturing a semiconductor device according to the embodiment of the present application is applied to the manufacture of a power MOS device is described. A case where the present invention is applied to manufacture will be described. As shown in FIG. 13, since most processes are common, only different parts will be described.

  As shown in FIG. 13, the only difference is that the Ni film forming step 111 in the Ni film forming region 62a is executed instead of the standby step 104 in terms of process. Further, regarding the structure of the back electrode, the only difference is that in FIG. 24, another nickel film (second nickel film) is added to the silicon substrate 1s side. Of course, the power MOS device and the IGBT device have different structures in the silicon substrate and on the device surface 1a of the silicon substrate, but these differences are not essential with respect to the structure of the back electrode and the manufacturing method thereof. . Further, even in a device belonging to the same category (for example, a power MOS device), there are various back electrode structures depending on the product type, and in mass production, products of various specifications usually flow around.

  The Ni film forming step 111 in the Ni film forming region 62a will be described with reference to FIGS. As shown in FIGS. 7 and 9, when the wafer 1 placed on the wafer susceptor 65 is placed on the lamp heating wafer stage 63a, the wafer stage 63a is raised and the Ni film forming step 111 (FIG. 13) is performed. Executed. Examples of film formation conditions include a film thickness of about 50 nm, a processing time of about 10 seconds, a DC power of about 4 kilowatts, an argon flow rate of about 10 sccm, and a gas pressure of about 0.4 Pascal. At this time, since the lamp heating is in an off state, the wafer temperature is room temperature or a temperature not much higher than that. When the Ni film forming process 111 is completed, the DC power is turned off, and the process waits for the completion of processing of another wafer in this state (referred to as “preliminary standby process”). If the process gas such as argon gas is stopped during the preliminary standby process, the vacuum degree of the entire sputtering film forming chamber 57 may increase. In such a case, although it is not essential, if a process gas such as an argon gas (for example, an argon flow rate of about 10 sccm in this case) is kept flowing, the problem can be avoided. Can do. When the preliminary standby process is completed, the wafer 1 is transferred onto the cooling wafer stage 63b by the internal transfer robot 58 while being placed on the wafer susceptor 65 simultaneously with the transfer of the wafer being processed in the same manner as before. The

6). Description of wafer back surface multilayer metal layer film forming process (example of LD-MOSFET system device) in the method of manufacturing a semiconductor device according to an embodiment of the present application (mainly referring to FIG. 13, FIGS. 1 to 12, 23 and FIG. (See 24)
In section 5, the case where the wafer back surface multilayer metal layer deposition process in the method of manufacturing a semiconductor device according to an embodiment of the present application is applied to the manufacture of an IGBT-based device has been described. A case where the present invention is applied to device manufacturing will be described. As shown in FIG. 13, since most processes are common, only different parts will be described. However, the Ni film forming step 111 is different in that a heat treatment is applied. In this process, unlike sections 4 and 5, wafer susceptor 65 is made of quartz.

  As shown in FIG. 13, in addition to the Ni film forming step 111 in the Ni film forming region 62a, the nickel layer (second nickel film) formed in the Ni film forming step 111 by executing the alloy process 112 is performed. The only difference is that it is converted to a nickel silicide layer. Also, regarding the structure of the back electrode, the only difference is that a nickel silicide film is added to the silicon substrate 1s side in FIG. Of course, the IGBT device and the LD-MOS device have different structures in the silicon substrate and on the device surface 1a of the silicon substrate, but these differences are related to the structure of the back electrode and the manufacturing method thereof as before. Is not essential. Further, even in a device belonging to the same category (for example, a power MOS device), there are various back electrode structures depending on the product type, and in mass production, products of various specifications usually flow around.

  The Ni film forming step 111 in the Ni film forming region 62a will be described with reference to FIGS. As shown in FIGS. 7 and 9, when the wafer 1 placed on the wafer susceptor 65 is placed on the lamp heating wafer stage 63a, the wafer stage 63a is raised, the lamp heater 72 is turned on, and preliminary overheating is performed. A process (wafer temperature is, for example, about 350 degrees Celsius and a preheating time of about 60 seconds) is performed. Subsequently, the Ni film forming step 111 (FIG. 13) is executed as it is. Examples of film formation conditions include a film thickness of about 50 nm, a processing time of about 10 seconds, a DC power of about 4 kilowatts, an argon flow rate of about 10 sccm, a gas pressure of about 0.4 Pascal, and a wafer temperature of about 350 degrees Celsius. . Subsequently, the alloy process 112 (FIG. 13) is executed with the DC power turned off as it is. Examples of alloy processing conditions include a processing time of about 60 seconds, an argon flow rate of about 10 sccm, a gas pressure of about 0.4 Pascal, and a wafer temperature of about 350 degrees Celsius. When the alloy process 112 is completed, the lamp heater 72 is turned off, and the process waits for another wafer to be processed in this state (referred to as “preliminary standby process”). If the process gas such as argon gas is stopped during the preliminary standby process, the vacuum degree of the entire sputtering film forming chamber 57 may increase. In such a case, although it is not essential, if a process gas such as an argon gas (for example, an argon flow rate of about 10 sccm in this case) is kept flowing, the problem can be avoided. Can do. When the preliminary standby process is completed, the wafer 1 is transferred onto the cooling wafer stage 63b by the internal transfer robot 58 while being placed on the wafer susceptor 65 simultaneously with the transfer of the wafer being processed in the same manner as before. The

7). Supplementary explanation about various aspects in the mass production process such as the wafer back surface multilayer metal layer film forming process (various devices) in the manufacturing method of the semiconductor device of one embodiment of the present application (mainly referring to FIG. 13, FIGS. 1 to 12, (See FIG. 23 and FIG. 24)
As described in Sections 4 to 6, since the back electrode structure of power devices varies widely between product categories or within product categories, devices of various back surface structures are inevitably mixed in the mass production process. Will flow. At this time, as described mainly in section 4, the magnetic target and the non-magnetic target are switched in at least one of a plurality of processing sections (film forming process areas) partitioned in the same film forming process chamber. By forming two or more layers, the throughput of the entire mass production process can be significantly improved.

  Even if only a product with a single specification is manufactured, it is possible to keep the number of film forming regions of the multilayer film forming apparatus to a minimum number.

  Further, as described in FIG. 9, since there are a plurality of film formation sites (film formation processing regions 62a, 62b, 62c) in the same vacuum chamber (sputtering film formation processing chamber 57), the vacuum exhaust system is commonly used. There is a merit that you can. Similarly, the load lock chamber 61 and the sputtering film formation processing chamber 57 have an advantage that a roughing pump of an evacuation system can be shared (may be separated).

  In the above embodiment, there are three film forming regions, and one of them is a multi-target film forming region. However, of the back surface specifications that flow through the mass production process, The number of multi-target film forming regions is appropriately increased by increasing the number of multi-target film forming regions (in this example, the maximum number of layers is 4 and there are 3 film forming regions). Since a plurality of film forming regions can be utilized as much as possible, the effect of improving the throughput is very large. In other words, if there is a product that exceeds the number of membranes that can be processed in order (pipeline processing), the product must be reverse-rotated once in the processing of the product, and during that time, the benefits of forward processing cannot be obtained. Become. Such a progressive process has an advantage that the processing efficiency is overwhelmingly high because basically all the stages except the transfer period are occupied by the wafer.

  For example, in the example of section 4, if the processing target is only the type having the maximum number of layers 3, the number of film forming regions can be only two (film forming regions 62b and 62c). This is the same in other examples, but the processing time for the longest processing site (load lock chamber or film formation processing area) (referred to as “maximum unit processing time”) is the overall rate limiting, Then, the processing time related to the load lock chamber is the longest overall (in some cases, the processing time related to the film forming process area 62a and other film forming process areas may be maximized). Accordingly, even if a plurality of films (up to three layers can be formed at the position site in the above-described apparatus configuration) are formed by switching the target in a film forming process area other than the film forming process area related to the maximum unit processing time, it is necessary to do so. Since the time is usually less than the maximum unit processing time, it does not affect the throughput.

  Further, as shown in FIG. 2, since the wafer stages 63a, 63b, 63c, and 63d are on the circumference around the rotation center of the internal transfer robot 58, there is an advantage that the transfer can be performed quickly. In this connection, in the target switching, as described with reference to FIGS. 9 and 10, the wafer stage 63b is not moved in a plane (of course, it may be moved), but the target (target switching mechanism 59) side. Is rotated (or may be moved in parallel), and there is an advantage that an operation such as returning to the original position is not required for transfer between wafer stages.

  Further, since the target (target switching mechanism 59) side is moved, there is an advantage that only one set of the magnetron magnet group 74, the shield 75, etc. is required for the film forming region.

8). Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. .

  For example, in the above-described embodiment, the power MOSFET has been specifically described as an example. However, the invention of the present application is not limited thereto, and other single units such as IGBT and LDMOSFET, integrated circuit elements including them, and the like. Needless to say, it can be widely applied.

  In the above-described embodiment, the N-channel type device such as the N-channel type power MOSFET has been specifically described. However, the invention of the present application is not limited thereto, and the P-channel type device such as the P-channel type power MOSFET is used. Needless to say, it can also be applied. In that case, what is necessary is just to perform PN inversion operation which carries out total exchange of P and N in the said embodiment.

  Furthermore, in the above-described embodiment, an example in which the present invention is applied to the formation of a multilayer metal film on the back surface of a substrate such as a wafer has been specifically described. However, the invention of the present application is not limited thereto, and the back surface of the substrate such as a wafer is described. Needless to say, the present invention can also be applied to the formation of a multilayer film composed of an insulating film and a metal film, a multilayer metal film on the device surface (first main surface) of a substrate such as a wafer, and a multilayer film composed of an insulating film and a metal film. Yes.

1 Semiconductor wafer (epitaxial wafer)
1a Device surface of the wafer (first main surface)
1b Wafer backside 1e Epitaxial layer (n-type epitaxial layer)
1s n + silicon substrate part 2 n-type drift region 3 p-type channel region (p-type base region)
4 n + source region 5 p + body contact region 6 Trench gate electrode (polysilicon electrode)
7 Gate insulating film 8 Chip or chip area 9 Resist film 11 Source pad 13 Gate pad 14 Scribe area (dicing area)
15 Back metal electrode film 15a Back titanium film 15b Back nickel film (first nickel film)
15c Back surface gold film 19 Guard ring 21 Interlayer insulating film 22 Recessed portion (source contact groove)
23 Barrier metal film 24 Aluminum metal film (source electrode)
50 Lift stage 51 Wafer processing equipment (multilayer sputtering deposition equipment)
52 Load port section 53 Deposition processing section 54 Wafer cassette (wafer transfer container)
55 Stage support base 56 External robot 56a Front end of external robot 57 Sputtering film formation processing chamber 58 Internal transfer robot 59 Target switching mechanism (upper electrode or cathode)
60 O-ring 61 Load lock chamber (degas chamber)
62a Single target film formation region (standby region or third sputtering film formation region)
62b Multi-target film formation process area (first sputtering film formation process area)
62c Single target film formation region (second sputtering film formation region)
63a Lamp heating wafer stage (fourth wafer stage)
63b Cooling wafer stage (second wafer stage)
63c Cooling wafer stage (third wafer stage)
63d Wafer stage with vacuum flange (first wafer stage)
64a gold target (non-magnetic target)
64n nickel target (magnetic target)
64s Other nickel target (magnetic target)
64t titanium target (non-magnetic target)
64x Empty position of target switching mechanism 65 Wafer susceptor 65n Misalignment prevention notch 66 Water cooling holder (base metal plate for cooling)
67 Metal spacer 68 ESC ceramic plate (with electrodes inside)
69a, 69b Insulating ring for positioning susceptor 70 Wafer surface protective layer (polyimide film)
71 Wafer holder base 72 Lamp heater 73 Reflector plate 74 Magnet group for magnetron (rotary plate equipped with magnet)
75 Film adhesion prevention shield (first, second and third film adhesion prevention shields)
76 Gas supply line (gas supply nozzle)
77 Wafer gate 78 Dry roughing pump 79 Cryo pump 80 Wafer back surface heating mechanism 81 Turbo molecular pump 82 Molecular pump valve 83 Dry pump valve 84 Roughing valve 85 Cryo pump exhaust valve 86 Main exhaust valve 87 Load lock exhaust valve 88 Exhaust pipe ( (Evacuation system)
89 Outer wall of film forming chamber 90 Expansion compartment for storing target switching mechanism 91 Inner wall of film forming chamber 92 Magnet-target spacing wall 93 Magnet rotation center 94n N pole of magnet 94s S pole of magnet 95 Backing metal plate 96 Spacer plate 97 Adhesion prevention ring 98 Quartz window 99 Metal stage 100 Multilayer plating unit cycle 101 Mounting process to susceptor 102 Introduction process to load lock chamber 103 Degassing process (vacuum process)
104 standby process 105 Ti film forming process in Ti / Ni film forming region (first sputtering film forming process)
106 Ni film forming step in Ti / Ni film forming region (second sputtering film forming process)
107 Gold film formation process 108 Ejection process from load lock chamber 109 Removal process from susceptor 111 Ni film formation process in Ni film formation area 112 Alloy treatment process D Distance between magnet targets L Single target film formation process area peripheral part G Cell repeat unit area R Strip-like repeat device pattern area cut-out part

Claims (20)

A method of manufacturing a semiconductor device using the following wafer processing apparatus, wherein the wafer processing apparatus includes:
(X1) a load lock room that is spatially independent from the outside;
(X2) Sputtering deposition processing chamber that is spatially independent of the outside and the load lock chamber and is spatially integrated;
(X3) first and second sputtering film forming regions provided in the sputtering film forming chamber;
(X4) a target switching mechanism in the first sputtering film forming region;
(X5) a magnetic target and a non-magnetic target held by the target switching mechanism,
Here, the manufacturing method of the semiconductor device includes the following steps:
(A) introducing a wafer into the load lock chamber and performing a vacuum treatment;
(B) After the step (a), in the first sputtering film forming region, the first sputtering film forming process using the magnetic target and the first sputtering film forming process using the non-magnetic target are performed on the wafer. Performing the sputtering film forming process of 2;
(C) A step of performing a third sputtering film forming process on the wafer in the second sputtering film forming region after the step (a);
(D) A step of repeatedly and continuously executing the processes including the steps (a), (b) and (c) on another wafer as soon as the load lock chamber is empty.     In the method of manufacturing a semiconductor device according to the item 1, the evacuation system is common to the first sputtering film formation region and the second sputtering film formation region.     In the method for manufacturing a semiconductor device according to the item 2, a set of magnetron magnet groups is provided in the first sputtering film forming region.     In the method for manufacturing a semiconductor device according to the item 3, the vacuum processing in the step (a) is degassing processing.     In the method for manufacturing a semiconductor device according to the item 4, the switching of the target in the first sputtering film forming region is performed by moving the magnetic target and the nonmagnetic target.     6. The method of manufacturing a semiconductor device according to 5 above, wherein the first sputtering film forming process, the second sputtering film forming process, and the third sputtering film forming process are performed on the back surface of the wafer and the other wafer. Executed.     In the method of manufacturing a semiconductor device according to item 6, the thickness of the wafer and the other wafer is less than 300 micrometers. 8. The method for manufacturing a semiconductor device according to item 7, wherein the wafer processing apparatus further includes:
(X6) a first wafer stage provided so as to form the bottom of the load lock chamber;
(X7) a second wafer stage provided in the first sputtering film formation region;
(X8) A third wafer stage provided in the second sputtering film forming region. 9. The method for manufacturing a semiconductor device according to item 8, wherein the wafer processing apparatus further includes:
(X9) a set of first film adhesion preventing shields provided in the first sputtering film formation region;
(X10) A pair of second film adhesion preventing shields provided in the second sputtering film forming region.     In the method of manufacturing a semiconductor device according to the item 9, the first wafer stage, the second wafer stage, and the third wafer stage are substantially on the same circumference in plan view.     In the method of manufacturing a semiconductor device according to the item 10, the wafer and other wafers in the wafer processing apparatus are processed in a state where each wafer of the wafer and the other wafer is close to a ring-shaped wafer susceptor. Executed.     12. In the method of manufacturing a semiconductor device according to the item 11, the first sputtering film forming process is a titanium film sputtering film forming process, and the second sputtering film forming process is a first nickel film sputtering film forming process. The third sputtering film forming process is a gold film sputtering film forming process.     In the method of manufacturing a semiconductor device according to the item 12, the diameter of the magnetic target is smaller than the diameter of the nonmagnetic target. 14. The method for manufacturing a semiconductor device according to the item 13, wherein the wafer processing apparatus further includes:
(X11) a first backing plate provided on the back surface of the magnetic target;
(X12) a second backing plate provided on the back surface of the nonmagnetic target;
(X13) A spacer plate provided between the nonmagnetic target and the second backing plate. In the method of manufacturing a semiconductor device according to the item 2, the evacuation system includes:
(Y1) dry pump;
(Y2) A cryopump. 16. In the method for manufacturing a semiconductor device according to the item 15, the evacuation system of the load lock chamber includes the following:
(Y3) the dry pump;
(Y4) Molecular pump. In the method of manufacturing a semiconductor device according to the item 12, the wafer processing apparatus further includes:
(X14) a third sputtering film forming region provided in the sputtering film forming chamber;
(X15) a fourth wafer stage provided in the third sputtering film forming region;
(X16) a set of third film adhesion preventing shields provided in the third sputtering film forming region;
Here, the third sputtering film forming region is for the sputtering film forming process of the second nickel film.     In the method of manufacturing a semiconductor device according to the item 9, the semiconductor device includes a power MOSFET, an IGBT, or an LDMOSFET.     In the method of manufacturing a semiconductor device according to the item 18, the first wafer stage, the second wafer stage, the third wafer stage, and the fourth wafer stage are substantially the same circle in plan view. It is on the lap.     In the method for manufacturing a semiconductor device according to the item 1, the step (b) is performed prior to the step (c).

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