JPH0465823A - Method and device for manufacturing semiconductor element - Google Patents
Method and device for manufacturing semiconductor elementInfo
- Publication number
- JPH0465823A JPH0465823A JP17737890A JP17737890A JPH0465823A JP H0465823 A JPH0465823 A JP H0465823A JP 17737890 A JP17737890 A JP 17737890A JP 17737890 A JP17737890 A JP 17737890A JP H0465823 A JPH0465823 A JP H0465823A
- Authority
- JP
- Japan
- Prior art keywords
- gas
- sputtering
- chamber
- target
- tin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 239000007789 gas Substances 0.000 claims abstract description 49
- 238000004544 sputter deposition Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 11
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract 9
- 238000005478 sputtering type Methods 0.000 claims 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 6
- 238000005546 reactive sputtering Methods 0.000 abstract description 5
- 229910052734 helium Inorganic materials 0.000 abstract description 4
- 239000001307 helium Substances 0.000 abstract description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 19
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 17
- 239000010936 titanium Substances 0.000 description 16
- 238000000151 deposition Methods 0.000 description 8
- 230000008021 deposition Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000002923 metal particle Substances 0.000 description 3
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000007872 degassing Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 238000000682 scanning probe acoustic microscopy Methods 0.000 description 1
Landscapes
- Physical Vapour Deposition (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は半導体素子における電極配線の製造方法および
その製造に関与する製造装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing electrode wiring in a semiconductor element and a manufacturing apparatus involved in the manufacturing.
(従来の技術)
半導体素子における電極配線の製造方法を第2図に主要
部分の断面図として示す。(Prior Art) A method for manufacturing electrode wiring in a semiconductor device is shown in FIG. 2 as a cross-sectional view of the main parts.
先ず(a)図に示すように、半導体基板lにトランジス
タ、キャパシタなどの素子を形成(図示せず)後、中間
絶縁膜2を形成し、所定領域にコンタクトホール3を開
孔し、第3図に示すスパッタ装置でオーミックをとるた
めのチタン(T i )4を反応性スパッタ法で厚さ約
500人、続いて配線のアルミニ1−ム(AI)6に対
する拡散バリアとして窒化チタン(TiN)5を同じく
反応性スパッタ法で厚さ約1500人堆積させる。続い
てこの基板(ウェハ)を−旦スバッタ装置から取り出し
てTiN膜5に酸素ガスを吸収させる。First, as shown in FIG. Using the sputtering equipment shown in the figure, titanium (Ti) 4 was deposited to a thickness of approximately 500 mm by reactive sputtering to obtain ohmic properties, and then titanium nitride (TiN) was deposited as a diffusion barrier for aluminum 1 (AI) 6 for wiring. 5 was also deposited to a thickness of about 1,500 layers using the reactive sputtering method. Subsequently, this substrate (wafer) is first taken out of the sputtering apparatus, and the TiN film 5 is made to absorb oxygen gas.
基板バイアスを印加しないでスパッタしたTiN膜は柱
状晶のポーラスな膜なので、大気中へ放置すると酸素ガ
スを吸蔵する性質が知られている。Since a TiN film sputtered without applying a substrate bias is a porous film with columnar crystals, it is known that it absorbs oxygen gas when left in the atmosphere.
その結果、耐熱性が向上する(酸素スタック法と呼ばれ
ている)。As a result, heat resistance improves (this is called the oxygen stack method).
次に(b)図のように、前記まで形成されたウェハを再
びスパッタ装置に装填してAI膜6を1μmの厚さ成膜
する。その後ホトリソグラフィ、エツチング技術(RI
E法)によりA16、TiN5、Ti膜4を配線パター
ンとする。Next, as shown in the figure (b), the wafer thus formed is again loaded into the sputtering apparatus to form an AI film 6 to a thickness of 1 μm. After that, photolithography, etching technology (RI
The A16, TiN5, and Ti films 4 are formed into a wiring pattern using method E).
なお、Ti膜4とTiN膜5をスパッタ法で成膜する条
件は、TiについてはDCパワー2kwスパッタ雰囲気
はArで7mTorrの圧力にして基板加熱なしで50
0人堆積させ、続いて同じTiターゲットを用いパワー
1.8kw、スパッタ雰囲気ArとN2の混合ガスにす
る。N2ガス分圧は全圧の30%(7mTorrX0.
3=2.1mTorr)にし、次にArガスを入れて7
mTorrに設定し、基板加熱しないでTiN膜を15
00人堆積させる。N2ガス分圧が全圧の25%以上で
化学量論的なTiN膜が形成されることはオージェ分光
により確かめられている。The conditions for forming the Ti film 4 and the TiN film 5 by sputtering are as follows: For Ti, the DC power is 2 kW, the sputtering atmosphere is Ar, the pressure is 7 mTorr, and the temperature is 50 mTorr without heating the substrate.
After that, using the same Ti target, the power was 1.8 kW, and the sputtering atmosphere was made into a mixed gas of Ar and N2. The N2 gas partial pressure is 30% of the total pressure (7 mTorr x 0.
3 = 2.1 mTorr), then put Ar gas and
The TiN film was heated to 15 mTorr without heating the substrate.
Deposit 00 people. It has been confirmed by Auger spectroscopy that a stoichiometric TiN film is formed when the N2 gas partial pressure is 25% or more of the total pressure.
さらにスパッタ装置(第3図)におけるTiターゲット
32とウェハ31間の距離りは通常5〜10cmに設定
されており、Arガスの圧カフmTorrの時の平均自
由行程(λ)は、λ=5.8X I O−”/P41
cmPはスパッタ圧力
であるので、L>5えとなっている。Furthermore, the distance between the Ti target 32 and the wafer 31 in the sputtering device (Fig. 3) is usually set to 5 to 10 cm, and the mean free path (λ) when the Ar gas pressure cuff is mTorr is λ = 5. .8X I O-”/P41
Since cmP is sputtering pressure, L>5.
なお第3図の従来のスパッタ装置の説明は非常に一般的
な装置の概要図であるので詳しい説明は省略する。要は
ウェハ31をスパッタする材料のターゲット32と一定
の距離をおいた位置に設置して電圧ををかけ放電するい
わゆるスパッタしてウェハ31上に必要な物質を堆積さ
せる装置である。Note that the description of the conventional sputtering apparatus shown in FIG. 3 is a schematic diagram of a very general apparatus, so detailed explanation will be omitted. In short, it is an apparatus that deposits a necessary material on the wafer 31 by so-called sputtering, which is installed at a certain distance from the target 32 of the material to be sputtered on the wafer 31 and applies a voltage to discharge the material.
(発明が解決しようとする課題) しかし、なから、前述の方法では以下の問題がある。(Problem to be solved by the invention) However, the above method has the following problems.
(1)TiNを反応性スパッタで成膜するときにArガ
スより軽いN2ガスはターゲットに付着し易い傾向があ
るので、中性のN2分子やN2イオンがTiターゲット
に衝突してターゲット表面が窒素で汚染され、そのまま
汚染されたTi膜が堆積されるのでオーミックはとれな
い。従ってその汚染されたTiターゲットを空デポジシ
ョンにより清浄化する必要がある。(1) When forming a TiN film by reactive sputtering, N2 gas, which is lighter than Ar gas, tends to adhere to the target, so neutral N2 molecules and N2 ions collide with the Ti target, causing the target surface to become nitrogen-rich. Ohmic properties cannot be achieved because the contaminated Ti film is deposited as it is. Therefore, it is necessary to clean the contaminated Ti target by empty deposition.
(2)前述したように成膜した直後のTiN膜は耐熱性
が乏しいためAI膜を堆積する前に一旦、大気中に出し
、酸素スタックしなければならないためスルーブツトが
低下する。(2) As mentioned above, since the TiN film just after being formed has poor heat resistance, it must be exposed to the atmosphere and stacked with oxygen before depositing the AI film, resulting in a decrease in throughput.
(3)通常のスパッタ装置ではターゲットとウニへ間の
間隅は平均自由行程の5倍以上離れているので、メタル
粒子同士が複数回衝突する。従ってウェハへの垂直入射
が殆どなくなり、いわゆる斜めスパッタとなるためセル
フシャドーイング効果により高アスペクト比を有するコ
ンタクトホールでのステップカバレッジが極端に低下す
る場合がある。(3) In a normal sputtering device, the distance between the target and the sea urchin is more than five times the mean free path, so the metal particles collide with each other multiple times. Therefore, there is almost no vertical incidence on the wafer, resulting in so-called oblique sputtering, so that the step coverage in a contact hole having a high aspect ratio may be extremely reduced due to the self-shadowing effect.
(課題を解決するための手段)
本発明は前述の課題、即ち(1)ターゲットの汚染、(
2)Ti、TiN%AI膜の連続スパッタ不可、(3)
コンタクトホールのステップカバレッジの不良の問題点
を解決するため以下の方法および装置を提供するもので
ある。即ち、(1)TiN膜形成時のスパッタガスとし
てHe(ヘリューム)とN、(窒素)の混合ガスを用い
ること、
(2)そのTiN膜形成直後に02ガスをスパッタした
装置に導入すること、
(3)およびターゲットとウェハの間隔を平均自由行程
(λ)の2ないし3倍にすること、を含む製造方法とし
、かつその製造装置を提供するものである。(Means for Solving the Problems) The present invention solves the above-mentioned problems, namely (1) target contamination, (
2) Continuous sputtering of Ti, TiN%AI film is not possible, (3)
In order to solve the problem of poor step coverage of contact holes, the following method and apparatus are provided. That is, (1) using a mixed gas of He (helium), N, (nitrogen) as a sputtering gas when forming the TiN film; (2) introducing 02 gas into the sputtering apparatus immediately after forming the TiN film; The present invention provides a manufacturing method including (3) and increasing the distance between the target and the wafer by two to three times the mean free path (λ), and also provides a manufacturing apparatus therefor.
(作用)
本発明は以上のような製造方法および製造装置としたた
め、TiN膜形成においてHeより重いN2ガスおよび
Tiはターゲットには付着せず基板のみに到達する傾向
となり、ターゲットへの汚染を防止することができる。(Function) Since the present invention employs the above-described manufacturing method and manufacturing apparatus, N2 gas and Ti, which are heavier than He, tend to not adhere to the target and reach only the substrate during TiN film formation, thereby preventing contamination of the target. can do.
またTiN膜形膜形真後真空らす02ガス雰囲気にさら
して酸素スタックさせるので、スループットが向上する
。In addition, since the TiN film is exposed to a vacuum 02 gas atmosphere and stacked with oxygen, the throughput is improved.
さらに、ターゲットとウェハとの間隔を短くしたのでメ
タル粒子のウェハへの垂直入射成分が多くなり、高アス
ペクト比段差でのステップカバレッジが改善される。Furthermore, since the distance between the target and the wafer is shortened, the vertical incidence component of metal particles on the wafer increases, improving step coverage at high aspect ratio steps.
(実施例)
第1図に本発明を実施する製造装置の概念図を示す。半
導体素子自身の製造工程における断面図は第2図の断面
図と同様であるので特にその図を記載することはせず、
その第2図を参考にしながら、第1図の本実施例の製造
装置を中心に製造工程を説明する。第1図の本実施例の
製造装置はその概念図であり、近年現出してきたマルチ
チャンバーと言われるシステムの一つである。即ち、半
導体素子を製造する各過程の種々のプロセス装置(第3
図と同類の)を、外気から遮断され真空度をまとめて制
御できる一つの真空装置(チャンバー)内に複数装置設
けたものである。(Example) FIG. 1 shows a conceptual diagram of a manufacturing apparatus for implementing the present invention. The cross-sectional view of the manufacturing process of the semiconductor element itself is similar to the cross-sectional view of FIG. 2, so that figure will not be particularly described.
The manufacturing process will be explained with reference to FIG. 2, focusing on the manufacturing apparatus of this embodiment shown in FIG. The manufacturing apparatus of this embodiment shown in FIG. 1 is a conceptual diagram thereof, and is one of the so-called multi-chamber systems that have appeared in recent years. That is, various process equipment (third
(similar to the one shown in the figure) are installed in a single vacuum device (chamber) that is isolated from the outside air and whose degree of vacuum can be controlled collectively.
本実施例では図に示すように、一つのチャンバー10に
、ウェハを出し入れするロードロツタ室11と後述する
種々のプロセス室12ないし15を設けた構成としであ
る。In this embodiment, as shown in the figure, one chamber 10 is provided with a load rotor chamber 11 for loading and unloading wafers, and various process chambers 12 to 15 to be described later.
真空排気系としてはチャンバ−10全体はロータリポン
プ17で真空荒引きし、クライオポンプ18で本引きす
る構成としているが、ロードロック室11とプロセス室
14は以下に述べるように別系としている。即ち、ロー
ドロック室11は前記ロークリポンプ17のみにより真
空排気する構成としており、デポジション室としてのプ
ロセス室14はターボポンプ19とロータリポンプ20
により差動排気する構成としている。つまり他のプロセ
ス室12.13.15とは別系にして真空度を独立に制
御できる機構としたものである。As for the evacuation system, the entire chamber 10 is roughly evacuated by a rotary pump 17 and main evacuated by a cryopump 18, but the load-lock chamber 11 and the process chamber 14 are separated from each other as described below. That is, the load lock chamber 11 is configured to be evacuated only by the rotary pump 17, and the process chamber 14 as a deposition chamber is evacuated by the turbo pump 19 and the rotary pump 20.
The structure is configured to perform differential pumping. In other words, it is a system that is separate from the other process chambers 12, 13, and 15, and has a mechanism in which the degree of vacuum can be controlled independently.
ガス系は図に示すように、ロードロック室11にはN2
ガス25、クリーニング室としてのプロセス室12には
Arガス26、もう一つのデポジション室としてのプロ
セス室13にはN2ガス25、Arガス26、並びにH
eガス27、さら Jにもう一つのデポジション室とし
てのプロセス室15にはArガス26を導入する機構と
しである。As shown in the figure, the gas system is equipped with N2 in the load lock chamber 11.
gas 25, Ar gas 26 in the process chamber 12 as a cleaning chamber, N2 gas 25, Ar gas 26, and H in the process chamber 13 as another deposition chamber.
A mechanism is used to introduce e gas 27 and Ar gas 26 into the process chamber 15, which serves as another deposition chamber.
そして差動排気しているプロセス室14には02ガス2
3とArガス26が圧力センサであるバラトロンセンサ
21とその制御を司るバラトロンコントローラ22で他
の室とは独立に制御されて導入出来るようにしである。02 gas 2 is placed in the process chamber 14 which is differentially pumped.
3 and Ar gas 26 can be introduced while being controlled independently from other chambers by a baratron sensor 21 which is a pressure sensor and a baratron controller 22 which controls the baratron sensor 21.
またプロセス室12.13.15への各ガス導入も図示
してないがバラトロンコントローラでガス圧を制御する
ようにしであることは言うまでもない。Although the introduction of each gas into the process chambers 12, 13, and 15 is not shown, it goes without saying that the gas pressure is controlled by a baratron controller.
加つるに、これも図示してないが、各プロセス室におけ
るターゲットとウェハとの間隔、即ち前述第3図で示し
たLを、λ=5.8XIO−3/ガス圧、で計算される
平均自白行程えの2ないし3倍、即ち2〜3cmに調整
できる機構とする。In addition, although this is also not shown, the distance between the target and the wafer in each process chamber, that is, the distance L shown in FIG. The mechanism is such that it can be adjusted to 2 to 3 times the confession distance, that is, 2 to 3 cm.
(L= (2〜3)Xλ) これは単に間隔を短(する
だけの機構であり容易に調整できる。(L=(2-3)Xλ) This is a mechanism that simply shortens the distance and can be easily adjusted.
以上述べた装置により、本実施例における電極配線部を
製造する工程を以下に記述する。The process of manufacturing the electrode wiring section in this example using the apparatus described above will be described below.
先ず第2図(a)図に示しかつ前述した工程のうちコン
タクトホール3開孔を終えたウェハをロードロック室1
1に装填し、次にクリーニング室としてのプロセス室1
2に移す。そこでベース圧をlXl0−’Torr以下
に排気(ロータリポンプ17、クライオポンプ18によ
り)した後Arガス26を導入し、ベークにより脱ガス
処理を行なう。First, the wafer shown in FIG.
1 and then process chamber 1 as a cleaning chamber.
Move to 2. Therefore, after the base pressure is evacuated to below 1X10-'Torr (by rotary pump 17 and cryopump 18), Ar gas 26 is introduced, and degassing processing is performed by baking.
次いでデポジションを行なうプロセス室13へ移送し、
Ar圧5mTorrでチタンターゲットにDC2kwを
かけ厚さ500人のチタン4を堆積させる。次いで一旦
真空引きによりlXl0−’Torr以下にしだ後N2
ガス25を導入し、全圧の30%に当たる2.1mTo
rrに調整した後、Heガス27を導入して7 m T
o r rに制御する。そしてTLツタ−ットに1.
8kwの電力を印加し、かつ基板にセルフバイアス10
0vをかけながら1500人の厚さにTiN膜5を反応
性スパッタ法で堆積させる。Next, it is transferred to the process chamber 13 where deposition is performed,
Titanium 4 was deposited to a thickness of 500 mm by applying DC 2 kW to the titanium target at an Ar pressure of 5 mTorr. Next, once the temperature was reduced to below lXl0-'Torr by evacuation, N2
Gas 25 is introduced and the pressure is 2.1 mTo, which is 30% of the total pressure.
After adjusting to rr, He gas 27 was introduced and the temperature was 7 mT.
Control to o r r. And 1 on TL.
Apply 8kw of power and self-bias 10 to the substrate.
A TiN film 5 is deposited to a thickness of 1500 mm by reactive sputtering while applying 0 V.
その後スパッタの放電を停止し、He、N2ガスを遮断
し真空引きすると同時にウェハを次のデポジションを行
なうプロセス室14に移す。そこで02ガス23を導入
、50 m T o r rの0□ガス雰囲気中に30
秒間保ってT i N膜5中に02を吸蔵させる。Thereafter, the sputtering discharge is stopped, the He and N2 gases are cut off, and the wafer is evacuated and at the same time the wafer is transferred to the process chamber 14 where the next deposition will be performed. Therefore, 02 gas 23 was introduced, and 30
This is maintained for a second to occlude 02 into the TiN film 5.
次に前記まで処理を終えたウェハを、温度150℃に保
持されたプロセス室(デポジション室)15へ移送し、
AIツタ−ットでスパッタしAl膜6を厚さ1.0μm
堆積させる。Next, the wafer that has been processed up to the above is transferred to a process chamber (deposition chamber) 15 maintained at a temperature of 150°C,
Al film 6 is sputtered with AI tutter to a thickness of 1.0 μm.
deposit
最後にロードロック室11に移し、冷却させた後N2ガ
スベント(25)によりチャンバー10より取り出す。Finally, it is transferred to the load lock chamber 11, cooled, and then taken out from the chamber 10 through the N2 gas vent (25).
以後の工程は従来同様、配線パターンを形成する。In the subsequent steps, a wiring pattern is formed in the same manner as in the conventional method.
特に記述しなかったが、このようなマルチチャンバーは
常識として外気からは遮断されており、その中でのウェ
ハの移送は全て人間が手を触れず自動的に制御される。Although not specifically described, such multi-chambers are generally isolated from the outside air, and the transfer of wafers within them is automatically controlled without human intervention.
(発明の効果)
以上説明したように本発明によれば、以下に述べるよう
な効果がある。(Effects of the Invention) As explained above, according to the present invention, there are the following effects.
(1)TiN膜形成にHeをベースにしたHeとN2混
合ガスを用いたので、Heより重いN2ガスおよびTi
はターゲットには付着せず、基板のみに到達する傾向と
なる。即ちターゲットが汚染されない。また基板バイア
スをかけていることも一層ターゲットへのN2汚染防止
に有効に働く。(1) Since a He-based mixed gas of He and N2 was used to form the TiN film, N2 gas, which is heavier than He, and Ti
tends to reach only the substrate without adhering to the target. That is, the target is not contaminated. Furthermore, applying a substrate bias also works more effectively to prevent N2 contamination on the target.
(2)TiN膜堆積後真空状態を止めず02ガス雰囲気
にさらして酸素スタックさせるので、大気中に一旦出す
よりスルーブツトが向上する。(2) After the TiN film is deposited, the vacuum state is not stopped and the film is exposed to the 02 gas atmosphere to stack oxygen, which improves the throughput compared to once exposing it to the atmosphere.
(3)ターゲットとウェハとの間隔を短くしたので、メ
タル粒子のウェハへの垂直入射成分が多くあり、高アス
ペクト比段差でのステップカバレッジが改善される。(3) Since the distance between the target and the wafer is shortened, there are many vertically incident components of metal particles to the wafer, and step coverage at high aspect ratio steps is improved.
第1図は本発明の実施例の装置の概念図、第2図は電極
配線の工程断面図、第3図は従来のスパッタ装置を示す
図である。
1・・・・・・・・基板、 2・・・・・・・・
絶縁膜、3・・・・・・・・コンタクトホール、4・・
・・・・・・Ti、 5・・・・・・・・Ti
N。
6・・・・・・−・A1. 10・・・・・・・・
チャンバー、111・・・・・・・・ロードロック室、
12.13.14.15・・・・・・・・プロセス室、
23・・・・・・・・02ガス、25−・・・−・・・
N2ガス、26・・・・・・・−Arガス、27・・・
・・・・・Heガス、31・・・・・・−・ウェハ、
32・・・・・・・・ターゲット。
電極配*の工程断面図
第2図FIG. 1 is a conceptual diagram of an apparatus according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of an electrode wiring process, and FIG. 3 is a diagram showing a conventional sputtering apparatus. 1・・・・・・・・・Substrate, 2・・・・・・・・・
Insulating film, 3...Contact hole, 4...
・・・・・・Ti, 5・・・・・・・・・Ti
N. 6・・・・・・-・A1. 10・・・・・・・・・
Chamber, 111...Loadlock chamber,
12.13.14.15... Process room,
23...02 gas, 25-...-...
N2 gas, 26...-Ar gas, 27...
...He gas, 31...Wafer,
32...Target. Figure 2: Process cross-sectional diagram of electrode arrangement*
Claims (2)
する電極配線の形成に当たって、 (a)TiN膜を形成する場合HeをベースとしたHe
とN_2の混合ガスをスパッタガスとして用いて反応性
スパッタ法で行ない、 (b)該TiN膜成膜直後に基板を大気中にさらすこと
なく、ガス雰囲気をO_2ガスに切り替えること、 (c)Ti、TiN、Alのスパッタをする際にウェハ
とターゲットの間隔を5.8×10^−^3/スパッタ
圧力=λで計算される平均自由行程の2ないし3倍に設
定すること、 を特徴とする半導体素子の製造方法。(1) When forming electrode wiring using Ti, TiN, and Al films in semiconductor devices, (a) When forming a TiN film, He-based He
(b) Immediately after forming the TiN film, the gas atmosphere is changed to O_2 gas without exposing the substrate to the atmosphere; (c) Ti , when sputtering TiN, Al, the distance between the wafer and the target is set to 2 to 3 times the mean free path calculated by 5.8 x 10^-^3/sputtering pressure = λ. A method for manufacturing a semiconductor device.
全体を外気から遮断したマルチチャンバーのシステムと
して、 (a)反応性スパッタを行なう室にAr、N_2、He
ガスを導入、これらの混合ができ、該混合ガスの圧力を
制御できること、 (b)マルチチャンバー全体のガス圧と異なる高いガス
圧を他のプロセス室とは独立に制御できる差動排気系を
有し、O_2ガスを導入できるプロセス室を設けること
、 (c)マルチチャンバー全体として少なくとも2種以上
のスパッタ用ターゲットを有すること、を特徴とする半
導体製造装置。(2) As a multi-chamber system that has multiple process chambers for semiconductor device manufacturing and is completely isolated from the outside air, (a) Ar, N_2, He,
It is possible to introduce gases, mix them, and control the pressure of the mixed gas; (b) It has a differential exhaust system that can control the high gas pressure, which is different from the gas pressure of the entire multi-chamber, independently from other process chambers. (c) The multi-chamber as a whole has at least two or more types of sputtering targets.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17737890A JPH0465823A (en) | 1990-07-06 | 1990-07-06 | Method and device for manufacturing semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17737890A JPH0465823A (en) | 1990-07-06 | 1990-07-06 | Method and device for manufacturing semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0465823A true JPH0465823A (en) | 1992-03-02 |
Family
ID=16029897
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17737890A Pending JPH0465823A (en) | 1990-07-06 | 1990-07-06 | Method and device for manufacturing semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0465823A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5346601A (en) * | 1993-05-11 | 1994-09-13 | Andrew Barada | Sputter coating collimator with integral reactive gas distribution |
US5628828A (en) * | 1994-03-04 | 1997-05-13 | Hitachi , Ltd. | Processing method and equipment for processing a semiconductor device having holder/carrier with flattened surface |
US6241857B1 (en) | 1996-11-20 | 2001-06-05 | Nec Corporation | Method of depositing film and sputtering apparatus |
US7312515B2 (en) | 2003-06-11 | 2007-12-25 | Ricoh Company, Ltd. | Semiconductor apparatus including a thin-metal-film resistor element and a method of manufacturing the same |
KR100797422B1 (en) * | 2000-09-25 | 2008-01-23 | 이비덴 가부시키가이샤 | Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board |
US7358592B2 (en) | 2004-03-02 | 2008-04-15 | Ricoh Company, Ltd. | Semiconductor device |
JP2010049017A (en) * | 2008-08-21 | 2010-03-04 | Asahi Kasei E-Materials Corp | Method for producing absorptive wire grid polarizer |
JP2011138976A (en) * | 2009-12-29 | 2011-07-14 | Renesas Electronics Corp | Method of manufacturing semiconductor device |
-
1990
- 1990-07-06 JP JP17737890A patent/JPH0465823A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5346601A (en) * | 1993-05-11 | 1994-09-13 | Andrew Barada | Sputter coating collimator with integral reactive gas distribution |
US5628828A (en) * | 1994-03-04 | 1997-05-13 | Hitachi , Ltd. | Processing method and equipment for processing a semiconductor device having holder/carrier with flattened surface |
US6241857B1 (en) | 1996-11-20 | 2001-06-05 | Nec Corporation | Method of depositing film and sputtering apparatus |
KR100797422B1 (en) * | 2000-09-25 | 2008-01-23 | 이비덴 가부시키가이샤 | Semiconductor element, method of manufacturing semiconductor element, multi-layer printed circuit board, and method of manufacturing multi-layer printed circuit board |
US7312515B2 (en) | 2003-06-11 | 2007-12-25 | Ricoh Company, Ltd. | Semiconductor apparatus including a thin-metal-film resistor element and a method of manufacturing the same |
US7718502B2 (en) | 2003-06-11 | 2010-05-18 | Ricoh Company, Ltd. | Semiconductor apparatus including a thin-metal-film resistor element and a method of manufacturing the same |
US7358592B2 (en) | 2004-03-02 | 2008-04-15 | Ricoh Company, Ltd. | Semiconductor device |
JP2010049017A (en) * | 2008-08-21 | 2010-03-04 | Asahi Kasei E-Materials Corp | Method for producing absorptive wire grid polarizer |
JP2011138976A (en) * | 2009-12-29 | 2011-07-14 | Renesas Electronics Corp | Method of manufacturing semiconductor device |
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