JPH0870069A - Semiconductor device - Google Patents

Abstract

PURPOSE: To provide a semiconductor device which is easily worked from a board material and has a heat sink of specified size. CONSTITUTION: Silver is used for a heat sink 10 for retaining a chip 2. Since the hardness of silver is low, working of silver to the size suitable to the heat sink is easily enabled by pressing. Working from plate material is easy, and a heat sink of specified size can be formed. Although the material cost of silver is higher than that of copper based material, the silver heat sink can be realized without causing cost increase, because the total cost containing working cost can be restrained low.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to an insulated gate type FET for high frequency power amplification applied to power amplification, high power switching and the like.

[0002]

2. Description of the Related Art Recently, an insulated gate FET (Field Effect Transistor) has been used as a semiconductor device for high frequency power amplification in the field of communication equipment such as a car telephone.
or) is being used. In the insulated gate FET used for such an application, a heat dissipation means for efficiently dissipating the heat generated in the semiconductor chip is indispensable for operating the device with high reliability.

The inventor of the present invention has previously disclosed a semiconductor device having a structure as shown in FIGS. 22 and 23 as a semiconductor device applied to such an application as disclosed in Japanese Patent Application No. 2-259575 (Japanese Patent Application Laid-Open No. 4-259575). 137551). 22 is a plan view showing a resin-sealed semiconductor device applied to, for example, an insulated gate FET, and FIG. 23 is a rear view of FIG.

A plurality of gate leads 83a, 8 are provided from one side of the mold resin 94 in which the semiconductor chip is sealed.
3b, 83c are drawn out, a plurality of drain leads 82a, 82b, 82c are drawn out from the other side surface, and a plurality of source leads 84 are drawn from the other side surface.
a and 84b are pulled out. On the other hand, a heat sink 85 made of a copper-based material (for example, copper-tungsten alloy) having excellent thermal conductivity is used, in which a semiconductor chip is fixed via a brazing material such as gold-silicon eutectic alloy and acts as a heat radiating means. , As shown in FIG. 23, this heat sink 8
5 is surrounded by a mold resin 94, and only the tip end portion to be mounted on the mounting board is exposed.

As described above, the semiconductor chip is supported by the heat sink 85 made of a copper-based material having excellent thermal conductivity, and the exposed surface of the tip end of the heat sink 85 is mounted on the mounting board by soldering, whereby the semiconductor chip is mounted. The heat generated in 1 is efficiently radiated by the heat sink 85.

Further, by exposing only the tip portion which is the mounting surface of the heat sink 85, when soldering to the mounting substrate, the solder abnormally sucks up the side surface of the heat sink 85 and a short circuit defect (for example, between the source and the gate) occurs. Can be prevented.

[0007]

As described above, when the semiconductor chip is supported by the heat sink 85 made of a copper-based material having excellent thermal conductivity, the heat sink 85 as a component is previously pressed by using a copper-based plate material. Although it is processed into a predetermined size, there is a problem that it is not easy to form into a size suitable for a heat sink of a semiconductor device by this press working.

That is, the size of the heat sink of the semiconductor device is small when viewed as a general pressing target, and a certain thickness is required for the heat sink. It has been difficult to process such materials using system materials to meet such requirements.
For this reason, it is often done by a method such as shaving, but since this processing method is troublesome, an increase in cost is inevitable.

Further, like the conventional semiconductor device, the periphery of the heat sink 85 is surrounded by the mold resin 94,
When the structure is such that only the tip part to be mounted on the mounting board is exposed, thermal stress occurs along with this because it is repeatedly turned on and off during element operation after mounting,
This thermal stress concentrates on the end of the heat sink 85. As a result, there is a problem that solder peeling easily occurs at the end of the heat sink 85.

An object of the present invention is to provide a semiconductor device having a heat sink of a predetermined size which can be easily processed from a plate material.

Another object of the present invention is to provide a semiconductor device which prevents peeling of solder at the end of a heat sink surrounded by a mold resin.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

(1) In the semiconductor device of the present invention, a semiconductor chip provided with a plurality of electrode pads, a heat sink to which the semiconductor chip is fixed via a brazing material, and a plurality of semiconductor chips arranged around the semiconductor chip. In a semiconductor device having a bonding wire connected between the lead and the electrode pad, the semiconductor chip, a heat sink, a mold resin for sealing a part of the lead and the bonding wire, the heat sink is made of silver, The mounting portion of the silver heat sink is exposed from the mold resin.

(2) According to another semiconductor device of the present invention, a semiconductor chip provided with a plurality of electrode pads, and a heat sink to which the semiconductor chip is fixed via a brazing material,
A semiconductor device having a bonding wire connected between a plurality of leads arranged around a semiconductor chip and the electrode pad, and a mold resin for sealing the semiconductor chip, the heat sink, a part of the lead and the bonding wire. In the above, the mounting portion of the heat sink is exposed from the mold resin, and a concave portion is provided along the boundary portion at or near the boundary portion of the exposed surface of the heat sink with the mold resin.

[0016]

According to the above-mentioned means (1), the semiconductor device of the present invention includes a semiconductor chip provided with a plurality of electrode pads, a heat sink to which the semiconductor chip is fixed via a brazing material, and a semiconductor. In a semiconductor device having a bonding wire connected between a plurality of leads arranged around a chip and the electrode pad, and a semiconductor chip, a heat sink, a part of the lead and a mold resin for sealing the bonding wire. Since the heat sink is made of silver, and the mounting portion of the heat sink made of silver is exposed from the mold resin, it is easy to process from a plate material based on the material of silver and a heat sink of a predetermined size can be provided. .

According to the above-mentioned means (2), another semiconductor device of the present invention is a semiconductor chip provided with a plurality of electrode pads, and a heat sink to which the semiconductor chip is fixed via a brazing material. A semiconductor having a bonding wire connected between a plurality of leads arranged around a semiconductor chip and the electrode pad, and a mold resin for sealing the semiconductor chip, a heat sink, a part of the lead and the bonding wire In the device, a mounting portion of the heat sink is exposed from the mold resin, and a concave portion is provided along the boundary portion at or near a boundary portion between the exposed surface of the heat sink and the mold resin. Therefore, since the thermal stress is dispersed in the depth direction by the concave portion, the heat enclosed by the mold resin is It is possible to prevent the solder separation at the sink end.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a plan view showing a semiconductor device according to Embodiment 1 of the present invention, which is an example applied to an insulated gate FET. 2 is a sectional view taken along the line AA of FIG. 1, FIG. 3 is a sectional view taken along the line BB of FIG. 1, and FIG. 4 is a rear view of FIG.
FIG. 5 is a plan view showing a structure obtained by removing the mold resin from FIG. 1, FIG. 6 is a plan view showing a semiconductor chip used in an insulated gate FET, and FIG. 7 is an insulated gate type F shown in FIG.
FIG. 8 is an enlarged sectional view showing a portion A which is a main part of the ET chip, and FIG. 8 is a perspective view of FIG. 7.

On the long side of the surface of a rectangular insulated gate FET chip (hereinafter simply referred to as a chip) 2 made of silicon, which constitutes the insulated gate FET 1, FIG.
As shown in FIG. 5, a plurality of gate electrode pads 4a to 4g and a plurality of drain electrode pads 6a to 6g are provided to face each other. The number of each electrode pad is shown as an example in which seven electrodes are provided. The chip 2 has a size of 1.2 mm × 2.0 mm, for example.

The cross section of the chip 2 is, as shown in FIG.
The P + layer 3A, the P− layer 3B formed on the P + layer 3A, and the pair of N + layers 3C and 3C selectively formed on the P− layer 3B.
D and N formed in contact with each of the N + layers 3C and 3D
The layers 3E and N− layer 3F, the P layer 3G formed so as to be in contact with the N− layer 3E and N− layer 3F, and the P + layer 3 on the P− layer 3B.
And a P + layer 3H formed so as to reach A. Here, one of the N + layer 3C and the N layer 3E is F
It constitutes the source region of ET and the other N + layers 3D and N-
The layer 3F constitutes the drain region, and includes the N layer 3E and the N− layer 3F.
A channel is formed in the P layer 3G on the surface between them.

The surface of the chip 2 is, for example, an oxide film (Si
O ₂ ), which is covered with an insulating film 8 and is not covered with the insulating film 8, one N + layer 3C and the other N + layer 3D are each formed of, for example, aluminum so as to extend onto the insulating film 8. The source electrode 5 and the drain electrode 6 are formed. Further, in the insulating film 8 immediately above the surface of the P layer 3G where the channel is to be formed, the gate electrode 4 is formed from a low resistance material such as polycrystalline silicon or molybdenum.

Here, in particular, one end of the source electrode 5 is P +
It is formed so as to be in contact with the layer 3H, so that the drain electrode 6 and the source electrode 5 through the channel during operation of the device
The current path to reach the chip 2 as shown by the arrow in FIG.
Is configured to face the back side of. Note that the P + layer 3H is not shown in FIG.

The FET chip 2 is formed by successively forming a plurality of cells adjacent to each other with one cell having such a structure as a unit. The size L of one cell shown in FIG. 7 is, for example, 15 to 20 μm.
Is set to The gate electrode 4 and the drain electrode 6 formed on each cell are formed on the chip 2 as shown in FIG.
Electrode pads 4a for a plurality of gates drawn around the
Through 4g and the electrode pads 6a through 6g for the drain are electrically connected. The source electrode 5 is pulled out to the back surface of the chip 2 and electrically connected to the heat sink as described later.

The chip 2 is, as shown in FIGS. 2 and 3,
It is fixed to a heat sink 10 made of rectangular silver through a gold-silicon eutectic alloy 9 which is a brazing material. As shown in FIG. 5, the heat sink 10 is supported on both short sides by a pair of heat sink suspension leads 11a and 11b made of, for example, an iron-nickel alloy material via an adhesive such as silver solder. The heat sink 10 is formed in advance into a predetermined size by press working using a silver plate material. The size of the heat sink 10 is 1.5 as an example.
A device having a size of mm × 3.4 mm × 1.5 mm (thickness) is used.

Also, on both long sides of the chip 2 fixed to the heat sink 10, a plurality of gate leads 12a, 12b, 12c integrated by a tie bar 12 made of, for example, an iron-nickel alloy material are also provided, and the tie bar is similarly formed. Thirteen
Drain leads 13a, 1 integrated by
3b and 13c are arranged. Between the plurality of gate electrode pads 4a to 4g on the surface of the chip 2 and the gate tie bar 12, and the plurality of drain electrode pads 6
A wire 14 such as a gold wire is bonded between a to 6 g and the tie bar 13 for drain.

Then, the chip 2, the heat sink 10, the bond wire 14 and the gate leads 12a to 12 are formed.
c and a part of the drain leads 13a to 13c are sealed by the mold resin 15. However, only the mounting portion 10A of the heat sink 10 is exposed from the mold resin 15.

Next, a method of manufacturing the insulated gate FET 1 of this embodiment will be described.

First, as shown in FIG. 9, a lead frame 16 made of, for example, an iron-nickel alloy material, which has been processed into a desired pattern by pressing, etching, or the like, is prepared. As described above, the lead frame 16 includes a pair of heat sink suspension leads 11 a and 11 b and a plurality of gate leads 12 integrated by a tie bar 12.
A large number of sets are formed along the length direction X, with a set of a, 12b, 12c and a plurality of drain leads 13a, 13b, 13c integrated by the tie bar 13. In addition, 3 is a positioning hole.

Next, as shown in FIG. 10, a pair of heat sink suspension leads 11a and 11b is formed by using a heat sink 10 formed in advance into a predetermined size by press working.
The both short sides are fixed to each other via an adhesive such as silver wax.
Then, the surface of each lead is plated with gold.

Subsequently, as shown in FIG. 11, the chip 2 made of silicon is fixed to the surface of the heat sink 10 by the gold-silicon eutectic alloy 9. The chip attachment using the gold-silicon eutectic alloy 9 is performed in advance with the heat sink 10.
Gold is partially or entirely plated with gold to a thickness of about 5 μm on the chip-attaching surface, or a gold foil with a thickness of about 10 μm is interposed between the heat sink 10 and the chip 2, Heat chip 2 to about 430 ° C for several 100μ
Do this by giving m scrubs. As a result, the source electrode 5 of the FET is electrically connected to the heat sink 10.

Next, as shown in FIG. 12, between the plurality of gate electrode pads 4a to 4g and the gate tie bar 12 on the surface of the chip 2, and the plurality of drain electrode pads 6a to 6g. Bonding is performed between the drain tie bar 13 and the drain tie bar 13 by a nail head bonding method using a wire 14 such as a gold wire.

Subsequently, as shown in FIG. 13, a lead frame 16 to which the chip 2 and the heat sink 10 are fixedly attached.
Is set between the upper mold 17 and the lower mold 18 of the transfer mold device, and the gate 19 provided on the upper mold 17 is set.
The resin is poured into the cavity 20 from. The tip of the gate 19 is formed narrow so as to easily remove a resin burr later. In this case, the resin is set so as not to adhere to the mounting portion 10A of the heat sink 10.

As a result, as shown in FIG. 14, in the lead frame 16, the chip 2, the heat sink 10,
Bonding wire 14 and gate leads 12a to 12
c and a part of the drain leads 13a to 13c are sealed by the mold resin 15. However, heat sink 1
Only the mounting portion 10A of 0 is exposed from the mold resin 15.

Next, after removing the resin burr 7 in the shaded portion in FIG. 14 by pressing and liquid honing, the lead frame 16 is cut along the broken line to form the insulated gate type as shown in FIG. FET1 is obtained by being separated individually. Subsequently, the characteristics of each FET 1 are measured and selected, and after marking is performed, the gate leads 12 a to 12 c and the drain leads 13 a to 13 are selected.
c is modified as shown in FIG. 2 to be suitable for mounting. Next, after a final inspection, the product is shipped to customers such as set makers.

Insulated gate type FE thus obtained
When the T1 is used in the field of communication equipment such as a car telephone, it is mounted on the module 21 as shown in FIG.
That is, the mounting portion 10 </ b> A of the heat sink 10 of the chip 2 is connected via the solder 24 to the header 22 made of copper, which is plated with the conductive layer 23 having excellent solder wettability such as nickel layer on both surfaces.

On the other hand, a ceramic substrate 26 having a strip line 25 formed on the surface thereof is arranged on the header 22. The strip line 25 is connected with the gate leads 12a to 12c via solder 24 and the drain. The leads 13a to 13c are connected. Since the heat sink 10 is made of silver, good soldering is performed. Similarly, since the surfaces of the gate leads 12a to 12c and the drain leads 13a to 13c are plated with gold, good soldering is performed. . Further, other chip parts (not shown) such as capacitors and resistors are mounted on other parts of the ceramic substrate 26.

According to the first embodiment, the following effects can be obtained.

(1) Heat sink 1 supporting chip 2
Since silver is used as 0, since silver has a low hardness, it is easy to process it into a size suitable for a heat sink by pressing, and it is easy to process from a plate material and a heat sink of a predetermined size can be provided. it can. Even if the material cost of silver is higher than that of the copper-based material, the total cost including the processing cost can be kept low, so that it can be realized without increasing the cost.

(2) Since the heat sink 10 made of silver has a low electric resistance, it is possible to reduce the operating resistance and also the thermal resistance.

(Embodiment 2) FIG. 16 is a rear view showing a semiconductor device according to a second embodiment of the present invention, and FIG.
FIG. Insulated gate type FET in Example 1
In the boundary portion between the mounting portion 10A of the heat sink 10 exposed from the first mold resin 15 and the mold resin 15, a recess 27 is formed in a frame shape along the boundary portion. The recess 27 is formed at the same time when the heat sink 10 is pressed from a plate material.

According to the second embodiment, the following effects can be obtained.

Since the concave portion 27 is formed in the boundary portion between the mounting portion 10A of the heat sink 10 and the mold resin 15, even if thermal stress occurs due to repeated ON / OFF during element operation after mounting, this Since the thermal stress is dispersed in the depth direction by the recess 27, the thermal stress does not concentrate on the end of the heat sink 10. Therefore, peeling of the solder at the end of the heat sink 10 can be prevented.

(Embodiment 3) FIG. 18 is a rear view showing a semiconductor device according to Embodiment 3 of the present invention, and FIG.
FIG. Insulated gate type FET in Example 1
In the boundary portion of the mounting portion 10A of the heat sink 10 exposed from the first mold resin 15 with the mold resin 15, recesses 27 are formed in a grid pattern over the mold resin 15. The recess 27 is formed by grinding the mounting portion 10A of the heat sink 10 after the resin molding is completed.

In the third embodiment, the second embodiment is also used.
Except that the means for forming the recess 27 is different from
Since it has the same structure, the same effect as the second embodiment can be obtained.

(Embodiment 4) FIG. 20 is a rear view showing a semiconductor device according to Embodiment 4 of the present invention, and FIG.
FIG. Insulated gate type FET in Example 1
In the boundary portion between the mounting portion 10A of the heat sink 10 exposed from the first mold resin 15 and the mold resin 15, concave portions 27 are discontinuously formed along the boundary portion. After the resin molding is completed, the recess 27 is
The mounting portion 10A of the heat sink 10 is formed by partially grinding.

Also in the fourth embodiment, the second embodiment is also used.
Except that the formation position of the recess 27 is different from
Since it has the same structure, the same effect as the second embodiment can be obtained.

As described above, the invention made by the present inventor is
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

For example, in the above-mentioned embodiment, an example of forming a semiconductor device by using an insulated gate FET chip made of silicon has been described, but the same applies to the case where a chip made of gallium-arsenic other than silicon is used. be able to. However, when the chip made of gallium-arsenic is fixed to the heat sink, the gold-silicon eutectic alloy as described above is not suitable as the brazing material, and therefore it is desirable to use the gold-germanium eutectic alloy instead. Alternatively,
A gold-tin eutectic alloy may be used, and these brazing materials can be applied to silicon.

Further, it can be applied to a vertical type insulated gate FET, and further applied to a bipolar semiconductor device.

Further, the concave portion formed in the mounting portion of the heat sink is not limited to the boundary portion with the mold resin,
You may form in the vicinity of this boundary part.

Furthermore, although an example in which gold is plated on a plurality of gate leads and drain leads has been described, solder is not limited to gold and may be plated.

In the above description, the case where the invention made by the present inventor is mainly applied to the manufacturing technology of a semiconductor device which is the field of application which is the background of the invention has been described, but the invention is not limited thereto. The present invention is applicable at least under the condition that the heat generated in the semiconductor chip is radiated by the heat sink.

[0054]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

Since silver is used as the heat sink for supporting the chip, it is possible to provide a heat sink of a predetermined size which can be easily processed from the plate material based on the material of silver.

Since the concave portion is formed in the mounting portion of the heat sink, even if thermal stress is generated by repeatedly turning on and off during operation of the element after mounting, the thermal stress is generated by the concave portion in the depth direction. Since it is dispersed, the thermal stress does not concentrate on the end of the heat sink, and the peeling of the solder at the end of the heat sink can be prevented.

[Brief description of drawings]

FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a sectional view taken along line BB of FIG. 1;

FIG. 4 is a rear view of FIG.

FIG. 5 is a plan view showing a structure in which the mold resin is removed from FIG.

FIG. 6 is a plan view showing a semiconductor chip used in the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is an enlarged cross-sectional view showing a portion A of FIG.

FIG. 8 is a perspective view of FIG. 7.

FIG. 9 is a plan view showing a lead frame used for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 11 is a cross-sectional view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 12 is a plan view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 13 is a cross-sectional view showing another process of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 14 is a plan view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 15 is a sectional view showing an example in which the semiconductor device according to the first embodiment of the present invention is mounted on a module.

FIG. 16 is a rear view showing a semiconductor device according to a second embodiment of the present invention.

17 is a cross-sectional view taken along the line AA of FIG.

FIG. 18 is a rear view showing a semiconductor device according to a third embodiment of the present invention.

19 is a cross-sectional view taken along the line AA of FIG.

FIG. 20 is a rear view showing a semiconductor device according to a fourth embodiment of the present invention.

21 is a cross-sectional view taken along the line AA of FIG.

FIG. 22 is a plan view showing a conventional example.

FIG. 23 is a rear view of FIG. 22.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Insulated gate type FET, 2 ... Semiconductor chip, 3 ... Positioning hole, 4 ... Gate electrode, 4a-4g ... Gate electrode pad, 5 ... Source electrode, 6 ... Drain electrode, 6a
To 6 g ... electrode pad for drain, 7 ... resin burr,
8 ... Insulating film, 9 ... Gold-silicon eutectic alloy, 10 ... Silver heat sink, 10A ... Silver heat sink mounting portion, 1
1 ... Heat sink suspension lead, 12a to 12c ... Gate lead, 13a to 13c ... Drain lead, 14 ...
Bonding wire, 15 ... Mold resin, 16 ... Lead frame, 17 ... Upper mold, 18 ... Lower mold, 19 ... Gate, 20 ... Cavity, 21 ... Module, 22 ... Header, 23 ... Conductive layer, 24 ... Solder, 25 ... Strip line, 26 ... Ceramic substrate, 27 ... Recessed portion of silver heat sink mounting portion.

Claims (7)

[Claims] 1. A semiconductor chip having a plurality of electrode pads, a heat sink to which the semiconductor chip is fixed via a brazing material, a plurality of leads arranged around the semiconductor chip, and the electrode pad. A bonding wire connected between the semiconductor chip, the heat sink,
In a semiconductor device having a part of leads and a mold resin for sealing a bonding wire, the heat sink is made of silver, and a mounting part of the silver heat sink is exposed from the mold resin. . 2. A semiconductor chip provided with a plurality of electrode pads, a heat sink to which the semiconductor chip is fixed via a brazing material, a plurality of leads arranged around the semiconductor chip, and the electrode pad. A bonding wire connected between the semiconductor chip, the heat sink,
In a semiconductor device having a part of leads and a mold resin for sealing a bonding wire, a mounting part of the heat sink is exposed from the mold resin, and an exposed surface of the heat sink is a boundary part with the mold resin or this. A semiconductor device, wherein a recess is provided along the boundary near the boundary. 3. The semiconductor device according to claim 2, wherein the heat sink is made of silver. 4. The semiconductor chip is an insulated gate FET
It consists of a chip, Claim 1 thru / or Claim 3 characterized by the above-mentioned.
The semiconductor device according to claim 1. 5. The semiconductor device according to claim 1, wherein the brazing material is made of a gold-silicon eutectic alloy. 6. The semiconductor device according to claim 1, wherein the brazing material is made of a gold-germanium eutectic alloy. 7. The semiconductor device according to claim 1, wherein the brazing material is made of a gold-germanium eutectic alloy.