JPS6271256A - Compound semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain an MMIC in high yield with good reproducibility without short-circuiting between electrodes even if air bridge electrodes are deformed in an assembling process by extending part of an insulating film which forms a capacitor of a passive element on gate and drain electrodes under space wirings. CONSTITUTION:In a compound semiconductor integrated circuit having a plurality of sets of electrodes of FETs are provided, and FET n which air bridge electrodes 123s, 123s,... are connected between source electrodes 103s, 103s,..., and a passive element having an insulating film which forms a capacitor on the same substrate as the FETs, parts of the insulating film 11 for forming the capacitor of the passive element are extended on gate electrodes 113g, 113g,.., drain electrodes 113d, 113d,.. under the air bridge electrode. Thus, even if the air bridge electrodes are deformed, a shortchicuit with the other electrode does not occur, the electrodes can be formed in good reproducibility without complicating the steps.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in the structure of a monolithic microwave integrated circuit (abbreviated as MMIC) using a compound semiconductor.

[Technical background of the invention and its problems]

An MMIC using gallium arsenide (GaAs), particularly an MMIC for power amplification using a field effect transistor (abbreviated as FET) as an active element, will be described below. This power amplification MMIC consists of an FET, a matching circuit section for impedance matching, and a power supply circuit section, and has a large chip size. Improving MMIC yield is important because as chip size increases, the total number of chips per wafer decreases. Needless to say, as a factor for improving the yield of the MMIC, it is necessary to improve the yield of FETs as active elements.

FIG. 3 is a cross-sectional view of an example of a conventional FET in which via holes are used to ground a plurality of source electrodes. In the figure, 100 is a GaAs semi-insulating substrate, 101 is an active layer (N
M), 102 is an ohmic contact layer (N+ layer), 103s is a source electrode, 103g is a gate electrode, 103d is a drain electrode, and 104 is a via hole. FE like this
Since the electrodes of T are closely arranged, it is very difficult to process via holes for grounding the plurality of source electrodes 103s, 103g, etc., resulting in a significant decrease in yield. It is also conceivable to widen the widths of the plurality of source electrodes in the active layer region in order to facilitate via hole processing, but this increases the chip area and becomes an obstacle to improving the integration density.

Next, the MMIC shown in FIG. 4 has a feature in which a plurality of source electrodes are bridged by a metal layer using a space wiring (air bridge) method which is advantageous for improving integration density. In FIG. 4, 110 is a GaAs semi-insulating substrate, 111 is an active layer (
N layer), 112 is an ohmic contact layer (N layer), 113s
113g is a gate electrode, 113d is a drain electrode, and 114 is an insulating film made of, for example, SiO□.

5L3N4.123s is a space electrode (air bridge electrode) that bridges the source electrodes, 115a is a capacitor base electrode, and 115b is a capacitor top electrode that faces the capacitor base electrode via an insulating layer. Each electrode formed in this way has a wiring pattern formed of a metal layer on a pad electrode provided at the periphery (none of these are shown).
It is derived by

The FET section to be taken up is formed as follows. First, after forming a gate electrode 113g, an insulating film 11 is formed on the entire surface of the wafer.
4 is deposited, and openings are formed in predetermined areas of this insulating film by photolithography. Next, electrode metal is deposited to form a source electrode 113s and a drain electrode 113d, which are ohmically connected in the openings. Further, during the metal vapor deposition, the metal layer deposited through a photoresist film (not shown) provided in the insulating film for forming the openings is simultaneously removed by photoresist film dissolution (so-called lift-off). The drain electrode 113d is formed in a comb shape, and the source electrode 113s is formed in an island shape. Furthermore, source electrode 1
13g.

The air bridge electrode 123s connecting to the electrodes 113s and bridging the air bridge electrodes 123s is formed by pattern plating.

According to the report, since there is no insulating film on the drain electrode 113d, the air bridge electrode 123s may be deformed by some chance during the manufacturing process, causing a short circuit between the source and drain electrodes as shown in FIG. This can lead to serious accidents. As a countermeasure against this, it is possible to add a new layer of second insulating protection 5124 to the entire surface as shown in FIG. 6, and to provide an opening only on the source electrode 113s, but the process is complicated. It is difficult to completely remove the protective film within the opening, and if this is insufficient, there are problems such as poor connection of the air bridge electrode.

[Purpose of the invention]

The present invention aims to improve the above-mentioned conventional problems and improve the integration density and yield of FETs provided in the air bridge electrode of an MMIC.

[Summary of the invention]

In the compound semiconductor integrated circuit according to the present invention, a plurality of sets of each electrode of the FET are provided, and a source electrode (103g) is provided.

103s...) between air bridge electrodes (123s,
123s...) and a passive element having an insulating film forming a capacitor on the same substrate, a part of the insulating film (11) forming the capacitor of the passive element. are the gate electrode (113g, 113g...) under the air bridge electrode, and the drain electrode (113d).

113d...).

According to the present invention, even if the air bridge electrode is deformed, short circuits with other electrodes do not occur, and manufacturing can be achieved with high yield and good reproducibility, and the manufacturing process is not complicated.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be explained with reference to FIG. 1 and further with reference to FIG. 2 showing the main part of the manufacturing process.

In addition, in the description, parts that are the same as before are indicated with the same reference numerals in the drawings.

The explanation will be omitted.

As shown in FIG. 1, the MMIC according to the present invention has a base electrode 115a in one capacitor of a passive element.
The insulating film 11 between the upper surface electrode 115b and the gate electrode 113gt is provided below the space wiring 123s of the FET via the resistive layer electrodes 116a, 116b, etc.
It has a structural feature extending over the drain electrode 113d. With this structure, it is possible to completely prevent the air bridge electrode from coming into contact with the drain electrode below it.

Next, a method of manufacturing the above structure will be explained with reference to FIG.

First, an acceleration energy of 140 keV and a dose of 3XIO"c were applied to the area where the active layer (N layer) 111 and the resistance layer 121 were to be formed on one main surface of the GaAs semi-insulating substrate 110.
m″″! Next, Si ions are selectively implanted into the area where the ohmic contact layer (N layer) 112 is to be formed at acceleration energies of 120 keV and 250 keV and a dose of 2XIOi.
Selectively implant 81 ions of 3 cm-” followed by 81 ions.
Annealing is performed at 50° C. to activate Si ions to form the active layer 111. Resistive layer 121° and ohmic contact layer 11
2 (Figure a).

Next, on the ohmic contact layer 112 and the resistance layer 121
Patterning for each electrode of the source, drain, and resistance layer is performed by photolithography, and an AuGa layer is deposited thereon. Subsequently, after performing lift-off to form each electrode pattern, 4
Heat to 50°C to form an alloy. Furthermore, Ti/Pt/Au were formed to have a thickness of 1,000 layers, 1,000 layers, and 7,000 layers, respectively, by the lift-off method to form a source electrode 113g.

Drain electrode L13d, resistance layer electrode 116a, 116
Next, the gate electrode and the capacitor base electrode are patterned by photolithography, AQ is deposited, and the gate electrode 113g and the capacitor base electrode 115a are formed by lift-off (FIG. 2B).

Next, an insulating film (S13N4) was coated with plasma C to protect the electrodes of the gate, drain, and resistance layer, and for the capacitor.
After depositing the material to a thickness of 2,000 yen by the VD method, the insulation l111 on the source electrode 113s is formed by photolithography and plasma etching using Freon gas (CF).
Drill a hole in 1 (Figure c).

Next, an air bridge electrode for connecting the source electrode and an electrode on the top surface of the capacitor were patterned by photolithography, and Ti was deposited to a thickness of 2000 mm by vapor deposition, and Au was plated to a thickness of 3 μm to form a source electrode 113 g.
An air bridge electrode 123g for connection between L3s... and a capacitor upper surface electrode 115b are provided to form the MMIC shown in FIG.

Since the insulating film 11 covers the drain electrode 113d as shown above, even if the air bridge electrode is deformed, no short circuit will occur between the source and drain electrodes.
Gate electrode with one insulating film deposition.

Since the protective film of the drain electrode and the insulating film of the capacitor are formed, there is an advantage that the process does not become complicated.

It should be noted that the thickness of the insulating film of 2,000 layers as described in the above embodiment is not limited to this, but may be deposited to such an extent that short circuits do not occur or the yield of capacitors does not decrease. Further, although Si and N layers are illustrated as examples of the insulating film, the present invention is not limited to these, and silicon oxide films (SiOz), phosphorus-doped oxide films (PSG), etc. may also be used.

〔Effect of the invention〕

According to this invention, as described above, since the drain electrode is covered with an insulating film, even if the air bridge electrode for connection between the source electrodes is deformed during the assembly process, there will be no short circuit between the two electrodes, and the MMIC can be manufactured with high yield and good reproducibility.

Furthermore, since the insulating film of the drain electrode is formed simultaneously with the insulating film of the capacitor and the insulating film of the gate electrode, there is a remarkable advantage that the manufacturing process is not complicated.

[Brief explanation of drawings]

Both FIGS. 1 and 2 show an MMTC according to an embodiment of the present invention, FIG. 1 is a sectional view, and FIGS. 2 a-c.
1 is a cross-sectional view showing a main part of the manufacturing process, and FIGS. 3 to 6 are cross-sectional views for explaining the main part of a conventional MMIC. 11 --- Insulating film 110 --- GaAs semi-insulating substrate 111 --
---One action layer (N layer) 112 ---Ohmic contact layer (N layer) 113g
---------Source electrode 113d-----Drain electrode L13g-----Gate electrodes 115a, 115b----Capacitor (base,
Top surface) Electrodes 116a, 116b----One resistance layer electrode 121---One resistance layer

Claims (1)

[Claims] A compound formed of a field effect transistor section in which a plurality of sets of each electrode of a field effect transistor are provided, a source electrode is connected by a space wiring, and a passive element having an insulating film constituting a capacitor on the same substrate. A compound semiconductor integrated circuit characterized in that a part of an insulating film constituting a capacitor of a passive element extends over a gate and drain electrode below a space wiring.