JPH0330432A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0330432A JPH0330432A JP16403889A JP16403889A JPH0330432A JP H0330432 A JPH0330432 A JP H0330432A JP 16403889 A JP16403889 A JP 16403889A JP 16403889 A JP16403889 A JP 16403889A JP H0330432 A JPH0330432 A JP H0330432A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- sidewall
- film
- gate electrode
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- 230000003647 oxidation Effects 0.000 claims abstract description 16
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims abstract description 5
- 239000004020 conductor Substances 0.000 claims abstract 4
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 7
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 5
- 230000001590 oxidative effect Effects 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 3
- 230000003014 reinforcing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、サイドウオールに導電性を持たせゲートに接
続した構造のＬＤＤ型ＭＯ３ＦＩＥＴの製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing an LDD type MO3FIET having a structure in which sidewalls are made conductive and connected to a gate.
従来の装置は、特開昭６１−２６０６７７号公報に記載
のように、ゲート電極形成後、直ちに導電性を持つサイ
ドウオールの形成工程を行なっていた。In the conventional apparatus, as described in Japanese Unexamined Patent Publication No. 61-260677, a step of forming a conductive sidewall was performed immediately after forming the gate electrode.
上記従来技術は、ゲート電極加工時にサイドウオール下
の酸化膜が受けるエツチングダメージや膜厚の目減りに
ついて配慮がされておらず、サイドウオールに導電性を
持たせた構造の場合、ゲート耐圧不良を招くという問題
があった。The above conventional technology does not take into account etching damage or loss of film thickness that is caused to the oxide film under the sidewall during gate electrode processing, and in the case of a structure in which the sidewall is made conductive, it may lead to poor gate breakdown voltage. There was a problem.
本発明は、ゲート側壁を酸化せずにサイドウオール下の
酸化膜を補強し、良好なゲート耐圧が得られる、導電性
を持つサイドウオールをゲート電極に接続した構造のＬ
ＤＤ型ＭＯ５ＦＥＴの製造方法を提供することを目的と
する。The present invention provides an L structure in which a conductive sidewall is connected to a gate electrode, which strengthens the oxide film under the sidewall without oxidizing the gate sidewall, and provides good gate breakdown voltage.
An object of the present invention is to provide a method for manufacturing a DD-type MO5FET.
上記目的を達成するために、ゲート電極を加工後ゲート
側壁部に耐酸化性膜を形成し、半導体基板表面を酸化し
、その後導電性を持つサイドウオ−ルを形成したもので
ある。To achieve the above object, after processing the gate electrode, an oxidation-resistant film is formed on the sidewalls of the gate, the surface of the semiconductor substrate is oxidized, and then conductive sidewalls are formed.
ゲート側壁に形成した耐酸化性膜は、半導体基板表面を
酸化する時、マスクとして作用する為ゲート側壁は酸化
されず、導電性のサイドウオールとゲート電極を接続す
ることができる。一方、サイドウオール下の酸化膜は酸
化工程によって補強される為、ゲート耐圧不良を起こす
ことがない。The oxidation-resistant film formed on the gate sidewall acts as a mask when the semiconductor substrate surface is oxidized, so the gate sidewall is not oxidized and the conductive sidewall and gate electrode can be connected. On the other hand, since the oxide film under the sidewall is reinforced by the oxidation process, gate breakdown voltage failures do not occur.
以下、本発明の一実施例を第１図〜第４図により説明す
る。まず、第１図に示す様にＰ型Ｓｉ基板７にゲート酸
化膜１を形成後、ポリＳｉ２゜ＣＶＤ５ｉＯｚ３を堆積
、加工してゲート電極を形成する。次にＣＶＤ５ｉａＮ
４ｔｌＡを堆積し、異方性エツチングを行なってゲート
側壁にのみ５ｉａＮ４膜４を形成する０次に熱酸化を行
って第２図に示す様にゲート酸化膜を補強する。この際
、−度ゲート電極下以外のゲート酸化膜を除去してから
酸化を行なっても良い０次に、熱リン酸処理を行ない５
ｉａＮａ膜４を除去し、第３図に示す様に薄い酸化膜５
を形成する。次にイオン打ち込みによって低濃度ドレイ
ン（ｎ−）層８を形成し、第４図に示す様にポリＳｉを
堆積し、異方性エツチングを行なってサイドウオール６
を形成する。次に、イオン打ち込みによって高濃度ドレ
イン（ｎ＋）層９を形成する。このとき、サイドウオー
ル６にもイオン打ち込みが行なわれるため導電性膜とな
る。以下、パッシベーション膜の形成、配線工程を行な
って導電性のサイドウオールを薄い抵抗を介してゲート
電極に接続した構造のＬＤＤ型ＭＯＳＦＥＴを得る。本
製造方法によれば、ゲート電極加工時に起こるサイドウ
オール下のゲート酸化膜のエツチングダメージや、酸化
膜厚の目減りを酸化工程により回復、補強できるため、
ゲート耐圧不良を起こすことが無い。An embodiment of the present invention will be described below with reference to FIGS. 1 to 4. First, as shown in FIG. 1, a gate oxide film 1 is formed on a P-type Si substrate 7, and then poly-Si2°CVD5iOz3 is deposited and processed to form a gate electrode. Next CVD5iaN
4tlA is deposited, anisotropic etching is performed to form a 5iaN4 film 4 only on the gate sidewalls, and zero-order thermal oxidation is performed to reinforce the gate oxide film as shown in FIG. At this time, oxidation may be performed after removing the gate oxide film except under the gate electrode.
The iaNa film 4 is removed and a thin oxide film 5 is formed as shown in FIG.
form. Next, a low concentration drain (n-) layer 8 is formed by ion implantation, poly-Si is deposited as shown in FIG. 4, and anisotropic etching is performed to form the sidewall 6.
form. Next, a heavily doped drain (n+) layer 9 is formed by ion implantation. At this time, ion implantation is also performed on the sidewall 6, so that it becomes a conductive film. Thereafter, a passivation film is formed and a wiring process is performed to obtain an LDD type MOSFET having a structure in which a conductive sidewall is connected to a gate electrode via a thin resistor. According to this manufacturing method, etching damage to the gate oxide film under the sidewalls and loss of oxide film thickness that occur during gate electrode processing can be recovered and reinforced through the oxidation process.
No gate breakdown voltage failure occurs.
なお、本実施例ではポリＳｉ単層のゲートに適用したも
のであるが、高融点金属を用いてシリサイド化した層を
設は低抵抗化を図った多層ゲート構造についてももちろ
ん適用できる。また、ゲート側壁に耐酸化マスクとして
用いたＣ Ｖ Ｄ 、Ｓ １３Ｎａ４の膜厚はほぼ堆積
時の膜厚で決まるが、厚くなる程５ｉａＮａ１９１直下
の、Ｓ ｉ表面が酸化しにくくなる。従って耐酸化マス
クとして機能する程度の膜厚とする必要がある。本実施
例ではＣＶ Ｄ Ｓ３．３Ｎ４を用いたが、プラズマＳ
ｉ３Ｎ４等、耐酸化マスクとして機能するものであれば
本発明に適用できる。In this embodiment, the present invention is applied to a poly-Si single layer gate, but it can of course also be applied to a multilayer gate structure in which a layer made of silicide using a high melting point metal is provided to lower the resistance. Furthermore, the thickness of the C V D , S 13 Na 4 film used as an oxidation-resistant mask on the gate sidewall is determined approximately by the film thickness at the time of deposition, and the thicker the film, the more difficult it is to oxidize the Si surface directly under the 5 ia Na 191 . Therefore, the film needs to be thick enough to function as an oxidation-resistant mask. In this example, CVD S3.3N4 was used, but plasma S3.3N4 was used.
Any material that functions as an oxidation-resistant mask, such as i3N4, can be applied to the present invention.
また、本実施例では導電性を持つサイドウオールとゲー
ト電極の間に抵抗として用いる薄い酸化膜を形成したデ
バイス構造に本発明を適用したものであるが、導電性を
持つサイドウオールとゲート電極を直接接続させた構造
、つまり単にドレイン低濃度層にゲートをオーバーラツ
プさせた構造についても本発明を適用できる。また、本
実施例ではＮＭＯ８について本発明を適用したものであ
るがＰＭＯ３についても同様にして適用できる。Furthermore, in this example, the present invention is applied to a device structure in which a thin oxide film used as a resistor is formed between a conductive side wall and a gate electrode. The present invention can also be applied to a directly connected structure, that is, a structure in which the gate is simply overlapped with the lightly doped drain layer. Further, in this embodiment, the present invention is applied to NMO8, but it can be similarly applied to PMO3.
本発明により導電性サイドウオールをゲート電極に接続
した構造のＬＤＤ型ＭＯ５ＦＩＥＴを製造すれば。According to the present invention, an LDD type MO5FIET having a structure in which a conductive sidewall is connected to a gate electrode can be manufactured.
導電性サイドウオール下のゲート酸化膜が補強されるの
で、ゲート耐圧不良を起こすことがない。Since the gate oxide film under the conductive sidewalls is reinforced, gate breakdown voltage failures do not occur.
第１図〜第４図は本発明の一実施例を示す断面図である
。
１・・・ゲート酸化膜、２・・・ポリＳｉゲート電極、
３−ＣＶＤ５ｉＯｚ膜、４・・・ＣｖＤ８１３Ｎ４暎、
Ｓ・・薄い酸化膜、６・・・ポリＳｉサイドウオール、
７・・・Ｐ型Ｓｉ基板、８・・・ドレイン（ソース）低
不純物濃度層、９・・・ドレイン（ソース）高不純物濃
度層。1 to 4 are cross-sectional views showing one embodiment of the present invention. 1... Gate oxide film, 2... Poly-Si gate electrode,
3-CVD5iOz film, 4...CvD813N4,
S... Thin oxide film, 6... Poly Si side wall,
7... P-type Si substrate, 8... Drain (source) low impurity concentration layer, 9... Drain (source) high impurity concentration layer.
Claims (1)
ート酸化膜上にゲート電極を形成する工程と、耐酸化性
材料をゲート電極側壁に形成する工程と、上記耐酸化性
材料をマスクとして酸化を行なう工程と、ゲート電極を
マスクとしてイオン打ち込みを行ない、ソース・ドレイ
ン低不純物濃度領域を形成する工程と、導電体でサイド
ウォールを形成する工程と、ゲート電極、および上記サ
イドウォールをマスクとしてイオン打ち込みを行ない、
ソース・ドレイン高不純物濃度領域を形成する工程を有
することを特徴とする半導体装置の製造方法。1. A step of forming a gate oxide film on a semiconductor substrate, a step of forming a gate electrode on the gate oxide film, a step of forming an oxidation-resistant material on the side walls of the gate electrode, and a step of forming the oxidation-resistant material as a mask. A step of performing oxidation, a step of performing ion implantation using the gate electrode as a mask to form a source/drain low impurity concentration region, a step of forming a sidewall with a conductor, and a step of forming the sidewall using the gate electrode and the sidewall as a mask. Perform ion implantation,
1. A method of manufacturing a semiconductor device, comprising the step of forming source/drain high impurity concentration regions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16403889A JPH0330432A (en) | 1989-06-28 | 1989-06-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16403889A JPH0330432A (en) | 1989-06-28 | 1989-06-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0330432A true JPH0330432A (en) | 1991-02-08 |
Family
ID=15785623
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16403889A Pending JPH0330432A (en) | 1989-06-28 | 1989-06-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0330432A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1020922A2 (en) * | 1998-12-28 | 2000-07-19 | Infineon Technologies North America Corp. | Insulated gate field effect transistor and method of manufacture thereof |
-
1989
- 1989-06-28 JP JP16403889A patent/JPH0330432A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1020922A2 (en) * | 1998-12-28 | 2000-07-19 | Infineon Technologies North America Corp. | Insulated gate field effect transistor and method of manufacture thereof |
| EP1020922A3 (en) * | 1998-12-28 | 2001-08-08 | Infineon Technologies North America Corp. | Insulated gate field effect transistor and method of manufacture thereof |
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