JPS62245675A - Ldd type mos transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To manufacture an LDD type MOSFET making an angle of gate sidewall with a substrate not exceeding 30 deg. by a method wherein a polysilicon gate is formed by etching using first CBrF3+O2 and second SF6 as masks. CONSTITUTION:A gate oxide film 11, a polysilicon 13 and a resist mask 14 are laminated on an Si substrate 12 and then a part of polysilicon 13 is anisotropically etched by CBrF3+O2 to be further isotropically etched by SF6 adjusting the angle of sidewall 17 to the substrate 12 not exceeding 30 deg.. When the resist mask 14 is removed for ion implantation 16 and thermal diffusion, a diffused layer 15 in low concentration near the gate 11 and in high concentration in the other parts is formed to manufacture an LDD type MOSFET with excellent reproducibility.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the constituent elements and manufacturing method of an LDD type MOS transistor.

[Conventional technology]

As transistors (MOS) become smaller, the electric field concentrates on the drain near the gate, reducing the drain breakdown voltage. Therefore, as a countermeasure, a drain (hereinafter abbreviated as LDD) structure is generally considered, which consists of a low concentration diffusion layer in the vicinity of the gate and a normal high concentration diffusion layer in other parts. Its structure is shown in FIG. In FIG. 3, 12 is a substrate, 31 is a gate oxide film, 62 is a thick diffusion layer, 63 is a thin diffusion layer, 34 is a polycrystalline silicon gate, and 65 is a sidewall made of an oxide film.

The manufacturing method is as follows: (1) forming the polycrystalline silicon gate 34; using the rear polycrystalline silicon gate 64 as a mask;
A thin diffusion layer 66 is formed.

(2) Deposit a gate oxide film 61 over the entire surface and etch the entire gate oxide film 31 to leave an oxide film 65 on the sidewalls of the polycrystalline silicon gate 64. (Hereinafter abbreviated as sidewall.) (3) Using the sidewall 65 as a mask, a normal dense diffusion layer 62 is formed. This is a common manufacturing method.

[Problem that the invention seeks to solve]

However, in the conventional LDD structure and LDD formation method, the polycrystalline silicon gate 34 and the sidewall 35
Since the LDD is formed separately, there are problems in forming a uniform LDD with good reproducibility (((), and in order to form a sidewall, there are many steps to form the LDD.The purpose of the present invention is to An object of the present invention is to provide an LDD structure and a manufacturing method thereof that can avoid the disadvantages of the above.

[Means for solving problems]

In order to achieve the above object, the present invention is characterized in that it has an LDD structure without sidewalls generated during gate etching, and that the LDD structure is formed by side etching of gate etching for shaping polycrystalline silicon.

〔Example〕

Embodiments of the present invention will be described below based on the drawings. 1st
The figure is a process diagram showing an LDD type MOS transistor formed by side etching during gate etching of the present invention and its manufacturing process.

In the figure, step a oxidizes the silicon substrate 12 to a thickness of 5
A gate oxide film 11 of 00A is formed. In the step, polycrystalline silicon 13, which will become a gate material, is deposited. Step C forms a resist mask 14 for polycrystalline silicon shaping, and steps d and e are polycrystalline silicon shaping steps that are a feature of the present invention. First, in step d, a part of the polycrystalline silicon 16 is anisotropically etched using CBrF3+02 gas. Next, in step e, the remaining polycrystalline silicon 13 is isotropically etched using SF and gas to shape it into a polycrystalline silicon gate having an angle α between the side wall 17 and the substrate 12 of 30° or less. . After removing the resist 14, in step f, ions 16 are added to form source and drain diffusion layers.
is implanted into the substrate 12. Then, by thermal diffusion in step g, a diffusion layer 15 is formed which has a low concentration near the gate and a high concentration elsewhere.

In the present invention, polycrystalline silicon shaped CB r FA+02
Two-step etching is performed using gas, SF, and gas; S Fa gas inherently has isotropic etching properties, and CB r Fs+ 02 gas has anisotropic etching properties. Therefore, etching polycrystalline silicon with SFa gas alone is better than etching some percentage of polycrystalline silicon anisotropically with CB r F, + 02 gas, and isotropically etching the remaining polycrystalline silicon with SFa gas. It would be expected that the amount of side etching would be larger than the amount of side etching, but in reality the result is the opposite. The results are shown in FIG. Figure 2 shows
FIG. 3 is a diagram showing the amount of side etching of polycrystalline silicon in two-step etching.

The value on the horizontal axis is CBrF, +02 of polycrystalline silicon.
This is the rate of etching with gas. (The value below the horizontal axis is the rate of etching polycrystalline silicon with SF6 gas following CB r F3+ 02 gas.) For example, the horizontal axis 20 (upper value) and 80 (lower value) are: A case is shown in which 20% of the entire polycrystalline silicon film is etched with CBrF3+02 gas, and then 80% is etched with SF gas, and the value on the vertical axis at that time is the side etching amount.

Also, the value zero at the top of the horizontal axis is when polycrystalline silicon is etched with only SF6 gas, and the value 100 at the top is CB.
This is the case where etching was performed only with rF and +o□.

It can be seen from Figure 2 that in one step CB r F
As the etching rate of polycrystalline silicon with +0 If this is done, the amount of side etching will be greatly reduced.

This means that CBrF, +O, gas, which contributes to this invention,
This figure shows the characteristics of two-step polycrystalline silicon etching using SFa gas. Therefore, for example, ゛CBrFa+
By etching 60% with 02CBrF3+02 gas and etching the remaining 40% with SF6 gas, the etching amount on the side wall will be about 3μ, making it possible to create an LD with good reproducibility at an angle of 30°C or less.
D is formed.

〔Effect of the invention〕

As is clear from the above explanation, the LDD manufacturing method according to the present invention is simpler than the conventional method, and both the diffusion layers of the thick diffusion region and the thin diffusion region can be formed by self-alignment, and the process is greatly shortened. effective.

[Brief explanation of drawings]

FIG. 1 is a process diagram of the method for manufacturing an LDD type MOS transistor according to the present invention, and FIG. 2 is a graph showing the amount of side etching in a two-step etch of polycrystalline silicon with different gases.
FIG. 3 is a cross-sectional view showing the structure of a conventional general LDD type MOS transistor. ' 11.31...Gate oxide film, 16...
・Polycrystalline silicon, 15... Diffusion layer, 16...
...Ion, 17...Side wall, 32...
・・Dark diffusion layer, 66・・・・Thin diffusion layer, 64・
...Polycrystalline silicon gate, 35...Side wall.

Claims (2)

[Claims] (1) In an LDD type MOS transistor, the gate of the MOS transistor is formed of polycrystalline silicon, and the angle between the side wall of the gate formed of polycrystalline silicon and the substrate is 30° or less. LDD type MO
S transistor. (2) In a method for manufacturing an LDD type MOS transistor in which the angle between the side wall of the gate made of polycrystalline silicon and the substrate is 30° or less, the gate made of polycrystalline silicon is etched using a mask. A two-step etching process was performed, with the first etching being CBrF_3.
The second etching is performed using a mixed gas of SF_ and O_2.
A method for manufacturing an LDD type MOS transistor characterized by using 6 gases.