JPS61171172A - Manufacture of mesfet - Google Patents
Manufacture of mesfetInfo
- Publication number
- JPS61171172A JPS61171172A JP60012164A JP1216485A JPS61171172A JP S61171172 A JPS61171172 A JP S61171172A JP 60012164 A JP60012164 A JP 60012164A JP 1216485 A JP1216485 A JP 1216485A JP S61171172 A JPS61171172 A JP S61171172A
- Authority
- JP
- Japan
- Prior art keywords
- metallic film
- electrode
- source
- gate electrode
- photo resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims description 18
- 238000000605 extraction Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 15
- 229910004205 SiNX Inorganic materials 0.000 abstract 2
- 230000008020 evaporation Effects 0.000 abstract 2
- 238000001704 evaporation Methods 0.000 abstract 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000004299 exfoliation Methods 0.000 abstract 1
- 239000004642 Polyimide Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910017401 Au—Ge Inorganic materials 0.000 description 1
- 206010011732 Cyst Diseases 0.000 description 1
- 101150114751 SEM1 gene Proteins 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
- H01L29/8128—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate with recessed gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＧＨｚ帯の高周波装置に使用されるＭＥＳＦＥ
Ｔの製造方法に関わり、特にソース或いはドレインの引
き出し電極を°形成する金属層によって電極間の短絡が
発生することの無いＭＥＳＦＥＴの製造方法に関わる。[Detailed Description of the Invention] [Industrial Application Field] The present invention applies to MESFE used in high frequency equipment in the GHz band.
The present invention relates to a method of manufacturing T, and in particular to a method of manufacturing MESFET in which short circuits between electrodes do not occur due to metal layers forming source or drain extraction electrodes.
なお、本明細書に於いアｊＴｋ田七飴２λｊ口Ｃひロ〒
ψ？ツ曇移神 一番−１ノＳｅｍ１ｃｏｎｄｕｃｔｅｒ
電界効果トランジスタの略称であって、シッットキバリ
ャグート型電界効果トランジスタと同義である。In addition, in this specification,
ψ? Tsugumo Mushin Ichiban-1 no Sem1 conductor
It is an abbreviation for field effect transistor, and is synonymous with sittkivaryagut field effect transistor.
ＭＥＳＦＥＴの代表的な素子であるＧａＡｓＦＥＴは、
第３図にその断面構造が示されるように、半絶縁性のＧ
ａＡｓ基板３０上にｎ型の能動層３１をエピタキシャル
成長させ、その表面を選択的にエツチングして浅い溝３
２を掘り、その底部をチャネル領域としてゲート電極３
３を形成し、溝の両側の台地部分にソース電極３４．ド
レイン電極３５を形成した構造を有する。半絶縁性Ｇａ
Ａｓ基板とｎ型の能動層の間にバッファ層が形成される
場合もあるが、第３図では省略されている。GaAsFET, which is a typical element of MESFET, is
As its cross-sectional structure is shown in Figure 3, semi-insulating G
An n-type active layer 31 is epitaxially grown on an aAs substrate 30, and its surface is selectively etched to form shallow grooves 3.
2, and use the bottom of the gate electrode 3 as a channel region.
Source electrodes 34.3 are formed on the plateau portions on both sides of the trench. It has a structure in which a drain electrode 35 is formed. Semi-insulating Ga
Although a buffer layer may be formed between the As substrate and the n-type active layer, it is omitted in FIG.
実際の素子では第４図に示すように、ゲート電極４３は
櫛の歯状のパターンを持ち、歯の部分を挟んでソース電
極とドレイン電極が交互に配置されるので、複数のソー
ス電極同士、ドレイン電極同士は引き出し電極４４．４
５で接続されることになる。In an actual device, as shown in FIG. 4, the gate electrode 43 has a comb tooth-like pattern, and source electrodes and drain electrodes are alternately arranged with the tooth portions in between. Drain electrodes are lead electrodes 44.4
5 will be connected.
ゲート電極は通常Ａｔで形成され、ソース／ドレイン電
極はＡｕ−Ｇｅ合金とＡｕを積層したもので形成される
。The gate electrode is usually made of At, and the source/drain electrodes are made of a stack of Au-Ge alloy and Au.
引き出し電極は次のような工程で形成される（以下、第
２図参照）。The extraction electrode is formed in the following steps (see FIG. 2 below).
＋ａ）図に断面形状を示すように、半絶縁性のＧａＡｓ
基板２０上にｎ型の能動層２１をエピタキシャル成長さ
せ、ゲート電極２３．ソース電極２４．ドレイン電極２
５を形成した後、プラズマＣＶＤ方によりＳ ｉ Ｎ
、２６を被着し、ソース電極及びドレイン電極上に窓を
開ける。+a) As the cross-sectional shape is shown in the figure, semi-insulating GaAs
An n-type active layer 21 is epitaxially grown on a substrate 20, and a gate electrode 23. Source electrode 24. drain electrode 2
After forming 5, SiN is formed by plasma CVD method.
, 26 and open windows over the source and drain electrodes.
次いで、（′ｂ）図に示すように金属皮膜２７を蒸着形
成する。この金属皮膜は実際には下から３０００人のＴ
ｉ 、 １５００人のｐｔ、ｓｏｏ人のＡｕを積層し
た３層構造の皮膜である。Next, as shown in Figure ('b), a metal film 27 is formed by vapor deposition. This metal film is actually 3000 T from the bottom.
It is a three-layered film consisting of 1500 pt, 1500 pt and soo Au laminated.
これをパターニングして（Ｃ１図の如くソース引き出し
電極４４、ドレイン引き出し電極４５が形成される。By patterning this (as shown in Figure C1, a source lead-out electrode 44 and a drain lead-out electrode 45 are formed).
上記工程で引き出し電極を形成すると、第２図ｔｃ＋に
２９として示される如く金属皮膜に残留部が発生ずる。When the extraction electrode is formed in the above process, a residual portion is generated in the metal film as shown as 29 in FIG. 2 tc+.
これは、高さが例えば７０００人のゲート電極が深さ２
０００人の溝の中に形成されており、ソース、ドレイン
電極がその両側の台地部分に形成され、ゲート電極との
間隔が１μｍ程度であることから、Ｓ ｉ Ｎ ｘ層に
深い窪みが発生し、パターニングの際に金属皮膜を完全
にエツチングし切れないことから発生するものである。This means that a gate electrode with a height of, for example, 7,000 people has a depth of 2
The source and drain electrodes are formed on the plateau on both sides, and the distance from the gate electrode is about 1 μm, so deep depressions occur in the S i N x layer. This occurs because the metal film cannot be completely etched during patterning.
この金属皮膜の残留部がゲート電極に沿って発生すると
、第４図に示される如くゲート電極とソース引き出し電
極が交叉する箇所は通常存在するから、その部分で両者
は短絡されることになる。If this residual portion of the metal film occurs along the gate electrode, there is usually a point where the gate electrode and the source extraction electrode intersect, as shown in FIG. 4, so that the two will be short-circuited at that point.
本発明はこのような短絡が発生することのない引き出し
電極形成法を提供するものである。The present invention provides a method for forming an extraction electrode in which such a short circuit does not occur.
本発明に於いては、前記金属皮膜蒸着工程の前に、深い
窪みの部分を含む領域をフォトレジスト Ｊ
・層で被覆して富みを埋め、しかる後金属皮膜を蒸着等
の手段により被着して不要のフォトレジストを除去する
ことにより、前記残留部の発生を解消している。In the present invention, before the metal film deposition step, the area including the deep depression is coated with photoresist J.
- The generation of the residual portion is eliminated by covering the photoresist with a layer to fill in the pores, and then applying a metal film by vapor deposition or other means to remove unnecessary photoresist.
上記の如くフォトレジストによって富みを埋めて金属皮
膜を蒸着しているので、エツチングし切れない部分は存
在せず、完全なパターニングが行われる。また、金属皮
膜は蒸着によって形成されるので、基板表面の温度上昇
は僅かであり、フォトレジストが分解することによる不
都合は生じない。As described above, since the metal film is deposited by filling in the rich areas with photoresist, there is no part that cannot be completely etched, and complete patterning is performed. Furthermore, since the metal film is formed by vapor deposition, the temperature rise on the substrate surface is slight, and no inconvenience caused by decomposition of the photoresist occurs.
フォトレジストの他に、例えばポリイミドのような樹脂
を使用することが可能であるが、この場合にはポリイミ
ドをパターニングすることによって同様の作用を生ぜし
めることが可能である。In addition to photoresist, it is possible to use a resin such as polyimide, in which case it is possible to produce a similar effect by patterning the polyimide.
第１図は本発明の工程の実施例を示す断面図である（以
下、第１図参照）。FIG. 1 is a sectional view showing an embodiment of the process of the present invention (see FIG. 1 below).
（８１図は通常の工程で基板１１上にゲート電極１３、
ソース／ドレイン電極１４．１５、ＳｉＮ、層１６が形
成され、フォトレジスト１６をマスクとしてＳｉＮ、層
に窓が開けられた状態を示している。(Figure 81 shows that the gate electrode 13 is placed on the substrate 11 in a normal process.
Source/drain electrodes 14 and 15, a SiN layer 16 are formed, and a window is opened in the SiN layer using the photoresist 16 as a mask.
シスト層をその侭残して、金属皮膜１７が蒸着される０
次いで金属皮膜がパターニングされ、引き出し電極４４
．４５が形成される。）オドレジスト層はその後レジス
ト剥離液で除去され、（０）図の如く金属皮膜残留部の
無いＭＥ Ｓ Ｆ ＥＴが形成される。A metal film 17 is deposited, leaving the cyst layer intact.
The metal film is then patterned to form the extraction electrode 44.
．． 45 is formed. ) The odd resist layer is then removed with a resist stripping solution, and a MESFET with no remaining metal film is formed as shown in Figure (0).
上記実施例では窓開は用のフォトレジストをその侭利用
したが、フォトレジストは一旦除去した後、ゲート電極
周辺の窪みの部分を中心に再度塗布しても良い。In the above embodiment, the photoresist used for opening the window was used, but the photoresist may be removed once and then reapplied mainly in the recessed area around the gate electrode.
既述した如く、フォトレジストの他にポリイミドのよう
な樹脂を使用することが可能であり、該樹脂を使用する
場合の実施態様もフォトレジストを使用する場合とはり
同様である。As mentioned above, it is possible to use a resin such as polyimide in addition to photoresist, and the embodiments when using this resin are similar to those when using photoresist.
本発明の工程によれば、ソース／ドレイン電極の引き出
し電極を形成する際に、ゲート電極近傍に金属皮膜が残
留することが無く、ソース／ドレインとゲートの短絡が
発生することが無い。According to the process of the present invention, when forming the extraction electrode of the source/drain electrode, no metal film remains in the vicinity of the gate electrode, and no short circuit between the source/drain and the gate occurs.
第２図は従来技術工程を示す断面図、
第３図、第４図はＭＥＳＦＥＴの電極構造を示す断面図
及び平面図である。
図に於いて、
１０．２０．３０は半絶縁性ＧａＡｓ基板１１．２１．
３１はｎ型の能動層
１３、２３．３３．４３はゲート電極
１４．２４．３４はソース電極
１５、２５．３５はドレイン電極
１６．２６はＳｉＮ、１層
１７．２７は金属皮膜
１８はフォトレジスト
２９は金属皮膜の残留部
３２は浅い溝
４４はソース引き出し電極
４５はドレイン引き出し電極
４６はゲート用ポンディングパッドである。FIG. 2 is a sectional view showing a conventional process, and FIGS. 3 and 4 are a sectional view and a plan view showing the electrode structure of a MESFET. In the figure, 10.20.30 are semi-insulating GaAs substrates 11.21.
31 is an n-type active layer 13, 23, 33, 43 is a gate electrode 14, 24, 34 is a source electrode 15, 25.35 is a drain electrode 16.26 is SiN, 1 layer 17.27 is a metal film 18 is photo The resist 29 includes a remaining portion 32 of the metal film, a shallow groove 44, a source lead-out electrode 45, a drain lead-out electrode 46, and a gate bonding pad.
Claims (1)
極を形成する工程と、ソース電極及びドレイン電極を形
成する工程を実施した後、少なくも前記凹所部分に樹脂
を埋め込んだ状態で金属皮膜を蒸着する工程と、該金属
皮膜をパターニングしてソース、ドレイン引き出し電極
を形成する工程とを有することを特徴とするＭＥＳＦＥ
Ｔの製造方法。After forming a shallow groove on the surface of the semiconductor substrate, forming a gate electrode in the groove, and forming a source electrode and a drain electrode, metal is filled with resin in at least the recessed part. A MESFE characterized by comprising a step of vapor depositing a film, and a step of patterning the metal film to form source and drain extraction electrodes.
Method for manufacturing T.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60012164A JPS61171172A (en) | 1985-01-25 | 1985-01-25 | Manufacture of mesfet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60012164A JPS61171172A (en) | 1985-01-25 | 1985-01-25 | Manufacture of mesfet |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61171172A true JPS61171172A (en) | 1986-08-01 |
| JPH0328061B2 JPH0328061B2 (en) | 1991-04-17 |
Family
ID=11797799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60012164A Granted JPS61171172A (en) | 1985-01-25 | 1985-01-25 | Manufacture of mesfet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61171172A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0526521U (en) * | 1991-09-26 | 1993-04-06 | 日産デイーゼル工業株式会社 | Damping force control device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS598378A (en) * | 1982-07-06 | 1984-01-17 | Nec Corp | Gaas fet |
-
1985
- 1985-01-25 JP JP60012164A patent/JPS61171172A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS598378A (en) * | 1982-07-06 | 1984-01-17 | Nec Corp | Gaas fet |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0526521U (en) * | 1991-09-26 | 1993-04-06 | 日産デイーゼル工業株式会社 | Damping force control device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0328061B2 (en) | 1991-04-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |