JPS62171139A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To avoid gas pockets by a method wherein a dummy part is added to a U-groove and the dummy part form a crossing part or a large width part which has a larger aperture than the other part of the U-groove and chemical vapor deposition of filling material is carried out under depressurized conditions. CONSTITUTION:Even if polycrystalline silicon is made to grow on the other part of a U-groove, a cavity 20a remains at the center part of a dummy part 22c. If chemical vapor phase deposition is continued in this state, growth gas, for instance SiH4, is made to flow into a tunnel cavity 20b in the part other than the dummy part 22c from the cavity 20a at the center part of the dummy part 22c to fill the cavity 20b with polycrystalline silicon. Although the cavity 20a is not yet completely filled when the cavity 20b is completely filled with polycrystalline silicon, the chemical vapor phase deposition is discontinued at this stage. If Al is applied like conventional examples and patterned, an Al dot 18b is left between electrode wirings 18. However, the Al dot 18b does not cause the short-circuit between the electrode wirings 18.

Description

[Detailed Description of the Invention] [Summary] In a Um burying method formed in a semiconductor substrate, a dummy trench is provided to supplement filling with polycrystalline silicon (polysilicon).

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for preventing the generation of holes that have conventionally been observed when a U-groove is filled with a filler, that is, polysilicon, to provide insulation isolation. .

[Conventional technology]

In the manufacturing process of semiconductor devices, a U-trench buried insulation isolation method is often used. To explain this with reference to the cross-sectional view of FIG. 5, a silicon nitride film (Si5Nu film) 12 is formed on the surface of a semiconductor substrate 11, and after patterning it, a U groove 13 is formed in the substrate by etching. The surface of the trench is oxidized to form an oxide film (SiO2 film) 14, and then a filler (polysilicon) is grown by chemical vapor deposition to form polysilicon 15.

Next, the surface of the substrate is made flat by polishing as shown in FIG.

Next, the silicon nitride film 12 is removed, and the polysilicon film 15 is removed.
A 5i02 film 16 is formed by oxidizing the surface of the 5i02 film 16. At this time, the substrate surface after the silicon nitride film has been removed is also oxidized, and a 5i02 film 16 is also formed on the substrate surface (FIG. 5(C)).
.

Next, as shown in FIG. 5(d), the electrode window 17 is opened and aluminum (An 1B) is deposited on the entire surface.

Finally, Al is patterned by, for example, anisotropic etching to form electrode wiring 18 as shown in FIG. 5(e).

FIG. 6 is a plan view of the buried insulating isolation layer 19 formed as described above, and the buried insulating isolation layer 19 is formed by forming a 5i02 film 16 on the surface of the polysilicon 15. In one example, the area surrounded by the buried insulating isolation layer has dimensions of 5 μm x 10-15 μm.

[Problem that the invention seeks to solve]

In the above-described U-trench embedding insulation isolation method, there are many cases where the U-trench shape becomes a narrow opening, and when filling such a narrow opening with a filler such as polysilicon, the polysilicon is
Because it grows evenly from the groove surface, the narrow part at the top of the groove closes before the inside of the groove is fully filled, resulting in a fifth layer inside the groove.
A cavity 20 may occur in figure fa). When this is flattened by a technique such as polishing, a groove 21 is generated at the center of the groove (FIG. 5(b)).

If such a step 21 exists, when the AI is etched by anisotropic etching in the AI patterning explained with reference to FIG. If the remainder 18a of An2 exists in this way, the electrode wiring 18
There is a problem in that the wires are short-circuited as shown in FIG.

The present invention was created in view of these points, and an object of the present invention is to provide a method for preventing the occurrence of scratches in a U-groove buried insulation isolation method.

[Means for solving problems]

FIG. 1 is a plan view of an embodiment of the present invention.

In the present invention, the conventional buried insulating R layer 19 is formed into dummy portions 22a and 22b as shown by the white arrows.

22c, and the mean free path of the filling gas (growth gas) for filling material growth.
system that lengthens the pass) (e.g. 0.1 to 1.OTor
The filling of the effective element portion is supplemented by vapor phase growth in a reduced pressure system (r).

[Effect]

In the method described above, the dummy parts 22a and 22b.

22c, during chemical vapor deposition, it takes time for the opening in the dummy part to be filled with the filler (polysilicon), and it takes time for the opening in the dummy part to be filled with the filler (polysilicon). Since the cavities in the dummy part are completely buried, the cavities that were previously generated over most of the buried insulating separation layer are completely eliminated.On the other hand, the small cavities in the dummy part remain in the form of dots, but even if the dots of Ag remain there, they are not in contact with the electrodes. There is no risk of wiring short-circuiting.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 (Al is a plan view of the embodiment of the present invention, it is an enlarged view of the dummy portion 22c in FIG. 1, and FIG. 2 (mountain) is a sectional view taken along line BB in FIG. 2(a).

In chemical vapor deposition, the filler, that is, polysilicon, grows uniformly from the surface of the U-groove, so even if polysilicon grows in other parts of the U-groove as seen in FIG. A cavity 20a remains in the center.If chemical vapor deposition is continued in this state, the cavity 20a in the center of the dummy part 22c will remain.
Tunnel-shaped cavity 20b in the part other than the dummy part from 0a
A growth gas (for example, Sth) flows into the cavity 20b.
Embed with polysilicon. When the cavity 20b is completely filled with polysilicon, the cavity 20a is not yet completely filled, but the chemical vapor deposition is stopped at this stage.

Then, when polished in the same manner as in the conventional example, the third
As shown in the plan view of the figure, the dotted holes 21 are connected to the dummy part 22.
remains at the center of c. Subsequently, when AI is deposited and buttered in the same manner as in the conventional example, dot-shaped A18b remains between the electrode wirings 18, as shown in the plan view of FIG.
As can be understood from a comparison between FIG. 4 and FIG. 6, in the past, Al 18a was linearly extended between the electrode wirings 18, causing a short circuit, but dotted A/ 18b There is no risk of causing a short circuit in the electrode wiring 18.

In order to promote the growth of the filling material (polysilicon) in the tunnel-like cavity 20b, the present invention uses a system in which the mean free path of the growth gas is long, that is, 0
, 1-1. Chemical vapor deposition is performed in a reduced pressure system of Q Torr to supplement the filling of the effective element portion (for example, the cavity 20b).

The shape of the dummy portion is not only the shape of the intersection shown by reference numerals 22a and 22c in FIG. 1, but also the wide part shown by the reference numeral 22b in the figure. The key is to provide extra structure to provide a wide opening rather than a narrow opening.

Incidentally, the formation of the U-groove, oxidation polishing of the surface of the U-groove, oxidation of the polysilicon surface, deposition of Aρ and its patterning, etc., are performed in exactly the same manner as in the conventional example to form the element insulation isolation layer.

〔Effect of the invention〕

As described above, according to the present invention, in the Ui buried insulation isolation method, by providing a dummy trench, filling with polysilicon is supplemented, short circuits of electrode wiring, etc. are prevented, and it is effective for increasing the reliability of semiconductor devices. It is.

[Brief explanation of drawings]

FIG. 1 is a plan view of an embodiment of the present invention, FIG. 2(a) is an enlarged portion of the dummy part in FIG.
3 is a plan view of the dummy part in FIG. 2 after polishing, and FIG. 4 is a plan view showing l remaining in the hole after electrode wiring is formed. Fig. 5 is a cross-sectional view of the conventional example, and Fig. 6 is a plan view showing problems of the conventional example. In Figs. 1 to 6, 11 is a semiconductor substrate, 12 is a silicon nitride film, and 13 is a U-groove. , 14 is a SiO2 film, 15 is a polysilicon, 16 is a SiO2 film, 17 is an electrode window, 18 is an electrode wiring, 18a and 18b are remaining parts, 19 is a buried insulating separation layer, 20, 20a, and 20b are cavities, 21 Lotus, 22a, 22b, and 22c are dummy parts. Agent: Patent attorney Moto Kuki Agent: Yoshiyuki Osuga Concave glue ゛S-name PmeL Fig. 2 't21 G+ side view Fig. 3 Electrode arrangement 1 unit remaining to support the J assembly ↑ Plan view Fig. 4 #R -faced En, 58 AT +8 electrulbles 177, ' / Ti self -♂ treat] 8 ノ''4 times Katsu 1 L].

Claims (1)

[Claims] A U-groove (13) is formed in a semiconductor substrate (11), and a U-groove (13) is formed in a semiconductor substrate (11).
3) In the U-groove embedding insulation isolation method in which a filler (15) is embedded in the U-groove (13), a dummy portion (22a, 2
2b, 22c), and chemical vapor deposition of the filler (15) is performed in a reduced pressure system.