JP2616134B2 - SOI transistor stacked semiconductor device and method of manufacturing the same - Google Patents

Description

The present invention relates to a semiconductor device for stacking SOI transistors and a method for manufacturing the same.

[Conventional technology]

Although the degree of integration of semiconductor devices has been improved by miniaturization, it has become a submicron region and further miniaturization is becoming technically difficult. Therefore, attempts have been made to increase the degree of integration by using a multi-layer transistor layer without miniaturizing the mask rule. However, wiring for electrically connecting the transistors is complicated, and it is necessary to connect the transistors not only within the layers but also between the layers. Therefore, the area required for wiring increases.

The conventional structure and manufacturing method will be specifically described with reference to the sectional view of the conventional SOI transistor stacked semiconductor device shown in FIG.

On a silicon substrate 1 in which an element isolation region is defined by a field oxide film 2, a lower transistor including a gate insulating film, a source / drain diffusion layer 3, and a gate electrode 4 partially extending over the field oxide film 2 is formed. It is formed. An interlayer insulating film 5 made of, for example, SiO _{2 over} the entire surface of the silicon substrate 1.
Is deposited thereon, and a silicon semiconductor layer is formed thereon. A gate insulating film, a source / drain semiconductor layer 6, and a gate electrode 7 made of polycrystalline silicon, a part of which extends over the interlayer insulating film 5, are formed on the silicon semiconductor layer. Thus, an upper layer transistor of the SOI structure is formed. Upper transistor, interlayer insulating film 5
On top of this is deposited an insulating film 8 made of, for example, SiO ₂ .

Next, the source / drain diffusion layer 3 of the lower transistor
The connection of the transistors between the layers will be described by taking, as an example, a case in which the transistor is connected to the source / drain semiconductor layer 6 of the upper transistor.

Before and after the formation of the upper transistor, a contact hole reaching the source / drain diffusion layer 3 is provided in the interlayer insulating film 5, tungsten 10 is buried in the contact hole by selective vapor deposition, and aluminum as the lower aluminum wiring is formed. Eleven patterns are formed on the interlayer insulating film 5.
Subsequently, after an insulating film 8 is deposited,
By providing a contact hole reaching 11 and a contact hole reaching the source / drain semiconductor layer 6 and forming aluminum 12 which is an upper aluminum wiring, the source / drain diffusion layer 3 of the lower transistor and the source / drain of the upper transistor are formed. The connection with the drain semiconductor layer 6 is realized.

[Problems to be solved by the invention]

As shown in FIG. 3, in the prior art, in order to obtain the connection of the transistors between the layers in the SOI transistor stacked semiconductor device, the terminals of the transistors between the layers cannot be directly connected. A wiring metal layer is required, and there are steps required for the wiring metal layer, and a dedicated area is also required, which hinders an improvement in the degree of integration.

[Means for solving the problem]

In the SOI transistor stacked semiconductor device of the present invention, terminals of transistors between layers are directly connected by one contact hole in which metal is buried by selective vapor deposition. Further, the side wall of the through-hole of the upper transistor terminal in the contact hole is formed to be recessed from the side wall of the other through-hole.

In the present invention, the first shape of the contact hole having the above shape is used.
First, a through portion is formed in the insulating film above the upper transistor by etching, then a through portion is formed in a terminal portion of the upper transistor by isotropic dry etching, and then anisotropic dry etching is performed. This is a method of forming a penetrating portion in an interlayer insulating film between an upper transistor and a lower transistor.

Second contact hole having the above-mentioned shape in the present invention
Is formed by anisotropic dry etching to form an insulating film above the upper transistor, a terminal portion of the upper transistor, and a through portion penetrating the interlayer insulating film between the upper transistor and the lower transistor with the same diameter, Selective vapor growth of metal in the through portion of the terminal of the upper transistor,
This is a method of forming the shape of the contact hole of the present invention by etching away the grown metal and etching the through portion at the terminal portion of the upper transistor to retreat the side wall of the through portion at the terminal portion of the upper transistor. .

[Action]

In the present invention, the terminal of the upper transistor and the terminal of the lower transistor are connected by one contact hole. Thus, the area required for the wiring can be reduced. Further, since the side wall of the penetrating portion of the contact hole in the terminal of the upper transistor is recessed, the contact area between the terminal of the upper transistor and the metal buried in the contact hole is increased, and the contact resistance in this portion is reduced. be able to.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 (a) to 1 (d) are sectional views in the order of steps for explaining a first embodiment of the present invention.

In the present embodiment, an example will be described in which the source / drain semiconductor layers of the upper transistor and the source / drain diffusion layers of the lower transistor are connected.

First, a gate insulating film, a source / drain diffusion layer 3a, and a lower layer composed of a gate electrode 4 partially extending on the field oxide film 2, are formed on a silicon substrate 1 having an element isolation region defined by a field oxide film 2. A transistor is formed. Next, an interlayer insulating film 5 made of, for example, SiO ₂ is deposited on the entire surface of the silicon substrate 1. A gate insulating film, source / drain semiconductor layers 6,
An upper layer transistor of an SOI structure including a gate electrode 7 made of polycrystalline silicon, a part of which extends on the interlayer insulating film 5, is formed. Further, the upper transistor, the interlayer insulating film 5
Over to 0.1~0.5μm deposited for example an insulation film 8a formed of SiO ₂ [Fig. 1 (a)].

Next, through-holes of the contact holes are formed in the insulating film 8a by anisotropic dry etching using the photoresist film 9 as a mask. Further, by isotropic dry etching using sulfur hexafluoride, nitrogen trifluoride or the like, the source / drain semiconductor layer 6 of the upper transistor is recessed by 0.3 to 0.8 μm from the side wall of the through-hole of the contact hole of the insulating film 8a. A penetrating portion of the contact hole having the formed side wall is formed (FIG. 1B).

Again, by performing anisotropic dry etching,
A penetrating portion of the contact hole of the interlayer insulating film 5 is formed.
Thereafter, the photoresist film 9 is peeled off. At this stage,
The shape of the contact hole extending from the uppermost insulating film 8a to the source / drain diffusion layer 3a of the lower transistor is completed [FIG. 1 (c)].

Next, tungsten 10a is grown and buried in the contact hole using selective vapor deposition [FIG. 1 (d)].

At the penetrating portion of the contact hole provided in the source / drain semiconductor layer 6 of the upper transistor, selective growth of tungsten occurs because the side wall surface is made of silicon.
However, when tungsten growth occurs due to a supply-controlled reaction as in the case of silane reduction selective tungsten CVD, gas wraparound is poor at the penetrating portion of the recessed contact hole provided on the source / drain semiconductor layer 6 of the upper transistor. The growth rate here is smaller than the growth rate of tungsten on the surface of the source / drain diffusion layer 3a at the bottom of the contact hole.

Therefore, when the tungsten grown from the side wall of the through-hole provided in the source / drain semiconductor layer 6 of the upper transistor fills the recessed portion of the through-hole, the tungsten grown from the bottom of the contact hole is sufficiently grown. . Therefore, even if the tungsten growth is continued as it is, a cavity does not remain in the through portion provided in the source / drain semiconductor layer 6 of the upper transistor.

2 (a) to 2 (c) are sectional views in the order of steps for explaining a second embodiment of the present invention.

Also in the present embodiment, a case where the source / drain semiconductor layers of the upper transistor and the source / drain diffusion layers of the lower transistor are connected will be described as an example.

First, the structure up to the structure shown in FIG. 1A is formed in the same manner as in the first embodiment, and then a photoresist film (not shown)
A contact hole reaching the source / drain diffusion layer 3a of the lower transistor is formed by anisotropic dry etching using as a mask. Subsequently, the photoresist film is stripped [FIG. 2 (a)]. At this stage, the recessed portion in the side wall is not formed in the contact hole.

Next, when tungsten is grown by selective vapor deposition, tungsten 10b and tungsten 10b are formed on the contact hole penetrating the source / drain semiconductor layer 6 of the upper transistor and the bottom of the contact hole formed by the surface of the source / drain diffusion layer 3a of the lower transistor. Tungsten 10
c grows. When the growth of the tungsten 10b progresses and the contact hole is closed at the penetrating portion of the source / drain semiconductor layer 6 of the upper transistor, the growth of the tungsten 10c stops and a cavity is formed in the penetrating portion of the interlayer insulating film 5 of the contact hole [ FIG. 2 (b)].

Subsequently, isotropic dry etching is performed using sulfur hexafluoride, nitrogen trifluoride, or the like. The tungsten 10b is removed by this etching. On the other hand, although the etching of the tungsten 10c slightly progresses, the change in the shape is slight. After the removal of the tungsten 10b, the etching of the exposed surface of the source / drain semiconductor layer 6 of the upper transistor proceeds, and the side wall of the through-hole of the source / drain semiconductor layer 6 of the upper transistor in the contact hole recedes. The shape of the contact hole is the same as that of the first embodiment (FIG. 2 (c)).

When the exposed surface of the source / drain semiconductor layer 6 is etched, the presence of the tungsten 10c protects the source / drain diffusion layer 3a from this etching.

Next, tungsten is again grown by selective vapor deposition to obtain the structure shown in FIG. 1D in the first embodiment. At this time, no cavity is formed inside the contact hole for the same reason as shown in the first embodiment.

In the first and second embodiments, the source / drain semiconductor layers of the upper transistor and the source / drain
Although the case of connecting to the drain diffusion layer has been described,
The combination of the connection terminals of the upper and lower transistors is not limited to this.

In the first and second embodiments, a silicon semiconductor device has been described. However, another semiconductor device such as GaAs may be used. Further, although tungsten is used as the selective vapor deposition metal, other metals, alloys, or compounds may be used.

〔The invention's effect〕

As described above, according to the present invention, in the SOI transistor stacked semiconductor device and the method of manufacturing the same, the connection wiring of the upper layer transistor and the lower layer transistor can be performed in one contact hole. In addition, the need for the formation process, a plurality of wiring metal layers and the formation process is eliminated, and the space dedicated to the connection wiring can be minimized.

[Brief description of the drawings]

1 (a) to 1 (d) are cross-sectional views in the order of steps for explaining a first embodiment of the present invention, and FIGS. 2 (a) to 2 (c) show a second embodiment of the present invention. FIG. 3 is a cross-sectional view of a conventional SOI transistor laminated semiconductor device for explaining the steps in order of steps. 1 .... silicon substrate, 2 .... field oxide film, 3, 3a ...
... Source / drain diffusion layers, 4,7 ... Gate electrodes, 5 ...
... Interlayer insulating film, 6 ... Source / drain semiconductor layer, 8,8a
…… Insulating film, 9 …… Photoresist film, 10,10a, 10b, 10c
…… Tungsten, 11,12 …… Aluminum.

Claims (3)

(57) [Claims] 1. A lower transistor comprising a gate insulating film, a source / drain diffusion layer, a gate electrode extending on the field oxide film on a semiconductor substrate having an element isolation region defined by a field oxide film, and an interlayer insulating film. An SOI-structure upper-layer transistor including a gate insulating film, a source / drain semiconductor layer, and a gate electrode extending on the interlayer insulating film on a semiconductor layer formed on the semiconductor substrate through the upper layer transistor; An SOI transistor laminated semiconductor device comprising a deposited insulating film, wherein the gate electrode or the source / drain semiconductor layer penetrates the insulating film and extends over the interlayer insulating film in the upper transistor. A portion extending through the interlayer insulating film and extending on the field oxide film in the lower transistor A contact hole reaching the gate electrode or the source / drain diffusion layer, and a contact hole in the portion of the upper-layer transistor having a side wall recessed from a side wall of the contact hole in another portion; The gate electrode or the source / drain semiconductor layer of the upper transistor is connected to the gate electrode or the source / drain diffusion layer of the lower transistor by a metal embedded in the contact hole. SOI transistor stacked semiconductor device characterized by the above-mentioned. 2. The SOI transistor stacked semiconductor device according to claim 1, wherein a mask pattern of said contact hole is formed by a photoresist film, and said insulating film is etched using said photoresist film as a mask. Forming a recessed side wall in a predetermined portion of the upper layer transistor by dry etching, forming a through hole in the interlayer insulating film by anisotropic dry etching, and forming the contact hole; Embedding the metal in the contact hole by a growth method. A method for manufacturing an SOI transistor stacked semiconductor device, comprising: 3. The SOI transistor stacked semiconductor device according to claim 1, wherein: a step of forming a mask pattern of the contact hole with a photoresist film; and an anisotropic dry etching using the photoresist film as a mask. Forming a contact hole in the insulating film, the predetermined portion of the upper transistor, and the interlayer insulating film, the contact hole having a penetrating portion having the same side wall as the upper surface of the contact hole; Depositing the metal on the side wall of the transistor; removing the metal deposited on the side wall of the upper layer transistor in the contact hole by isotropic dry etching; etching the side wall of the upper layer transistor; After the sidewalls in the upper transistor A method for manufacturing a SOI transistor stacked semiconductor device, comprising: a step of recessing; and a step of embedding the metal in the contact hole by selective vapor deposition.