JPH02150064A - Electrode structure for gallium arsenide field effect transistor - Google Patents

Abstract

PURPOSE:To prevent generation of an Al2O3 layer and to prevent the deterioration, etc., in FET characteristics due to sintering by forming a thin Ni layer on an upper of an Al electrode. CONSTITUTION:A n<+>-type layer 22 as a source.drain diffused layer, an n-type layer 23 as a channel layer are formed on a substrate 21, and an AuGe ohmic electrode 24 is formed as source, drain electrode on the layer 22. Then, the whole surface is covered with regist 25, and an opening 26 having an inverted taper is formed on the layer 23 as the channel layer from above. Thereafter, the whole surface is formed with a multilayer film made of a Ti layer 27, an Al layer 28 and an Ni layer 29, and the regist 25 is thereafter removed by a lift-off method. The layers 27 and 28 are Schottky electrode layers in the multilayer film remaining as a gate electrode, and the layer 29 is to prevent generation of an Al2O3 layer on the top of the layer 28.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to the electrode structure of a semiconductor device, and particularly to the structure of a gate electrode in a gallium arsenide field effect transistor (hereinafter referred to as GaAsPET).

(Prior art) Conventionally, GaAsFETs are MES (Metal-Semi
Since the semiconductor device has a Schottky structure, its gate electrode is formed directly on the GaAs substrate using a Schottky structure.

Various gate electrodes have been developed to have this Schottky structure, but in the case of GaAs analog devices, AJ-based electrodes are the mainstream.

As an example of a GaAsFET having this Al-based electrode,
GaAsFET with Ti/A I gate electrode structure
The manufacturing method will be explained using FIG. 2.

First, an N9 layer 2 as a source/drain diffusion layer and an O layer 3 as a channel layer are formed on a GaAa substrate 1 [see FIG. 2(a)].

Next, Au was used as the upper source and drain electrodes on the n layer.
A Ge-based ohmic electrode 4 is formed [see FIG. 2(b)].

Next, a resist 5 is applied on the GaAs 1 plate 1, and an opening 6 is formed on the 1 layer 3 by a photolithography process. At this time, the opening 6 has a reverse taper due to the resist 5 [see FIG. 2(c)].

Next, Ti/Ap was continuously deposited using a vacuum evaporation method, and TiJ! ii7, An! Form Ji8 [Fig. 2 (
See d)].

Thereafter, the resist 5 is removed using a solvent. Then, along with the resist 5, TiF17 on the resist 5,
The A1 layer 8 is also removed, and these Ti layers 7°AN layers 8 are
The electrode remains only on the 0 layer 3 and on the electrode winding pad. (This electrode forming process using an organic solvent will be referred to as a lift-off method hereinafter) [see FIG. 2(e)].

Next, an insulating film 9 is formed as a protective film over the entire surface of the GaAs substrate 1 (see FIG. 2(f)).

Thereafter, a photolithography process is performed to form a hole in the insulating film 9 on the pad portion for conduction with the wiring electrode, and the insulating IIW 9 is removed by reactive ion etching to form a contact hole.

Next, a resist pattern for wiring electrodes is formed using a process similar to the photolithography process for forming gate electrodes [Figure 2 (g
)reference〕.

After that, Ti, PL, and Au were successively deposited using a vacuum evaporation method, and then a Ti layer 10 was formed using a lift-off method.
Form a wiring electrode consisting of a PT layer 11 and a dielectric layer 12 [
See Figure 2 (h)].

At that time, in order to obtain sufficient electrical contact between the gate electrode and the wiring, A1 wet etching with dilute acid is performed before wiring deposition, and after lift-off, heating is performed at around 400°C to complete the process [Figure 2] (+) see].

(Problem to be solved by the invention) However, the above-mentioned conventional Ti/A 1! The gate electrode structure had the following problems.

(1) Ti/A gate electrode 1. A7! The layer is very susceptible to oxidation, resulting in the formation of an A J zoz layer.

(2) To solve the above problem, etching is performed using dilute acid, but it is difficult to remove A1zo3N sufficiently.

(3) In sintering after wiring electrode formation, sufficient electrical contact cannot be obtained unless the temperature is raised to around 400°C, but heating to such a temperature will cause the GaAs substrate and the gate electrode Ti/A I N This reaction occurs, and the Schottky characteristics of the gate and, ultimately, the FET characteristics deteriorate. In other words, Aj! whose top layer is made of AI! .

When using a gate metal such as Ti/A 12 or Mo/^2 and forming wiring electrodes by a lift-off method,
It is sometimes difficult to achieve both good electrical contact between the gate and wiring and good Schottky characteristics of the gate.

The present invention is directed to the above-mentioned Aj! ! Preventing the occurrence of layer 03,
Moreover, it is an object of the present invention to provide a stable electrode structure for a gallium arsenide field effect transistor that prevents deterioration of FET characteristics due to sintering and is suitable for mass production.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a GaAsFET using an AI-based electrode, in which a single thin layer is formed above the Aff-based electrode.

The thickness of the Ni layer is preferably 10 Å or more and 100 Å or less.

(Function) According to the present invention, as described above, since a thin Ni layer is formed on the upper part of the Al zOs
It prevents the formation of layers, ensures electrical contact between the ^l-based gate electrode and wiring, which was difficult in the past, and also reduces the sintering temperature to reduce F[! Deterioration of T characteristics can be prevented.

Furthermore, by making the Ni layer very thin (20 to 50 layers), it is possible to suppress the occurrence of hillocks peculiar to AN, and it is possible to form an electrode with good morphology (flattened). .

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a cross-sectional view of a GaAsPET manufacturing process showing an embodiment of the present invention.

This embodiment will be explained using a Ti/Aβ/Ni gate structure as an example.

First, a 00 layer 22 as a source/drain diffusion layer and a 1 layer 23 as a channel layer are formed on a GaAs substrate 21 [see FIG. 1(a)].

Next, A
Forming the uGe-based ohmic electrode 24 [Fig. 1(b)]
reference〕.

Next, a resist 25 is applied to the entire surface of the GaAs substrate 21, and then on the 0 layer 23 as a channel layer.
Opening 2 that has a reverse taper due to the normal photolithography process
6 [see FIG. 1(c)].

Next, continuous evaporation is performed on the entire surface of the GaAs substrate 21 by a vacuum evaporation method, and Til! (200 people) 27. Al1
N (4000 people) 28, Ni1W (20 people) 29
[See FIG. 1(d)].

Thereafter, the resist 25 is removed by a lift-off method.

Then, together with the resist 25, the multilayer film consisting of TiJi 27 to NiN 29 on the 3-layer resist 25 is removed, and this multilayer film remains on the GaAs substrate 21 as an electrode only on the nJi 23 and the gate electrode conduction pad.
See figure (e)].

Here, in the multilayer film remaining as the gate electrode, the Ti layer 27
and AI layer 2 is the Schittky electrode layer, and Ni layer 2 is the Schittky electrode layer.
9 is Aj at the top of A1 layer 28! ,0. This is to prevent the formation of layers. At this time, the Ni layer 29 is 10 to 10
A value of 0 is good, and if the thickness is greater than that, it may cause FB deterioration due to Ni reaction and oxidation, so care must be taken.

Also, since the Ni layer 29 is thin, at this time, AIJ! ! 28
There is a possibility that they are not continuous on the top and are scattered like islands, but there is no particular problem.

Next, an insulating film 30 is formed as a protective film over the entire surface of the GaAs substrate 21 [see FIG. 1(f)].

Thereafter, a photolithography process for making holes is performed on the insulating film 30 on the bunt part for conduction with the wiring electrode, and the insulating film 30 is removed by reactive ion etching, and the contact hole 31 is removed by reactive ion etching.
[See Figure 1 (g)].

Next, a wiring electrode resist pattern is formed using a process similar to the gate electrode forming photolithography process. After that, the wiring Ti layer 32, PT layer 33, ^U
Form a multilayer film consisting of layer 34 [see FIG. 1(h)]
.

Next, using the lift-off method, wiring electrodes are formed in the same way as for forming gate electrodes, and the process is completed by sintering at approximately 300°C, which is much lower than the conventional sintering temperature [see Figure 1 (1)] .

Furthermore, this electrode structure can be used not only as a gate electrode but also as a lower wiring electrode of a multilayer wiring.

In addition, in the above process, Ti/A I /Ni was taken as an example, but this process is A j! /Ni, Mo
The present invention can be similarly applied to gate electrode structures such as /A I /Ni.

Furthermore, Afi-based electrodes can be roughly classified into alloy films and multilayer films. As the alloy film, for example, Aj! −
Cu, Al-3i, as a multilayer film, for example, M
There are o/Al, ^β, etc., and the present invention can also be applied to these Al-based electrodes.

In this embodiment, dilute acid etching before forming the wiring electrodes is not particularly necessary, but may be performed, in which case electrical contact can be obtained with lower temperature sintering.

Further, in an embodiment of the present invention, GaAsFESFE
Although the above case has been described, it can be easily applied to other compound semiconductors, element semiconductors, or semiconductor elements having β-based wiring on an insulator.

Note that the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

(Effects of the Invention) As described above in detail, according to the present invention, a thin Ni layer is formed on the top of the Al-based electrode, so that
Prevents the formation of β201 layer, which is difficult to achieve in the past.
Electrical contact between the f-type electrode and the wiring can be ensured, and at the same time, deterioration of FET characteristics can be prevented by lowering the sintering temperature.

Further, by making the thickness of the upper NiN layer 10 Å or more and 100 Å or less, it is possible to suppress the occurrence of hillocks peculiar to the A1 layer, and it is possible to form an electrode with good morphology.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of the manufacturing process of a GaAsFET showing an embodiment of the present invention, and FIG. 2 is a cross-sectional view of the manufacturing process of a conventional GaAsFET. 21...GaAsJJ board, 22...n''FJ (source/drain diffusion layer), 23...n layer (channel layer)
, 24... AuGe-based ohmic electrode (source/drain electrode), 25... resist, 26... opening,
27...Ti layer (200 people), 28...A1 layer (
4000 people), 29... Ni layer (20 people), 30...
・・Dark rim, 31 ・Contact hole, 32・・
-Ti layer, 33...ptl, 34...Au layer. Patent applicant Oki Electric Industry Co., Ltd.

Claims (2)

[Claims] (1) An electrode structure of a gallium arsenide field effect transistor using an aluminum-based electrode, characterized in that a nickel layer is formed on the top of the aluminum-based electrode. (2) The electrode structure of a gallium arsenide field effect transistor according to claim 1, wherein the nickel layer has a thickness of 10 Å or more and 100 Å or less.