JPS59194451A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS59194451A
JPS59194451A JP6855083A JP6855083A JPS59194451A JP S59194451 A JPS59194451 A JP S59194451A JP 6855083 A JP6855083 A JP 6855083A JP 6855083 A JP6855083 A JP 6855083A JP S59194451 A JPS59194451 A JP S59194451A
Authority
JP
Japan
Prior art keywords
insulating film
film
plasma cvd
resistance heating
deposited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6855083A
Other languages
Japanese (ja)
Inventor
Yoshinobu Kadowaki
門脇 好伸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6855083A priority Critical patent/JPS59194451A/en
Publication of JPS59194451A publication Critical patent/JPS59194451A/en
Pending legal-status Critical Current

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Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To reduce the characteristic change of an active region as large as possible by forming an interlayer insulating film in 2-layer structure having the first insulating film made of a thin deposited insulating film due to resistance heating and the second insulating film which is sufficiently thick due to a plasma CVD method. CONSTITUTION:Electrodes 1, 2, 4 are formed on a semi-insulating GaAs substrate, the first insulating film 5a made of thin silicon oxidized film due to resistance heating deposition is accumulated, and the second insulating film 5b made of sufficiently thick silicon nitrided film is accumulated by plasma CVD method on the entire surface. Further, a photoresist layer 7 is covered and a window 8 is patterned thereon by the normal photolithography the film 5 of 2-layer structure is selectively etched, opened at a hole 9, and wiring metal 6 is formed on the second insulating film 5b.

Description

【発明の詳細な説明】 −〔発明の技術分野〕 この発明は半導体装置の製造方法、特に能動領域の特性
変化を低減した層間絶縁膜の形成方法に関するものであ
る。
Detailed Description of the Invention - [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming an interlayer insulating film that reduces changes in characteristics of an active region.

〔従来技術〕[Prior art]

砒化ガリウム(以下、GaAsと略す)集積回路を例と
して、従来の層間絶縁膜を用いた配線形成後の半導体装
置の構成を第1図に示す。すなわち、この第1図におい
て、半絶縁性Gaps基板上には、ソース電極(1)お
よびドレイン電極(2)と、これらに挾まれたチャネル
領域(3)上にあってゲート電極(4)とを形成したの
ち、これらの全面にプラズマい■法、あるいはスパッタ
蒸着法−によシ、シリコン窒化膜(SiaN+ ) 、
またはシリコン酸化膜(8iσ0などからなる層間絶縁
膜(5)を堆積し、かつ通常のホトリックラフイにより
、ドレイ/電極(2)上の層間絶縁膜(5)を選択的に
開孔でせ、このドレイン電極(2)に接続する配線金属
(6)を形成したものである。
Taking a gallium arsenide (hereinafter abbreviated as GaAs) integrated circuit as an example, FIG. 1 shows the structure of a semiconductor device after wiring is formed using a conventional interlayer insulating film. That is, in FIG. 1, on the semi-insulating Gaps substrate, there are a source electrode (1), a drain electrode (2), and a gate electrode (4) on a channel region (3) sandwiched between these. After forming a silicon nitride film (SiaN+), a silicon nitride film (SiaN+),
Alternatively, an interlayer insulating film (5) made of a silicon oxide film (8iσ0, etc.) is deposited, and holes are selectively opened in the interlayer insulating film (5) on the drain/electrode (2) by ordinary photolithography. A wiring metal (6) connected to the electrode (2) is formed.

しかし乍らこのような従来構成の場合には、眉間絶縁膜
(5)をプラズマCVD法、あるいはスパッタ蒸着法に
よシ堆積しているために、例えば抵抗加熱による蒸着絶
縁膜に比較して、その膜質が緻密で面内均一性が高く、
信頼性に優れている反面。
However, in the case of such a conventional configuration, since the glabellar insulating film (5) is deposited by plasma CVD or sputter deposition, it is difficult to deposit the glabellar insulating film (5) compared to, for example, a vapor-deposited insulating film by resistance heating. The film quality is dense and has high in-plane uniformity,
On the other hand, it has excellent reliability.

その機構においてプラズマ反応現象を応用していること
から、堆積時に基板表面に多くのダメージを発生させ、
例えばチャネル領域(3)の表面不純物濃度を著るしく
低減きせる結果、これらのソース。
Because the mechanism uses a plasma reaction phenomenon, it causes a lot of damage to the substrate surface during deposition.
For example, these sources result in a significant reduction in the surface impurity concentration of the channel region (3).

ドレイン、およびゲート各電極(1) 、 (21、お
よび(4)からなるGaAs電界効果トランジスタにあ
っては、飽和ドレイン電流Idssが層間絶縁膜堆積後
、大幅に低減してしまうという不都合があった。
A GaAs field effect transistor consisting of drain and gate electrodes (1), (21, and (4)) has the disadvantage that the saturated drain current Idss is significantly reduced after the interlayer insulating film is deposited. .

〔発明の概要〕[Summary of the invention]

この発明は従来のこのような欠点に鑑み、層間絶縁膜を
、抵抗加熱による蒸着絶縁薄膜からなる第1の絶縁膜と
、これに続いてプラズマCVD法あるいはスパッタ蒸着
法による充分に厚い第2の絶縁膜との2層構造に形成き
せることによって、能動領域の特性変化を極力低減させ
たものである。
In view of these conventional drawbacks, the present invention has developed an interlayer insulating film by forming a first insulating film consisting of a thin insulating film deposited by resistance heating, followed by a sufficiently thick second insulating film by plasma CVD or sputter deposition. By forming the active region into a two-layer structure with an insulating film, changes in the characteristics of the active region are minimized.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明方法の一実施例につき、第2図(a)な
いしくd)を参照して詳細に説明する。
Hereinafter, one embodiment of the method of this invention will be described in detail with reference to FIGS. 2(a) to 2d).

第2図(a)ないしくd)はこの実施例方法を製造工程
順に示している。すなわち、前記従来例と同様にして、
半絶縁性GaAs基板上にソース、ドレイン、およびゲ
ート各電極(1)、 (21、および(4)を形成した
上で、これらの全面を被覆するようにして、抵抗加熱蒸
着によるシリコン酸化1(SiQ2)の薄膜からなる第
1の絶縁膜(5a)を堆積きせ(同図(a))、続いて
その全面上に従来と同様のプラズマCVD法、あるいは
スパッタ蒸着法により、第1の絶縁膜(5a)よシも充
分に厚いシリ2ン窒化膜(SiaN4) 、またはシリ
コン酸化膜(Sing)などからなる第2の絶縁膜(5
b)を堆積させ(同図(b))、さらにその上に通常の
ホトリソグラフィによシ、ホトレジスト層(7)の被着
と、そのドレイン電極(2)対応部の窓開口(8)のパ
ターニングとをなしく同図(C) ) 、かつこのホト
レジスト層(力をマスクにした乾式、あるいは湿式エツ
チングによシ前記2層構造による眉間絶縁7!(51を
選択的にエツチングして開口(9)させると共に、この
開口(9)を通してドレイン電極(2)と接続する配線
金属(6)を、第2の絶縁膜(5b)上に形成したもの
である(同図(d))。
FIGS. 2(a) to 2d) show this embodiment method in the order of manufacturing steps. That is, similarly to the conventional example,
After forming source, drain, and gate electrodes (1), (21, and (4)) on a semi-insulating GaAs substrate, silicon oxide 1 ( A first insulating film (5a) made of a thin film of SiQ2) is deposited (see figure (a)), and then the first insulating film is deposited on the entire surface by the conventional plasma CVD method or sputter deposition method. (5a) A second insulating film (5a) made of a sufficiently thick silicon nitride film (SiaN4) or silicon oxide film (Sing).
b) is deposited (FIG. 2(b)), and then a photoresist layer (7) is deposited on top of it by ordinary photolithography, and a window opening (8) corresponding to the drain electrode (2) is formed. The glabella insulation 7! (51) of the two-layer structure is selectively etched to form an opening ( 9), and a wiring metal (6) connected to the drain electrode (2) through this opening (9) is formed on the second insulating film (5b) (FIG. 9(d)).

従ってこの実施例方法の場合には、眉間絶縁膜を2層構
造にし、基板上に直接被着される第1の絶縁膜(5a)
として、抵抗加熱蒸着によるシリコン酸化薄膜を用いて
いるために、同膜形成時に基板表面層に誘起される結晶
ダメージが極めて少なく、また第1の絶縁膜(5a)上
の第2の絶縁膜(5b)として、プラズマCVD法、あ
るいはスパッタ蒸着法によシ厚膜形成しても、下層に第
1の絶縁膜(5a)があるために、これが表面層にダメ
ージを与える惧れがなくな)、結果的に眉間絶縁膜(5
)の形成前後での能動層の特性は殆んど変化せず、しか
も第1の絶縁膜(5a)単独ではみたされなかった緻密
で信頼性の高い層間絶1#膜(5)を得られるのである
。      ゛ 〔発明の効果〕 一以上詳述したようにこの発明方法によれば、基板結晶
層に直接被着する第1の絶縁膜として抵抗加熱蒸着によ
る薄膜を用い、かつその上に連続して均一性が高く緻密
で高信頼性のプラズマCVD法、あるいはスパッタ蒸着
法による第2の絶縁膜を厚く堆積して層間絶縁膜とした
ので、この絶縁膜形成前後での能動層の電気的特性の変
化を小さくでき、均一性、および信頼性を向上させ得る
特長がある。
Therefore, in the case of this embodiment method, the glabella insulating film has a two-layer structure, and the first insulating film (5a) is directly deposited on the substrate.
As a silicon oxide thin film formed by resistance heating vapor deposition is used, crystal damage induced on the substrate surface layer during the formation of the film is extremely small, and the second insulating film (5a) on the first insulating film (5a) is 5b), even if a thick film is formed by plasma CVD or sputter evaporation, there is no risk of this damaging the surface layer because there is the first insulating film (5a) in the lower layer) As a result, the glabella insulating film (5
) The characteristics of the active layer before and after the formation of the active layer hardly change, and moreover, it is possible to obtain a dense and highly reliable layer interlayer 1# film (5) that could not be satisfied by the first insulating film (5a) alone. It is. [Effects of the Invention] As described above in detail, according to the method of the present invention, a thin film formed by resistance heating vapor deposition is used as the first insulating film directly deposited on the substrate crystal layer, and a thin film is continuously and uniformly deposited on the first insulating film. Since the second insulating film is thickly deposited using a highly precise, highly reliable plasma CVD method or sputter evaporation method to form an interlayer insulating film, changes in the electrical characteristics of the active layer before and after the formation of this insulating film can be avoided. It has the advantage of being able to reduce the size and improve uniformity and reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例による層間絶縁膜を用いた半導体装置を
示す断面図、第2図(a)ないしくd)はこの発明方法
の一実施例による層間絶縁膜構造を得るための製造工程
を順次に示す断面図であ、る。 (1)・・Φ・ソース電極、(2)・・・・ドレイン電
極、(4)・・・・ゲート電極、(5)・・・・層間絶
縁膜、(5a)、(5b) 11 @ * @第1.第
2の絶縁膜、(6)・・・・配線金属。 代理人 大岩増雄
FIG. 1 is a sectional view showing a semiconductor device using a conventional interlayer insulating film, and FIGS. 2(a) to 2d) show manufacturing steps for obtaining an interlayer insulating film structure according to an embodiment of the method of the present invention. FIG. (1)...Φ source electrode, (2)...drain electrode, (4)...gate electrode, (5)...interlayer insulating film, (5a), (5b) 11 @ * @1st. Second insulating film, (6)...wiring metal. Agent Masuo Oiwa

Claims (1)

【特許請求の範囲】[Claims] 半導体基板面にソース、ドレイン、およびゲート電極を
形成させ、かつこれらの各電極を層間絶I#膜によシ被
覆きせる半導体装置において、前記層間絶縁膜を2層構
造にするため、前記基板上に抵抗加熱蒸着によって、薄
膜からなる第1の絶縁膜を形成する工程と、この第1の
絶縁膜上にプラズマCVD法、あるいはスパッタ蒸着法
などによって、厚膜からなる第2の絶縁膜を形成する工
程とを含むことを特徴とする半導体装置の製造方法。
In a semiconductor device in which source, drain, and gate electrodes are formed on the surface of a semiconductor substrate, and each of these electrodes is covered with an interlayer insulating I# film, in order to make the interlayer insulating film have a two-layer structure, A step of forming a first insulating film made of a thin film by resistance heating vapor deposition, and a second insulating film made of a thick film is formed on this first insulating film by a plasma CVD method, a sputter deposition method, etc. A method for manufacturing a semiconductor device, comprising the steps of:
JP6855083A 1983-04-18 1983-04-18 Manufacture of semiconductor device Pending JPS59194451A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6855083A JPS59194451A (en) 1983-04-18 1983-04-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6855083A JPS59194451A (en) 1983-04-18 1983-04-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS59194451A true JPS59194451A (en) 1984-11-05

Family

ID=13376975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6855083A Pending JPS59194451A (en) 1983-04-18 1983-04-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59194451A (en)

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