JP2838932B2 - Field effect type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect type semiconductor device formed of a semiconductor film such as polycrystalline silicon, and more particularly to a structure of a source / drain diffusion layer of a MIS (Metal Insulator Semiconductor) type transistor.

[0002]

2. Description of the Related Art FIG. 13 is a cross-sectional view showing a conventional semiconductor device described in, for example, the Technical Report of the Institute of Electronics, Information and Communication Engineers (Vol. 91, No. 66). FIG. 2 is a cross-sectional view illustrating a configured MIS transistor as an example. In the figure, 1 is a single crystal silicon substrate having a silicon oxide film 2 formed on the entire surface, 3 is a gate electrode formed on this substrate, 4 is a gate insulating film, 5 is a channel region and a source / drain diffusion layer. The gate electrode 3, the gate insulating film 4, and the polycrystalline silicon film 5 constitute a MIS transistor. Reference numeral 6 denotes an insulating film. The insulating film 6 is opened to form a diffusion layer electrode 7, and the diffusion layer electrode is taken out to the surface of the semiconductor device. Reference numeral 8 denotes a surface protective film of the MIS transistor.

Next, a conventional method for manufacturing a semiconductor device will be described with reference to FIGS. A gate electrode material, for example, a polycrystalline silicon film is deposited on a single crystal silicon substrate 1 having a silicon oxide film 2 formed on the surface by a chemical vapor deposition method (hereinafter referred to as a CVD method), and the gate electrode material is formed by, for example, photolithography. Resist pattern 50
Is formed, and the gate electrode 3 is formed by anisotropic etching using the resist pattern 50 as an etching mask (FIG. 14). Next, after the resist pattern 50 is removed, a silicon oxide film serving as the gate insulating
A VD method is formed over the entire surface to a thickness of about 40 nm, and a polycrystalline silicon film 5 constituting an active layer of the MIS transistor is formed to a thickness of about 35 nm by, for example, a CVD method (FIG. 15).

Next, a resist pattern 60 covering the channel region of the MIS transistor is formed by, for example, photolithography, and using this resist pattern 60 as a mask, ion species 80 of a desired polarity are formed in the polycrystalline silicon film 5. To form a diffusion layer serving as a source and a drain of the MIS transistor,
A MIS transistor having a desired polarity is formed (FIG. 1)
6). After the formation of this MIS transistor, an insulating film 6 such as a silicon oxide film is formed on the surface, and a resist pattern 70 for forming a connection hole for forming a gate electrode and a diffusion layer electrode is formed by, for example, photolithography. (FIG. 17).

[0005] Using the resist pattern 70 as an etching mask, the insulating film 6 is etched by anisotropic etching to form a connection hole 90 (FIG. 18). Next, after the resist pattern 70 is removed, a gate electrode and a diffusion layer electrode are formed in the connection hole 90 using a metal material such as an aluminum alloy, and the surface is protected by, for example, a silicon nitride film by a plasma CVD method. By forming the film, the conventional semiconductor device shown in FIG. 13 can be obtained.

[0006]

The conventional semiconductor device is configured as described above, and the polycrystalline silicon film 5 constituting the active layer of the MIS transistor has a channel region 1
00 and the diffusion layer region 200 have the same thickness,
Moreover, its film thickness is thin. Therefore, there is a problem that it is difficult to stably open the connection hole when forming the connection hole for forming the diffusion layer electrode 7 because there is little room for anisotropic etching. Further, when a metal electrode is formed in the connection hole, the contact area between the polycrystalline silicon film 5 and the metal electrode is small, and the opening state of the connection hole is affected. was there.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and can stably form a connection hole for taking an electrode in a polycrystalline silicon film constituting an active layer of a MIS transistor. It is another object of the present invention to provide a field-effect semiconductor device capable of stabilizing the resistance of the connection hole and reducing the resistance.

[0008]

A field effect type semiconductor device according to the present invention comprises: an insulating film formed on a substrate; a first semiconductor film formed on the insulating film to form a channel region; A gate electrode formed on the first semiconductor film and covered with a gate insulating film, electrically connected to the first semiconductor film, and sandwiching the gate electrode via the gate insulating film; A second semiconductor film formed on the insulating film, a third semiconductor film formed on the gate insulating film on the opposite side to the substrate with respect to the gate electrode and forming a channel region, A diffusion layer electrode disposed on both sides of the electrode and electrically connected to the first and third semiconductor films, wherein the first semiconductor film is used as an active layer ; The semiconductor film is used as a diffusion layer region and has the above gate electrode. A first transistor, above the third semiconductor film an active layer, in which a second transistor having the gate electrode was constructed.

[0009]

The field effect type semiconductor device according to the present invention has an MI
Since the thickness of the diffusion layer region including at least the region for taking the diffusion layer electrode of the polycrystalline silicon film constituting the active layer of the S-type transistor is configured to be thicker than the thickness of the channel region,
When a connection hole for forming a diffusion layer electrode is opened, the connection hole can stop anisotropic etching in the middle of the polycrystalline silicon film having a thickness that constitutes the diffusion layer region, so that sufficient etching margin can be obtained. Because of this, the connection hole can be stably opened.
Further, the diffusion layer electrode formed for the connection hole comes into contact with the bottom surface and both side surfaces of the connection hole, so that the contact area increases, and the resistance of the diffusion layer can be reduced and stabilized. . Therefore, a high-speed semiconductor device can be formed stably.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. Embodiment 1 FIG. 1 is a main sectional view of a field-effect semiconductor device according to one embodiment of the present invention. In the figure, reference numerals 1 to 8 are the same as or correspond to those of the conventional semiconductor device. Reference numeral 9 denotes a second semiconductor film constituting an active layer of the present semiconductor device. The second semiconductor film 9 is thicker than the channel region 100 due to the polycrystalline silicon film 5 and the second semiconductor film 9 as the first semiconductor films. A diffusion layer region 200 is formed. An MIS structure is formed by the gate electrode 3, the gate insulating film 4, and the first semiconductor film 5.

The semiconductor device configured as described above is manufactured as follows. This will be described with reference to FIGS.
First, a second semiconductor film 9, for example, a polycrystalline silicon film is formed on a single crystal silicon substrate 1 having a silicon oxide film 2 formed on its surface to a thickness of about 200 nm by a CVD method.
A resist pattern 20 is formed by, for example, photolithography so as to open a region for forming the MIS structure of the IS type transistor. Using the resist pattern 20 as an etching mask, the polycrystalline silicon film 9 is etched by, for example, anisotropic etching (FIG. 3). In the figure, reference numeral 9a denotes a groove portion where the polycrystalline silicon 9 is etched.

Next, after removing the resist pattern 20, a first semiconductor film 5, for example, a polycrystalline silicon film, which becomes an active layer of the MIS transistor, is formed to a thickness of 40 nm by a CVD method.
It is formed thin with a film thickness of about m. Thereafter, the gate insulating film 4 of the MIS transistor is formed, for example, by a silicon oxide film by CVD.
It is formed to a thickness of about 40 nm by the method (FIG. 4).

Next, a gate electrode material, for example, a polycrystalline silicon film is formed thick by a CVD method and is buried in a groove for forming a MIS structure of the MIS transistor (FIG. 5). Next, by etching back the entire surface of the polycrystalline silicon film serving as the gate electrode material, the polycrystalline silicon film is buried only in the grooves for forming the MIS structure of the MIS transistor, and the gate electrode 3 is formed. Next, when forming a desired type of ion species 80, for example, NMOS, As
For example, if a PMOS is formed, B or the like is ion-implanted into the first semiconductor film 5 and the second semiconductor film 9 through the gate insulating film 4 to form a MIS transistor having a desired polarity. At this time, the source / drain diffusion layer region 200 of the MIS transistor is formed in a self-aligned manner with respect to the gate electrode 3 (FIG. 6).

Next, an insulating film 6 and a silicon oxide film are formed on the surface on which the MIS transistor is formed, for example, by a CVD method. Thereafter, a resist pattern 30 is formed, for example, by photolithography to open a connection hole for taking an electrode to the gate electrode 3 and the diffusion layer (FIG. 7).
Next, using the resist pattern 30 as an etching mask, the insulating film 6 is etched by anisotropic etching to form a connection hole 91 (FIG. 8). At this time, the etching may penetrate the first semiconductor film 5 and reach the second semiconductor film 9. Next, the resist pattern 30 is removed, and a gate electrode and a diffusion layer electrode are formed using a method similar to the conventional method.
By forming the surface protection film, the semiconductor device of the first embodiment shown in FIG. 1 can be obtained.

As described above, in the first embodiment, the MI
Since the thickness of the semiconductor film constituting the source / drain region 200 is made larger than the thickness of the semiconductor film constituting the channel region 100 of the S-type transistor, a connection hole is opened to take an electrode to the diffusion region. At this time, the etching margin of the anisotropic etching is improved, and the connection hole can be stably formed. Further, the etching for opening the connection hole may be stopped in the middle of the thick semiconductor film in the diffusion layer region 200. At this time, when the diffusion layer electrode 7 is formed, the etching is performed with the metal film of the diffusion layer electrode. Since the contact area of the diffusion layer with the semiconductor film increases, the resistance of the diffusion layer electrode decreases, and a stable diffusion layer resistance can be obtained. Further, since the thickness of the source / drain diffusion layer region 200 is large, the resistance of the source / drain diffusion layer itself is reduced, so that a high-speed and stable semiconductor device can be obtained.

Embodiment 2 FIG. 2 is a main sectional view of a field effect type semiconductor device showing a second embodiment according to the present invention. In the figure, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts. Reference numeral 10 denotes a second gate insulating film formed so as to cover the gate electrode 3 and the gate insulating film 4, and reference numeral 11 denotes a third semiconductor film formed so as to cover the second gate insulating film 10. It constitutes an active layer of a type transistor. At this time, the gate insulating film 4 and the first semiconductor film 5
Thus, the lower channel type MIS transistor is formed, and the upper channel type MIS transistor is formed by the second gate insulating film 10 and the third semiconductor film 11. An MIS transistor having a thick semiconductor film is formed on the upper and lower surfaces with respect to the gate electrode 3.

Next, the semiconductor device shown in the second embodiment thus constructed is manufactured as follows. This is shown in FIG.
This will be described with reference to FIGS. First, as shown in the manufacturing method of the first embodiment, a lower channel MIS transistor is formed according to FIGS. Thereafter, a second gate insulating film 10 such as a silicon oxide film is formed on the surface by CVD at a thickness of about 40 nm, and a third semiconductor film 11 is further formed on the surface,
1 is formed to a thickness of about 40 nm by a CVD method. As a result, an MIS structure is formed above the gate electrode 3 (FIG. 9).

Next, a resist pattern 40 covering the channel region 100 is formed by, for example, photolithography, and the resist pattern 40 is used as a mask to form an active layer of the MIS transistor formed above the gate electrode 3. A desired type of ion species 80 is implanted into the third semiconductor film 11 to be formed to form a MIS transistor having a desired polarity (FIG. 10).

After removing the resist pattern 40,
An insulating film 6 such as a silicon oxide film is formed by a CVD method so as to cover the third semiconductor film 11 (FIG. 11).
Next, a resist pattern 5 is used to open connection holes for connecting electrodes to the source / drain diffusion layers and the gate electrode.
0 is formed by, for example, photolithography, and a connection hole 91 is formed by anisotropic etching using the resist pattern 50 as an etching mask (FIG. 12). At this time, the anisotropic etching may penetrate through the first semiconductor film 5 and reach the second semiconductor film 9 having a large thickness.

Thereafter, the resist 50 is removed, and the metal electrode 7 is formed in the connection hole 91 in the same manner as in the prior art.
By forming the surface protection film 8, the semiconductor device of the second embodiment shown in FIG. 2 can be obtained.

As described above, in the second embodiment, the MIS transistor formed below the gate electrode 3 has a thickness smaller than the thickness of the semiconductor film forming the channel region.
Since the thickness of the semiconductor film constituting the source / drain regions has been increased, when opening a connection hole for taking an electrode to the diffusion layer region, the etching margin of anisotropic etching is improved, and the connection is stabilized. Holes can be drilled. Further, the etching for opening the connection hole may be stopped in the middle of the thick semiconductor film in the diffusion layer region. In this case, when the diffusion layer electrode is formed, the metal layer and the diffusion layer of the diffusion layer electrode are formed. Since the contact area with the semiconductor film constituting the structure is increased, the resistance of the diffusion layer electrode is reduced, and the diffusion layer electrode can be stabilized.

The source / drain diffusion layer region 200
Is thick, the resistance of the source / drain diffusion layers themselves is reduced. Further, in the MIS transistor formed above the gate electrode 3, when the connection hole is formed, the diffusion layer electrode is connected by contacting the side surface of the third semiconductor film 11. Therefore, the lower channel type MIS transistor and the upper channel type MIS transistor
Since two S transistors are formed, the drain current of the MIS transistor can be obtained accordingly, and the driving capability is improved, so that a high-speed and high-performance semiconductor device can be obtained.

[0023]

As described above, according to the present invention, in the field effect type semiconductor device, the thickness of the semiconductor film constituting the diffusion layer region is made larger than that of the semiconductor film constituting the channel region. The etching margin when opening a connection hole for taking an electrode is improved, the connection hole can be stably opened, and the resistance of the diffusion layer itself can be reduced. Further, the etching for opening the connection hole can be stopped in the middle of the thick semiconductor film forming the diffusion layer region, and when the metal electrode is buried, the contact area between the metal electrode and the semiconductor film increases. Therefore, a diffusion layer electrode having a low resistance can be obtained . In addition, since two channel regions are formed,
This has the effect of increasing the in-current and stably obtaining a high-speed and high-performance semiconductor device.

[Brief description of the drawings]

FIG. 1 is a main cross-sectional view showing a field-effect semiconductor device according to one embodiment of the present invention.

FIG. 2 is a main cross-sectional view showing a field-effect semiconductor device according to another embodiment of the present invention.

FIG. 3 is a sectional view showing one step of a method of manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 4 is a sectional view showing a step after the step in FIG. 3;

FIG. 5 is a sectional view showing a step after the step in FIG. 4;

FIG. 6 is a sectional view showing a step after the step in FIG. 5;

FIG. 7 is a sectional view showing a step after the step in FIG. 6;

FIG. 8 is a cross-sectional view showing a step after the step in FIG. 7;

FIG. 9 is a sectional view showing one step of a method of manufacturing a field-effect semiconductor device according to another embodiment of the present invention.

FIG. 10 is a sectional view showing a step after the step in FIG. 9;

FIG. 11 is a sectional view showing a step after the step in FIG. 10;

FIG. 12 is a sectional view showing a step after the step in FIG. 11;

FIG. 13 is a cross-sectional view showing a conventional field-effect semiconductor device.

FIG. 14 is a sectional view showing one step of a method of manufacturing a semiconductor device according to a conventional example.

FIG. 15 is a sectional view showing a step after the step in FIG. 14;

FIG. 16 is a sectional view showing a step after the step in FIG. 15;

FIG. 17 is a sectional view showing a step after the step in FIG. 16;

FIG. 18 is a sectional view showing a step after the step in FIG. 17;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Single crystal silicon substrate 2 Silicon oxide film 3 Gate electrode 4 Gate insulating film 5 First semiconductor film 6 Insulating film 7 Diffusion layer electrode 8 Surface protection film 9 Second semiconductor film 100 Channel region 200 Diffusion region

Claims (2)

(57) [Claims] 1. A field-effect semiconductor device comprising a semiconductor film, comprising: an insulating film formed on a substrate; and a first film formed on the insulating film and forming a channel region.
A gate electrode formed on the first semiconductor film and covered with a gate insulating film; and a gate electrode electrically connected to the first semiconductor film, via the gate insulating film. A second semiconductor film formed on the insulating film so as to sandwich the same; and a third semiconductor formed on the gate insulating film on the opposite side of the substrate with respect to the gate electrode and forming a channel region A diffusion layer electrode disposed on both sides of the gate electrode and electrically connected to the first and third semiconductor films; the first semiconductor film as an active layer ; A first transistor having the gate electrode, and a second transistor having the gate electrode using the third semiconductor film as an active layer. Field-effect semiconductor Location. 2. The field effect type semiconductor device according to claim 1, wherein one end of said diffusion layer electrode is provided in said second semiconductor film.
A field effect type semiconductor device characterized by being embedded .