JPH0828507B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0828507B2 JPH0828507B2 JP57041168A JP4116882A JPH0828507B2 JP H0828507 B2 JPH0828507 B2 JP H0828507B2 JP 57041168 A JP57041168 A JP 57041168A JP 4116882 A JP4116882 A JP 4116882A JP H0828507 B2 JPH0828507 B2 JP H0828507B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- thin film
- semiconductor device
- source
- silicon thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 29
- 229910052710 silicon Inorganic materials 0.000 claims description 29
- 239000010703 silicon Substances 0.000 claims description 29
- 239000010409 thin film Substances 0.000 claims description 28
- 239000010408 film Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Description
本発明はMOS型薄膜半導体装置の構造に関するもので
ある。The present invention relates to the structure of a MOS type thin film semiconductor device.
MOS型半導体装置でスイッチングトランジスタアレイ
を形成した液晶表示パネルはグラフィック表示装置を小
型化できる物として、携帯用機器の表示装置への活用が
注目されている。しかし、従来のスイッチングトランジ
スタアレイを有する液晶表示パネルでは、直射日光下及
び裏面から照射を行った場合にスイッチングトランジス
タのリーク電流が増大し、キャパシタに蓄積された電荷
が消失して表示機能が失われる欠点を有している。A liquid crystal display panel in which a switching transistor array is formed of a MOS type semiconductor device has been attracting attention as a display device of a portable device, as a graphic display device that can be miniaturized. However, in the liquid crystal display panel having the conventional switching transistor array, the leakage current of the switching transistor increases when the light is irradiated from the direct sunlight and the back surface, and the charge accumulated in the capacitor disappears to lose the display function. It has drawbacks.
本発明は、上記の薄膜半導体装置の光リーク特性を改
善して液晶表示パネルの特性を向上させることを目的と
する。It is an object of the present invention to improve the light leakage characteristics of the above thin film semiconductor device and improve the characteristics of the liquid crystal display panel.
本発明は、基板上に形成された半導体装置において、 互いに離間して島状に形成された第１シリコン薄膜か
らなる第１領域及び第２領域と、 該島状の第１領域及び第２領域の間及び上に形成され
た膜厚が1000オングストローム以下である第２シリコン
薄膜とを含み、 該半導体装置のチャンネル領域は該第２シリコン薄膜
の一部からなり且つ該第１領域及び第２領域の間に配置
されてなり、 該チャンネル領域上にはゲート絶縁膜を介してゲート
電極が配置されてなり、 該半導体装置のソース・ドレイン領域は該第１領域及
び第２領域と該第２シリコン薄膜の一部からなり、 該ソース・ドレイン領域は金属からなるソース配線及
びドレイン配線に電気的に接続されてなり、 該ソース・ドレイン領域の膜厚は、該チャンネル領域
の膜厚よりも厚く形成されてなることを特徴とする。According to the present invention, in a semiconductor device formed on a substrate, a first region and a second region made of a first silicon thin film formed in an island shape spaced apart from each other, and the island-shaped first region and the second region are formed. A second silicon thin film having a film thickness of 1000 angstroms or less formed between and above the channel region, the channel region of the semiconductor device being formed of a part of the second silicon thin film, and the first region and the second region. A gate electrode is disposed on the channel region via a gate insulating film, and the source / drain regions of the semiconductor device are the first and second regions and the second silicon region. The source / drain region is made of a part of a thin film, and the source / drain regions are electrically connected to a source wiring and a drain wiring made of metal. The thickness of the source / drain region is larger than that of the channel region. Is formed, characterized by comprising.
以下、実施例によって詳しく説明する。本発明は、上
記の目的を達成するためにチャンネル領域のシリコン膜
厚１を従来のものと比較して薄くする。第１図は本発明
の薄膜半導体装置の断面図である。図中１、５、６はシ
リコン薄膜、２はゲート絶縁膜、３、４はアルミ配線、
７はゲート電極、８は基板、９は絶縁膜である。 基板８の上にシリコン薄膜５、６が互いに離間されて
島状に形成されている。この島状のシリコン薄膜５、６
の間および上にシリコン薄膜１が帯状に形成されてい
る。シリコン薄膜１の表面にゲート絶縁膜２が形成さ
れ、その上にゲート電極７が形成されている。このよう
な半導体装置のソース・ドレイン領域は、ゲート電極等
をマスクとしてイオン打ち込みすることにより、シリコ
ン薄膜５、６及びシリコン薄膜１のうちのイオン打ち込
みされた領域により形成すればよい。シリコン薄膜１、
５、６、及びゲート電極の上に絶縁膜９が形成され、コ
ンタクトホールを通してソース・ドレイン領域上にアル
ミ配線３、４が設けられている。 シリコン薄膜１のうち、ゲート電極７に対向する領域
が、チャンネル領域である。上述のように、チャンネル
領域の多結晶シリコンもしくは単結晶シリコン膜１は従
来の薄膜半導体装置において2500〜3000オングストロー
ムが最も薄い値であったが、本発明では、離間した島状
のシリコン薄膜５、６から、その間にかけてシリコン薄
膜１を形成し、その膜厚を薄くすることにより、チャン
ネル領域の膜厚の薄い薄膜トランジスタを実現した。こ
のチャンネル領域を形成するシリコン薄膜の膜厚は、10
00オングストローム以下である。 このようにして、チャンネル領域のシリコンの膜厚を
1000オングストローム以下の極めて薄いものとすること
により、光照射が無い場合でも有る場合でもリーク電流
を減少させることができ、光リーク特性が改善される。
しかし、ゲート絶縁膜２をシリコン膜の酸化によって形
成する場合には、シリコン表面の凹凸を考慮して残留シ
リコン膜厚を500〜1000オングストロームとすることが
量産上は妥当な値である。 チャンネル領域のシリコン薄膜１の厚さを少なくする
ことによって、アルミ配線３、４とのコンタクト不良を
生じる度合いが大きくなるという問題が派生する。そこ
で、チャンネル領域のシリコン膜形成前または形成後
に、アルミ配線とのコンタクト部分のみシリコン膜厚を
大きくするためにシリコン薄膜５、６を島状に形成して
おく。このように本発明によれば、ソース・ドレイン領
域が厚く形成されているので、コンタクト不良を防止で
きる。Hereinafter, a detailed description will be given with reference to examples. In the present invention, in order to achieve the above object, the silicon film thickness 1 in the channel region is made thinner than the conventional one. FIG. 1 is a sectional view of a thin film semiconductor device of the present invention. In the figure, 1, 5 and 6 are silicon thin films, 2 are gate insulating films, 3 and 4 are aluminum wiring,
Reference numeral 7 is a gate electrode, 8 is a substrate, and 9 is an insulating film. Silicon thin films 5 and 6 are spaced apart from each other and formed in an island shape on a substrate 8. This island-shaped silicon thin film 5, 6
The silicon thin film 1 is formed in a band shape between and on the space. A gate insulating film 2 is formed on the surface of the silicon thin film 1, and a gate electrode 7 is formed thereon. The source / drain regions of such a semiconductor device may be formed by ion-implanted regions of the silicon thin films 5 and 6 and the silicon thin film 1 by ion-implanting using the gate electrode or the like as a mask. Silicon thin film 1,
An insulating film 9 is formed on the gate electrodes 5 and 6, and aluminum wirings 3 and 4 are provided on the source / drain regions through the contact holes. A region of the silicon thin film 1 facing the gate electrode 7 is a channel region. As described above, the polycrystalline silicon or single crystal silicon film 1 in the channel region has the thinnest value of 2500 to 3000 angstroms in the conventional thin film semiconductor device. A thin film transistor having a thin film thickness in the channel region was realized by forming the silicon thin film 1 from 6 to in between and thinning the film. The thickness of the silicon thin film that forms this channel region is 10
It is less than 00 angstroms. In this way, the thickness of the silicon in the channel region
By making it extremely thin, 1000 angstroms or less, the leak current can be reduced and the light leak characteristics can be improved with or without light irradiation.
However, when the gate insulating film 2 is formed by oxidizing the silicon film, it is an appropriate value for mass production to set the residual silicon film thickness to 500 to 1000 angstroms in consideration of the unevenness of the silicon surface. By reducing the thickness of the silicon thin film 1 in the channel region, there arises a problem that the degree of occurrence of contact failure with the aluminum wirings 3 and 4 increases. Therefore, before or after forming the silicon film in the channel region, the silicon thin films 5 and 6 are formed in an island shape in order to increase the silicon film thickness only in the contact portion with the aluminum wiring. As described above, according to the present invention, since the source / drain regions are formed thickly, contact failure can be prevented.
以上述べたように、本発明の半導体装置は、従来のも
のと比較して、光の影響を受けないので、携帯用機器等
の表示装置として大いに適している。As described above, since the semiconductor device of the present invention is not affected by light as compared with the conventional device, it is highly suitable as a display device for portable equipment and the like.
第１図は本発明の薄膜半導体装置の断面図である。 １、５、６……シリコン膜 ２……ゲート絶縁膜 ３、４……アルミ配線 ７……ゲート電極 ８……基板 ９……絶縁膜 FIG. 1 is a sectional view of a thin film semiconductor device of the present invention. 1, 5, 6 ... Silicon film 2 ... Gate insulating film 3, 4 ... Aluminum wiring 7 ... Gate electrode 8 ... Substrate 9 ... Insulating film
Claims (1)
なる第１領域及び第２領域と、 該島状の第１領域及び第２領域の間及び上に形成された
膜厚が1000オングストローム以下である第２シリコン薄
膜とを含み、 該半導体装置のチャンネル領域は該第２シリコン薄膜の
一部からなり且つ該第１領域及び第２領域の間に配置さ
れてなり、 該チャンネル領域上にはゲート絶縁膜を介してゲート電
極が配置されてなり、 該半導体装置のソース・ドレイン領域は該第１領域及び
第２領域と該第２シリコン薄膜の一部からなり、 該ソース・ドレイン領域は金属からなるソース配線及び
ドレイン配線に電気的に接続されてなり、 該ソース・ドレイン領域の膜厚は、該チャンネル領域の
膜厚よりも厚く形成されてなることを特徴とする半導体
装置。1. A semiconductor device formed on a substrate, comprising: a first region and a second region formed of a first silicon thin film, which are formed in an island shape so as to be separated from each other, and the island-shaped first region and the second region. A second silicon thin film having a film thickness of 1000 angstroms or less formed between and above the regions, the channel region of the semiconductor device being formed of a part of the second silicon thin film, and the first region and the second region. A gate electrode is disposed on the channel region via a gate insulating film, and the source / drain regions of the semiconductor device are the first region, the second region, and the second region. The source / drain regions are made of a part of a silicon thin film, and the source / drain regions are electrically connected to a source wiring and a drain wiring made of metal. The thickness of the source / drain regions is larger than that of the channel region. A semiconductor device characterized by comprising the Ku formed.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57041168A JPH0828507B2 (en) | 1982-03-16 | 1982-03-16 | Semiconductor device |
| JP5197508A JPH07118545B2 (en) | 1982-03-16 | 1993-08-09 | LCD display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57041168A JPH0828507B2 (en) | 1982-03-16 | 1982-03-16 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5197508A Division JPH07118545B2 (en) | 1982-03-16 | 1993-08-09 | LCD display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58158971A JPS58158971A (en) | 1983-09-21 |
| JPH0828507B2 true JPH0828507B2 (en) | 1996-03-21 |
Family
ID=12600889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57041168A Expired - Lifetime JPH0828507B2 (en) | 1982-03-16 | 1982-03-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0828507B2 (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58182272A (en) * | 1982-04-19 | 1983-10-25 | Seiko Epson Corp | Thin film transistor |
| JPS58178564A (en) * | 1982-04-13 | 1983-10-19 | Seiko Epson Corp | Thin film transistor |
| JPS6020582A (en) * | 1983-07-14 | 1985-02-01 | Nec Corp | Mis transistor and manufacture thereof |
| JPS60186063A (en) * | 1984-02-06 | 1985-09-21 | Sony Corp | Thin film transistor |
| JPH0758793B2 (en) * | 1984-12-19 | 1995-06-21 | 松下電器産業株式会社 | Method of manufacturing thin film transistor |
| JPH025572A (en) * | 1988-06-24 | 1990-01-10 | Matsushita Electron Corp | Semiconductor device |
| JPH0442579A (en) * | 1990-06-08 | 1992-02-13 | Seiko Epson Corp | Manufacture of thin film transistor |
| JP2838932B2 (en) * | 1991-12-20 | 1998-12-16 | 三菱電機株式会社 | Field effect type semiconductor device |
| JP3580564B2 (en) * | 1993-01-27 | 2004-10-27 | 田岡化学工業株式会社 | Cobalt-containing azo compound, its use and production method |
| JP2500484B2 (en) * | 1994-07-11 | 1996-05-29 | ソニー株式会社 | Thin film transistor manufacturing method |
| JP2531383B2 (en) * | 1994-07-11 | 1996-09-04 | ソニー株式会社 | Thin film transistor manufacturing method |
| JP2546538B2 (en) * | 1994-07-11 | 1996-10-23 | ソニー株式会社 | Thin film transistor manufacturing method |
| JP3292657B2 (en) * | 1995-04-10 | 2002-06-17 | キヤノン株式会社 | Thin film transistor and method for manufacturing liquid crystal display device using the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56135968A (en) * | 1980-03-27 | 1981-10-23 | Canon Inc | Amorphous silicon thin film transistor and manufacture thereof |
| JPS5710266A (en) * | 1980-06-23 | 1982-01-19 | Fujitsu Ltd | Mis field effect semiconductor device |
-
1982
- 1982-03-16 JP JP57041168A patent/JPH0828507B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58158971A (en) | 1983-09-21 |
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