JPS60186063A - Thin film transistor - Google Patents

Abstract

PURPOSE:To reduce the thickness of an active region, to raise the mobility of a carrier, to lower a threshold voltage and to reduce the resistances of a source region and an active region by forming source and drain regions of a laminated film of a polycrystalline silicon film for forming the active region and a low resistance film. CONSTITUTION:A doped polysilicon film 13 which is reduced in the resistance value by the addition of an impurity is coated by a CVD method on the surface of a silicon dioxide film 12. A central portion interposed between the source and drain regions of the film 13 (the portions at both sides of the drawing) remain except the both regions is removed by photoetching. Then, a polysilicon film 14 is coated in the necessary thickness on the active layer by a CVD method. The thickness of the film 14 at this time is reduced to improve the characteristic. Then, the laminated films 14 and 13 are removed at both sides. Here, the portion interposed between the films 14 and 13 becomes an active region.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a thin film transistor formed by depositing a semiconductor thin film on an insulating substrate.

Background technology and its problems> Thin film transistors (T F T : T
b1n Film Transister) has a configuration as shown in FIG. 1, for example.

That is, in this FIG. 1, an insulating substrate 1 such as a quartz plate
After forming an insulating film 2 such as silicon dioxide thereon, a semiconductor thin film such as polysilicon (polycrystalline silicon) is deposited, and by performing etching, impurity diffusion, etc. on this, the source region 3 is formed. , a drain region 5, a channel ζ, and an active region (channel region) 4 between these regions. After forming the insulating film 6 to cover these three regions, it is made of aluminum A1 or the like.
While the summation electrode 1 and the drain electrode 8 are being formed, a gate electrode 9 is being formed of toppolysilicon (polycrystalline silicon added with impurities) or the like. Note that each of the above three regions is formed with a film thickness of about 3000 to 5000 A:''.

"For conventional thin film transistors like this"? Therefore, the active region 4 is preferably thin in order to increase carrier mobility and lower the threshold voltage. However, as mentioned above, the source region 3, active region 4, and drain/
Since the region 5 is formed with the same film thickness by depositing a semiconductor thin film, if an attempt is made to reduce the film thickness of the active region 4, the film thicknesses of the source region 3 and drain region 5 will also become thinner at the same time. The resistance value in one area becomes high. In addition, l(I E (reactive ion etching)
It is also possible to make only the active region 4 thinner by, etc., but this method is usually not used because it is difficult to control the film thickness and the damage to the film is large.

<Purpose of the Invention> The present invention has been made in view of the above-mentioned problems of the conventional art. Another object of the present invention is to provide a thin film transistor in which the drain region is made thicker than the active region to reduce the resistance of these two regions.

<Summary of the Invention> In order to achieve the above-mentioned object, a thin film transistor according to the present invention includes a semiconductor layer made of a polycrystalline silicon film, in which a source region, a drain region, and respective electrodes are formed, and a region between the source region and the drain region. In a thin film transistor in which a gate electrode is formed in an active region via a gate insulating film, the source and drain regions are formed of a laminated film with a film having a lower resistance than the polycrystalline silicon film forming the active region. It is characterized by:

<Embodiments> Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

FIGS. 2 to 11 are schematic cross-sectional views showing manufacturing steps in a first embodiment of a thin film transistor according to the present invention.

First, as shown in FIG. 2, an insulating film, for example, a silicon dioxide film 12, is formed on an insulating substrate 11 such as a quartz plate or a glass plate by a C1f-D method (vapor phase growth method), etc.; , as shown in FIG. 1C, a doped polysilicon (polycrystalline silicon with impurities) film 1 whose resistance value has been lowered by adding impurities to the surface of this silicon dioxide film 12.
3 is deposited and formed by CVD method or the like. At this time, the doped polysilicon film 13 is preferably formed to have a thickness of about 3000 mm.

Then, as shown in FIG.
The center portion sandwiched between these regions is removed by photo-etching or the like, leaving only the portions on both sides in the figure.

Next, as shown in FIG. 5, the polysilicon (polycrystalline silicon) film 14 is CVD to a thickness necessary for the active region to be described later.
Adhesion is formed by the D method or the like. Polysilicon film 1 at this time
It is preferable that the film thickness of No. 4 be made thinner than the film thickness when forming a general thin film transistor, for example, 1500 λ as shown below, but as will be described later, by making it extremely thin to 100 to 750 λ, the characteristics can be significantly improved. Excellent effects such as improved performance are rated as 1.

Subsequently, as shown in FIG. 6, the portions on both sides of the layered polysilicon film 14 and doped polysilicon film 13 in the figure are separated from other separators (not shown). ,
It is removed by photo-etching or the like. Here, the doped polysilicon film 1 of the polysilicon film 14 is
The part sandwiched by 3 becomes the active region.゛Next, as shown in Fig. 7, after a short period of thermal oxidation, the silicon dioxide film 1 is formed by applying a CVD method.
5 is deposited to a film thickness of about xooo1. Note that the silicon dioxide film 15 may be formed only by the CVD method, but as described above, by performing thermal oxidation for a short time before applying the CVD method, the silicon dioxide film 15 and the polysilicon film 14 can be formed. In addition to improving adhesion, adverse effects at these interfaces are reduced, and properties can be improved.

Next, as shown in FIG. 8, a phosphorus-doped polysilicon (phosphorus-doped polycrystalline silicon) film 16 doped with phosphorus P as an impurity is deposited by a CVI method or the like, and then as shown in FIG. The phosphorus-doped polysilicon film 16 and the silicon dioxide film 15f are removed by photo-etching or the like, leaving only the gate portion at the center in the figure.

Subsequently, as shown in FIG. 1θ, a silicon dioxide film 17, for example, is deposited as an insulating film by CVD or the like. At this time, it is preferable to form the silicon dioxide film 1T to a thickness of about 3000λ.

Finally, as shown in FIG. 11, a window for the electrode is opened, and alumina (AI) or the like is vacuum-deposited, for example, to form the source electrode 18, A gate' electrode 19 and a drain electrode 20 are respectively formed.

By setting the thickness of the polysilicon film 14 forming the active region in the thin film transistor obtained through such a manufacturing process to 100 to 750 nm, the threshold voltage can be lowered and the effective movement of carriers can be reduced. The leakage current at the junction between the source region and the drain/region and the leakage current between the source region and the drain region caused by external light can be reduced. Note that when configuring such an ultra-thin film transistor, the polysilicon film 1 in the active region
The film thickness of No. 4 may be in the range of 100 to 750 λ, but generally it is preferably 100 to 600 λ, and 20
0 to 50 (more preferably 3A').

Next, a second example will be described. 12 to 21 are schematic cross-sectional views showing the manufacturing process in a second embodiment of the thin film transistor according to the present invention. In addition,
The thin film transistor in this embodiment is of a so-called back gate type.

First, as shown in FIG. 12, an insulating film, for example, a silicon dioxide film 22, is deposited on an insulating substrate 21 such as a quartz plate or a glass plate by CVD method, and then as shown in FIG. A doped polysilicon film 23 is formed on the surface of this silicon dioxide film 22 by CVD or the like.

Then, by leaving only the central part of the doped polysilicon film 23 in the figure and removing the other parts by photoetching or the like, the gate/electrode 23 is etched as shown in FIG.
Form 3a.

Next, by subjecting this to thermal oxidation or CVD, the gate voltage is made as shown in FIG. A silicon dioxide/recon film 24 is formed on the surface of the doped polysilicon film 23.

Then, as shown in FIG. 16, a polysilicon film 25 forming an active region (channel region) is deposited by CVD or the like.At this time, the polysilicon film 25 has a thickness of 100 mm as described above. ~750A', preferably 10
It goes without saying that the characteristics can be improved by making the thickness extremely thin, preferably 0 to 600 λ, more preferably 200 to 500 λ.

Subsequently, as shown in FIG. 17, this polysilicon film 1 is
After forming a doped polysilicon film 26 having a resistance lower than that of 5, as shown in FIG. Portions of the silicon film 25 on both sides in the figure are removed by photoetching or the like.

Further, as shown in FIG. 19, the central gate portion, that is, the gate electrode 2 of the doped polysilicon film 26
Only the portion located above 3a is removed by photo-etching or the like.

Next, as shown in FIG. 20, a silicon dioxide film 27 is deposited as an insulating film by CVD or the like. At this time, it is preferable that the silicon dioxide film 27 be formed to have a thickness of about 30,001 mm. Note that if the silicon dioxide film 21 is thermally oxidized for a short time and then deposited by the CVD method, the adhesion with the polysilicon film 25 will be improved.

Then, as shown in FIG. 21, a window is finally opened for the electrode, and aluminum (AI) or the like is vacuum-deposited and pattern-etched to form the source electrode 28.
and a drain electrode 29 is formed. Note that the gate electrode 23a is drawn out from the direction toward the center of this element in the figure.

The thin film transistor obtained through such a manufacturing process exhibits the same effects as the thin film transistor of the first embodiment described above.

<Effects of the Invention> As is clear from the description of the embodiments described above, according to the present invention, the film thickness of the active region can be reduced to improve characteristics, for example, by increasing the mobility of vocal carriers and lowering the threshold pressure. At the same time, it is possible to provide a thin film transistor in which the thickness of the source region and the drain region is made thicker than that of the active region, thereby lowering the resistance of these two regions. can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view showing one row of the configuration of a conventional thin film transistor. 2 to 11 show the manufacturing process in the first embodiment of the thin film transistor according to the present invention + a schematic cross-sectional view, and a 12th embodiment.
Figures 21 to 21 show details of thin film transistors according to the present invention.
It is a schematic sectional view showing the manufacturing process in the example. 11.21... Insulating plate 13, '26... Doped polysilicon film 14.2
5... Polysilicon film 15.24... Silicon dioxide film 18.28... Source electrode 19.23; I... Gate electrode 20.29... Drain electrode ) ++B 1lllI eo April 9, 2006 Manabu Shiga, Commissioner of the Japan Patent Office1, Indication of the case 1982 Patent Application No. 184812, Relationship with Title of the Invention A'1 Patent 3'r Applicant's Address Tokyo 6-7-35, Kita-Shinyo, Parts Ward Name (
21B) Sony Corporation (Name) Representative: Norio Ohga 4, Agent: 105 Address: 11th Floor, 11 Mori Building, 2-6-4 Toranomon, Son-ku, Tokyo (508) 8266 (Spontaneous) 6. "Detailed Description of the Invention" column of the specification to be amended, "Brief Description of Drawings" column, and Drawing 7, Contents of the Amendment (7-1) 8A Specification, page 10, line 16 1st page on the same page as
Add the following statement between the 7 lines. [Next, a third embodiment will be described using FIGS. 22 to 26. Note that the same reference numerals as in the first embodiment will be used to refer to common parts, and a description thereof will be omitted. The thin film 1 to the run star of the third embodiment are as shown in FIG.
It has a structure in which a doped polysilicon film 13, which is a north region and a train region, and a silicon dioxide film 32 are deposited on a PSG (IJ silicate glass) film 31 so as to have substantially equal thicknesses on the surrounding region. ing. Therefore, the 1-but polysilicon film 1 which is a low resistance region
There is no step difference on the surface of the doped polysilicon film 13, and the contact between the doped polysilicon film 13 and the polysilicon film 14 is good. This thin film 1-run star may be manufactured, for example, by the following manufacturing process. That is,
After a PSG film 31 and a silicon dioxide film 32 are deposited on the insulating substrate 11 by CVD or the like (see FIG. 23), the regions of the silicon dioxide film 32 that will become the source region and the train region are removed by photoetching or the like. Groove 40
(See Figure 24). Then, a doped polysilicon film 13 is deposited and a resist 33 is applied by a spin code method or the like (see FIG. 25), so that the resist 33 and the doped polysilicon film 13 have the same enotinic rate. Under certain conditions, RIE (reactive ion etching) or the like is applied to flatten the surface (see FIG. 26). The subsequent steps are similar to those for manufacturing ordinary thin film transistors. According to this thin film transistor, the PSG film 31 can prevent contamination from the insulating substrate 11, and the P 8 G film 31 can also be used for impurity diffusion. Further, FIG. 27 is a schematic cross-sectional view showing a thin film I transistor of the fourth embodiment, in which a groove 50 is formed on an insulating substrate 11, and the groove is doped with dope 1 to form a north region and a train region.
It has a structure in which a doped polysilicon film 13 is formed, and there is no step difference as in the eighth embodiment, and the contact between the doped polysilicon film 13 and the polysilicon film 14 is good. In this FIG. 27 as well, the same reference numerals as in the first embodiment are used for common parts, and a description thereof will be omitted. The same effects as the thin film transistor of the first embodiment can be obtained with each of the thin film transistors of the third and fourth embodiments described above. (7L-2) Page 11, line 13 of the specification and contribution number 1
Add the following statement between lines 4 and 4. 22 is a schematic sectional view showing the third embodiment of the thin film transistor according to the present invention, and FIGS. 23 to 26 are the third embodiment of the thin film transistor according to the present invention.
FIG. 27 is a schematic sectional view showing an example of the manufacturing process of the thin film transistor according to the fourth embodiment of the present invention. (7-8) The attached drawings, Figures 22 to 27, are added as attached. Above Figure 22 1 Figure 23 1 Figure 24 4/) Figure 25 Mom 1 Figure 26! ,) tt 50

Claims (1)

[Claims] A thin film transistor in which source and drain regions and respective electrodes are formed in a semiconductor layer made of a polycrystalline silicon film, and a gate electrode is formed in an active region between the source and drain regions via a gate insulating film, A thin film transistor in which the source and drain regions are formed of a laminated film of the polycrystalline silicon film forming the active region and a film with a lower resistance than the polycrystalline silicon film.