JPH0228361A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent extension of diffusion length and lowering of reliability on deterioration of element characteristics by using 'on-the-place adding method' in which impurity gas is added into active gas so as to accumulate a doping layer directly. CONSTITUTION:After forming an insulating film 7 consisting of a silicon oxide film on a lower electrode 7, a polycrystalline silicon layer 18 doped with phosphorous in high concentration is accumulated by 'on-the-place adding method'. Hereupon, a substrate 1 is installed in a CVD device, and after letting only silane gas flow, phosphine gas is added so as to accumulate a polycrystalline silicon layer 18 which is doped with phosphorus in high concentration with a thickness of 2000Angstrom at the substrate temperature of 600 deg.C, and this is patterned so as to form the pattern of an upper electrode 18. Hereafter, heat treatment at 1050 deg.C is done for 15 seconds. Accordingly, a MOS capacitor which caught the insulating film 7 with the upper electrode 18 and the lower electrode 6 is formed, and a memory cell consisting of a MOS FET and a MOS capacitor can be obtained. Hereby, it becomes one that the extension of a diffusion layer is also small, the characteristics are excellent even for high integration, and reliability is high.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for increasing the degree of integration thereof.

(Conventional technology) In recent years, demands for higher integration and higher performance in semiconductor integrated circuit devices have been increasing, and it is important to realize these demands using design rules and technology that are allowed by the process. It has become a challenge.

On the other hand, advances in contact formation technology have led to the direct contact method in which impurities are directly diffused from the polycrystalline silicon layer constituting the contact to form an active region, and the direct contact method in which impurities are diffused directly from the polycrystalline silicon layer constituting the contact, and silicon is selectively removed only from the contact portion in the active region. The 5EG (SSG) growth method and the like have been developed, and it has become possible to make contact with the semiconductor active region in one direction or in a completely self-aligned manner.

For example, in a dynamic RAM (DRAM), a MOSFE as a switching transistor is installed in a semiconductor activation region (one cell region) surrounded by an element isolation insulating film.
T and a MOS capacitor are formed.

However, in order to achieve high integration, the isolation width must be made as small as possible, and the substrate activation region width must be made as large as possible in order to increase the driving ability of the transistor or to increase the capacitor's 8R. . In other words, a decrease in the area of the capacitor that stores information means a decrease in the amount of accumulated charge, which may lead to problems such as the memory information being destroyed due to disturbances if the memory information is read incorrectly.

As described above, even with the latest contact technology, there is a conflicting problem between high integration and high performance, such as reducing the width of the substrate active region to achieve high integration, resulting in a decrease in device performance. was occurring.

Therefore, in order to solve the problem that the area of the capacitor is not reduced due to high integration, a MOS capacitor is stacked on the memory cell area, and one electrode of the capacitor is formed on the semiconductor substrate. A memory cell called a gi-layer pear-shaped memory cell has been proposed, which has a structure in which the capacitance of a MOS capacitor is substantially increased by making one electrode of a switching transistor conductive.

This stacked memory cell is shown in FIGS. 2(a) to 2(e).
), a source made of an n-swelled diffusion layer is placed in one memory cell region separated by an element isolation insulating film (not shown) formed in a p-type silicon substrate 1. - Drain regions 2a, 2b and source/drain regions 2a.

A gate 'M$M4 is formed between 2b and 2b through a gate insulating film 3 to form a MOSFE as a switching transistor.
An insulating film 5 is formed on the gate electrode 4 of the MOSFET and the gate electrode (word II) of the MOS FET of the adjacent memory cell so as to form a contact with the source region 2a of the MOS FET in the upper layer. A capacitor is formed by sandwiching an insulating film 7 between a lower electrode 6 and an upper electrode 8.

This 1a layer type memory cell is formed as follows.

That is, this stacked memory cell is first constructed as shown in FIG. 2(a).
As shown in FIG. 2, source/drain regions 2a and 2b made of n-swelled diffusion layers and source/drain regions 2a and 2b are provided in a p-type silicon substrate 1.
A gate electrode 4 is formed between the drain regions 2a and 2b with a gate insulating film 3 interposed therebetween to form a MOS FET as a switching transistor.

Next, as shown in FIG. 2(b), after forming a silicon oxide film as a passivation film 5 over the entire surface of the substrate, a contact hole h for contacting the drain region 2b is formed, and a silicon oxide film is formed with a high concentration. A pattern of a lower electrode 6 made of a doped polycrystalline silicon layer is formed.

Then, as shown in FIG. 2C, an insulating film 7 made of a silicon oxide film and a polycrystalline silicon layer 8a are sequentially deposited on this lower electrode 6.

Thereafter, as shown in FIG. 2(d), impurities such as phosphorus are introduced into the polycrystalline silicon layer a by a diffusion method or the like. At this time, the diffusion temperature is about 900'0120 minutes,
A desired conductivity is imparted to the polycrystalline silicon layer by doping impurities at a high concentration.

Finally, the highly doped polycrystalline silicon layer is patterned to form a MOS capacitor with an insulating film 7 sandwiched between an upper electrode 8 and a lower electrode 6.
As shown in Figure (e), a memory cell consisting of a MOSFET and a MOS capacitor is 4F? It will be done.

(Problems to be Solved by the Invention) In such a configuration, since it is a laminated structure, the capacitor area can be increased and the capacitance can be increased, but the following problems arise in the manufacturing process. Ta.

That is, when forming the upper electrode, it is desirable that the impurity diffusion temperature be high and for a long time in order to provide sufficient conductivity to the polycrystalline silicon layer.

However, since the transistor has already been formed, if heat treatment is performed at high temperature and for a long time, the impurities in the n-swelled diffusion layer constituting the source/drain regions 2a and 2b will be re-diffused and the diffusion length will be extended, resulting in transistor characteristics. This caused deterioration and reduced reliability.

That is, in addition to the problem that the n-swelled diffusion layer extends to the region of the element isolation insulating film, which significantly reduces the element isolation ability, the n-swelled diffusion layer extends to the channel region due to the lateral extension of the n-swelled diffusion layer. As a result, there was an unavoidable problem that the effective channel length would decrease and the performance of the MOS transistor would deteriorate due to the short channel effect.

Such a problem is not limited to DRAMs, but applies to all other semiconductor devices having a structure in which a doping layer must be formed after a diffusion layer is formed.

The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to suppress the extension of diffusion length as much as possible when forming a doping layer in a semiconductor device having a diffusion layer, and to provide a semiconductor integrated circuit device with high density and high reliability. The purpose is to

Further, the present invention provides M of a DRAM having a stacked memory cell structure.
When forming a heavily doped polycrystalline silicon layer as the upper electrode of an OS capacitor, the extension of the diffusion layer of the MOSFET is minimized to provide a DRAM with an f1 layer type memory cell structure that is small and has good characteristics. purpose.

(Structure of the Invention) (Means for Solving the Problems) Therefore, in the present invention, when forming a doping layer on a semiconductor substrate on which a diffusion layer has already been formed, "in-situ addition" is used.
I try to use

Furthermore, in the present invention, when forming a heavily doped polycrystalline silicon layer as the upper electrode of a MOS capacitor of a DRAM having an f1 layer type memory cell structure, a thin polycrystalline silicon layer is first formed using a reactive gas that does not contain impurities. A pre-process of depositing a silicon layer is used, followed by a main process of depositing a polycrystalline silicon layer by "in-situ addition" using a reactive gas containing impurities.

(Function) According to the above configuration, since an "in-situ addition" method is used in which an impurity gas is added to a reactive gas and a doping layer is directly deposited, the doping layer is doped at a high concentration at a low temperature. This prevents impurities in the diffusion layer from re-diffusing and lengthening the diffusion length, and prevents deterioration of device characteristics and reliability even when increasing density. It can be prevented.

Furthermore, when forming a DRAM, the diffusion layer extends into the region of the element isolation insulating film, significantly reducing the element isolation ability, and the effective channel length decreases due to the lateral extension of the diffusion layer. , MOS due to short channel effect
There are no problems such as deterioration of transistor performance, and the transistor can be made small and have good characteristics.

Furthermore, prior to the main process of depositing a polycrystalline silicon layer by "in-situ addition", a thin polycrystalline silicon layer is first deposited using a reactive gas that does not contain impurities as a pre-process. This has the effect of preventing impurities from penetrating into the underlying insulating layer and creating a path to the lower electrode.

(Example) Hereinafter, details of an example of the present invention will be described with reference to the drawings.
Explain.

Figures 1(a) to 1(d) are v1 of the embodiment of the present invention.
FIG. 2 is a diagram showing an example of a manufacturing process of a DRAM having a layered memory cell structure. This method is characterized by the use of "in-situ addition" when forming the lower electrode and the upper electrode, and the rest is exactly the same as the method shown in the conventional example.

That is, this stacked memory cell is first constructed as shown in FIG. 1(a).
As shown in FIG.
Inside, a source/drain region 2a consisting of an n-swelled diffusion layer,
2b and a gate electrode 4 via a gate insulation WA3 between the source/drain regions 2a and 2b to form a MOSFET as a switching transistor.

Next, as shown in FIG. 1(b), after forming a silicon oxide film as a passivation film 5 over the entire surface of the substrate, a contact hole h for making contact with the drain region 2b is formed. A highly phosphorous-doped polycrystalline silicon layer is deposited to a thickness of 4,000 mm using the "additive method" at a substrate temperature of 600 DEG C., and is patterned to form a pattern for the lower electrode 6.

Then, as shown in FIG. 1C, after forming an insulating film 7 made of a silicon oxide film on this lower electrode 6, a polycrystalline silicon layer 18 doped with phosphorus at a high concentration is formed by "in-situ addition". are sequentially deposited.Here, the substrate is deposited by CVD.
Installed in a Vt chamber, first flowing only silane gas, then adding phosphine gas and heating at a substrate temperature of 600°C. A thickness 2
A polycrystalline silicon layer 18 doped with phosphorus at a high concentration of 00OA is deposited and patterned to form a pattern for the upper electrode 18. After that, heat treatment is performed at 1050° C. for 15 seconds.

In this way, the upper electrode 18 and the lower electrode 6 insulate Wj! A MOS capacitor sandwiching 7 is formed, and the first
As shown in Figure <d), a memory cell consisting of a MOS FET and a MOS capacitor is obtained.

DR of the stacked memory cell structure thus formed
In AM, the diffusion layer has less extension, and even when the density is increased, the properties are good and the reliability is high.

In the above embodiment, both the upper electrode and the lower electrode were formed by "in-situ addition", but it goes without saying that it is also effective to apply the method only to the formation of the lower electrode or the upper electrode.

Further, in the embodiment described above, a heat treatment was performed after patterning the upper electrode to activate the impurities, but this step may be omitted. Furthermore, since this heat treatment is instantaneous heating, the extension of the diffusion length can be kept small.

Furthermore, the present invention is not limited to the formation of a DRAM, but is also effective when forming a doping layer on a semiconductor substrate on which a diffusion layer has already been formed when forming other elements.

[Effects of the Invention] As explained above, according to the present invention, when forming a doping layer on a semiconductor substrate on which a diffusion layer has already been formed, "in-situ addition" is used.
It is possible to reduce the thermal influence on the already formed regions, and prevent deterioration of element characteristics and reliability even when increasing the density.

Further, in the present invention, M of a DRAM having a stacked memory cell structure is
When forming a highly doped polycrystalline silicon layer as the upper electrode of an OS capacitor, a process is used to deposit the polycrystalline silicon layer by "in-situ addition" using a reactive gas containing ring≠cinene pure substances. Because I am doing this,
It is possible to eliminate disadvantages such as a decrease in effective channel length due to an increase in diffusion length, and to achieve miniaturization and improvement in characteristics.

In addition, prior to the main process of depositing a polycrystalline silicon layer by "in-situ addition", a thin polycrystalline silicon layer is deposited using a reactive gas that does not contain impurities as a pre-process. This prevents impurities from penetrating into the underlying insulating layer and causing a short circuit with the lower electrode, thereby improving manufacturing yield.

[Brief explanation of the drawing]

1(a) to 1(d) are manufacturing process diagrams of a DRAM with a stacked memory cell structure according to an embodiment of the present invention, and FIG. 2(a)
) to FIG. 2(e) are manufacturing process diagrams of conventional DRAMs. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2a, 2b... Source/drain region, 2... N swelling diffusion layer, 3... Gate insulating film, 4... Gate electrode, 5... Passivation film, 6... lower electrode, h... contact hole,
7... Insulating film, 8... Upper electrode, 8a... (non-doped) polycrystalline silicon layer, 18... Polycrystalline silicon layer doped with phosphorus at a high concentration.

Claims (2)

[Claims] (1) A semiconductor device characterized in that, when a doping layer is formed on a semiconductor substrate on which a diffusion layer has already been formed, the step of forming the doping layer includes a deposition step using an "in-situ doping method". Production method. (2) In a method for manufacturing a MOS capacitor for a DRAM with a stacked memory cell structure, the deposition process for forming a heavily doped polycrystalline silicon layer as the upper electrode is performed using a reactive gas containing no impurities to form a thin polycrystalline silicon layer. Manufacture of a semiconductor device characterized by comprising a pre-process of depositing a crystalline silicon layer and a main process of depositing a polycrystalline silicon layer by an "in-situ addition method" using a reactive gas containing impurities. Method.