JPH03283570A - Semiconductor device and its production - Google Patents

Abstract

PURPOSE:To stabilize element characteristics and allow high-speed operation by providing a memory cell and the transistor of the peripheral circuit and permitting the gate electrode of the transistor to have double layer structure which laminates a bottom gate electrode and a top gate electrode. CONSTITUTION:The device is provided with a memory cell, which has a floating electrode 12 provided on a semiconductor substrate 2 through a first gate insulating film, and a control electrode 16a formed on the floating electrode through a space insulating film 14 and a transistor, which has a gate electrode on the semiconductor substrate 2 through a second gate insulating film. The gate electrode of the transistor is permitted to have double structure which laminates a bottom gate electrode 12b and a top gate electrode 16b. The memory cell and the first and the second gate insulating films of the transistor are formed by controlling to have the desired thicknesses, and on the first and the second gate insulating films, the floating electrode 12a and the bottom gate electrode 12b are formed respectively by the same layer. The space insulating film 14 is formed by the desired thickness on the floating electrode 12a and the control electrode 16a and the top gate electrode 16b are formed by the same layer.

Description

[Detailed Description of the Invention] [Summary] This relates to a semiconductor device, particularly an E having a floating electrode and a control electrode.
PROM, E” PROM, FLASHEPROM/E
' Regarding semiconductor memory devices equipped with non-volatile memory cells such as PROMs and ordinary MOS transistors arranged in their peripheral circuits, it is possible to stabilize element characteristics, improve reliability, and enable high-speed operation. The purpose of the present invention is to provide a semiconductor device that can reduce the number of design steps. A semiconductor device comprising a memory cell having a control electrode formed thereon, and a transistor having a gate electrode provided on the semiconductor substrate with a second gate insulating film interposed therebetween, wherein the gate electrode is connected to a lower gate electrode and an upper gate electrode. The floating electrode and the lower gate electrode are formed in the same layer, the control electrode and the upper gate electrode are formed in the same layer, and the first and second gate electrodes are stacked.
The gate insulating film and the interlayer insulating film are each controlled to have a desired thickness.

[Industrial Field of Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular to an EPROM, an E2PROM, an FROM having a floating electrode and a control electrode.
The present invention relates to a semiconductor memory device including a nonvolatile memory cell such as a LASHEPROM/E'' PROM and a normal MOS transistor arranged in its peripheral circuit, and a method for manufacturing the same.

[Prior Art] In recent years, non-volatile semiconductor memory elements have become popular because they can be easily handled without requiring a power source to maintain their memory state.
Applications to memory cards and the like are attracting attention, and demands for improved reliability, reduced cost, and high-speed operation are increasing.

M of conventional non-volatile semiconductor memory elements having floating electrodes and control electrodes, such as FLASHEPROM and its peripheral circuits.
FIG. 7 shows a semiconductor memory device including an OS transistor.

Field oxidation WA4 is formed on semiconductor substrate 2 to isolate device regions 6. And FLASHEPROM
An n1 type impurity region 8a serving as a source and drain region is formed on the surface of the semiconductor substrate 2 in the element region 6 where the semiconductor substrate 2 is formed. A floating electrode 54 is formed on the semiconductor substrate 2 sandwiched between these n1 type impurity regions 8a via a gate oxide 1152. A control electrode 58 is formed on the floating electrode 54 via an interlayer insulating film 56 made of, for example, a silicon oxide film.

Similarly, on the surface of the semiconductor substrate 2 in the element region 6 where the MOS transistor is formed, n+ type impurity regions 8b are formed as source and drain regions. On the semiconductor substrate 2 sandwiched between these n+ type impurity regions 8b,
A gate electrode 62 is formed with a gate oxide film 60 interposed therebetween. In this way, the FLASHEPROM 64 and the MOS transistor 66 of its peripheral circuit are formed.

In this way, in a semiconductor memory device including a FLASHEPROM 64 and a MOS transistor 6 as a peripheral circuit, the FLASHEPROM 64 has a two-layer structure of a floating electrode 54 and a control electrode 58, whereas a MOS transistor 66 as a peripheral circuit. The gate electrode 62 has a one-layer structure. Therefore, in the manufacturing method, the floating electrode 5
4 and the gate electrode 62 are formed in the same layer, or the control electrode 58 and the gate electrode 62 are formed in the same layer, thereby shortening the manufacturing process.

[Problems to be Solved by the Invention] As described above, a semiconductor memory comprising the conventional FLASHEPROM 64 having a two-layer structure of the floating electrode 54 and the control electrode 58 and the MOS transistor 66 having a single-layer structure of the gate electrode 62 is provided. In the device, the manufacturing process is shortened by forming either the floating @[I54 or the control electrode 58 and the gate electrode 62 in the same layer.

First, a case where the floating electrode 54 and the gate electrode 62 are formed in the same layer will be described.

In order to speed up the peripheral circuit, MOS transistor 66
A high melting point silicide layer is used for the gate electrode 62 of
If a high melting point silicide layer is used in the floating electrode 5,
Unlike the normal case where 4 is made of a polysilicon layer, it becomes impossible to form an interlayer insulating film 56 on the floating electrode 54 by thermal oxidation of the polysilicon layer. In addition, the floating electrode 5
High melting point silicide is not preferable also from the viewpoint of the withstand voltage of the interlayer insulating film 56 between the control electrode 58 and the control electrode 58 .

Therefore, there is a problem that high-speed operation cannot be performed due to gate delay.

If an attempt is made to ensure high-speed operation of the MOS transistor 66 by using a polysilicon layer doped with impurities at a high concentration instead of using a high melting point silicide layer, when the interlayer insulating film 56 is formed on the floating electrode 54 by thermal oxidation. Furthermore, the growth rate of the silicon oxide film increases due to the high concentration of impurities contained therein, making it difficult to control the thickness of the interlayer insulating film 56.

By the way, the control electrode 58 of FLASHEPROM64
When applying a voltage to the floating electrode 54, the voltage applied to the floating electrode 54 is applied to the interlayer insulation between the control electrode 58 and the floating electrode 54! I5
6 and the gate oxide WA 52 under the floating electrode 54, and the memory cell is optimized by changing this capacitance ratio. There is a problem in that it causes fluctuations in

Next, a case where the control electrode 58 and the gate electrode 62 are formed in the same layer will be described.

The gate oxide film 60 of the MOS transistor 66 must be formed immediately before forming the gate electrode 62 in order to avoid contamination in the process, damage due to plasma, etc., and film thickness instability. Therefore, high-temperature heat treatment is required. The gate oxide film 60 will be formed after the gate oxide film 52 of the FLASHEPROM 64 is formed.

By the way, FLASHEPROM64 has floating t[,5
Since this is a nonvolatile memory in which charge is stored using a tunnel in M52 and the storage state is determined by the amount of stored charge, a tunnel current flows through the gate oxidation M52. It has been reported that when a tunnel current flows through the gate oxide film 52, positive charges or negative charges are captured in the gate oxide film 52, and leakage current becomes significant in a low electric field. It has been found that the leakage current of the gate oxide l1152 in a low electric field becomes more intense when high temperature heat treatment is performed after forming the gate oxide film 52, leading to deterioration of device characteristics.

Therefore, when the control electrode 58 and the gate t[I62 are formed in the same layer, the gate oxide film 52 is
When an electric field is applied to the floating electrode 54, the electric charge in the floating electrode 54 is lost due to leakage current of a low electric field, and the memory state cannot be maintained, resulting in a problem of lack of reliability.

In addition, when the control electrode 58 and the gate electrode 62 are formed in the same layer, the gate oxide film 60 of the transistor 6 (MOS)
is the interlayer insulation Ill! under the control electrode 58 of the FLASHEPROM 64. 56 will be formed at the same time.

By the way, the interlayer insulating film 56 and the gate oxide film 5 that control the voltage applied to the floating electrode 54 of the FLASHEPROM 64
When optimizing the memory cell by changing the capacity ratio with 2,
Generally, a simple method of changing the thickness of the interlayer insulating film 56 on the floating electrode 54 is adopted.

Therefore, changing the thickness of the interlayer insulator 856 on the floating electrode 54 involves changing the thickness of the gate oxide film 60, which also changes the characteristics of the transistor (MOS) transistor 6. To prevent this, it is necessary to modify the design. There is a problem in that the number of turns can last for a long time.

Further, in the above conventional example, the case where the interlayer insulation WA 56 is made of a silicon oxide film has been described, but for example, it may be made of a silicon oxide film/silicon nitride film, or a silicon oxide film/silicon oxide film/silicon oxide film.
A silicon nitride film having a multilayer structure such as silicon nitride III/silicon oxide film may be used. This is because in the case of a silicon oxide film, the surface of the floating electrode 54 made of a polysilicon layer is formed by oxidizing, so the film cannot be made thick enough, which causes current leakage.

Also, during this oxidation, the already formed gate oxide film 52
This is because high-temperature heat treatment is performed in the process, which generates a low electric field leakage current.

If a silicon nitride film is used as the interlayer insulating film 56 to solve this problem, the gate oxide film 60 of the MOS transistor 6 will also have a silicon nitride film. However, since the silicon nitride film has many traps, there is a problem in that electrons injected by hot carriers are trapped in the silicon nitride film, resulting in deterioration of the characteristics of the transistor 6 (MOS).

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device and its manufacturing method that can stabilize element characteristics, improve reliability, enable high-speed operation, and shorten design steps. It is something to do.

[Means for Solving the Problem] The above problem has a floating electrode provided on a semiconductor substrate with a first gate insulating film interposed therebetween, and a control electrode formed on the floating electrode with an interlayer insulating film interposed therebetween. In a semiconductor device comprising a memory cell and a transistor having a gate electrode provided on the semiconductor substrate via a second gate insulating film, the gate electrode may include a lower gate electrode and an upper gate electrode stacked together. The floating electrode and the lower gate electrode are formed in the same layer, the control electrode and the upper gate electrode are formed in the same layer, and the first and second gate insulating films and the interlayer This is achieved by a semiconductor device characterized in that each insulating film is controlled to have a desired thickness.

Further, a first step of forming a field oxide film on the semiconductor substrate to separate the first and second device regions, and forming a gate insulating film on the semiconductor substrate of the first and second device regions, respectively. A second step of forming a film, and after depositing a first conductive layer on the entire surface, patterning it into a predetermined shape, and depositing the first conductive layer on the gate insulating film in the first and second element regions, respectively. a third step of forming a floating electrode and a lower gate electrode made of a conductive layer; and a fourth step of removing part or all of the interlayer insulating film on the lower gate electrode after forming an interlayer insulating film on the entire surface. After depositing a second conductive layer on the entire surface, it is patterned into a predetermined shape to form a control electrode made of the second conductive layer on the floating electrode via the interlayer insulating film, and An upper gate consisting of the second conductive layer on the lower gate electrode! [! A fifth step of laminating a semiconductor device.

[Function] That is, the present invention includes a memory cell and a transistor of a peripheral circuit, the gate electrode of the transistor has a two-layer structure in which a lower gate electrode and an upper gate electrode are laminated, and the first gate electrode of the memory cell and the transistor and a second gate insulating film each controlled to a desired thickness, and these first gate insulating films are
A floating electrode of a memory cell and a lower gate electrode of a transistor are respectively formed in the same layer on the second gate insulating film, an interlayer insulating film of a desired thickness is formed on the floating electrode, and a control electrode and an upper gate electrode are formed on the floating electrode. By forming the gate electrodes in the same layer, the gate insulating films of the memory cell and the transistor and the interlayer insulating film of the memory cell can be controlled to desired thicknesses. Further, the resistance of the upper gate electrode of the transistor can be reduced. Furthermore, the number of design steps can be shortened.

[Example] The present invention will be specifically described below based on an illustrative example.

FIGS. 1(a) and 1(b) are plan views showing a FLASHEPROM of a semiconductor device and a MOS transistor of its peripheral circuit according to an embodiment of the present invention, and FIGS. 1(c) and (
d) is a sectional view showing a cross section along the Xl-Xi line and a cross section along the Yl-Yl line of the FLASHEPROM in FIG. 1(a), respectively;
Figures 1(e) and (f) are the MOS of Figure 1(b), respectively.
FIG. 3 is a cross-sectional view showing a cross section of the transistor taken along the line X2-X2 and along the line Y2-Y22.

A field oxide film 4 is formed on the semiconductor substrate 2, and the FL
Element regions 6 forming MOS transistors of the ASHEPROM and its peripheral circuits are separated. And F.L.A.
On the surface of the semiconductor substrate 2 in the element region 6 forming the SHEPROM, n+ type impurity regions 8a are formed as source and drain regions. These n4″ type impurity regions 8
The film thickness is 100 to 200 mm on the semiconductor substrate 2 sandwiched between
A floating electrode 12a made of a polysilicon layer and having a thickness of 500 to 3000 Å is formed through the human gate oxide film 10a. Then, on this floating electrode 12a, an interlayer insulating film 14 made of a thermal oxide film with a thickness of 100 to 500, for example.
The thickness of the silicide layer is 500 to 5000
A control electrode 16a is formed as a word line.

Similarly, n+ type impurity regions 8b as source and drain regions are formed on the surface of the semiconductor substrate 2 in the element region 6 forming the MOS transistor of the peripheral circuit. On the semiconductor substrate 2 sandwiched between these n+ type impurity regions 8b, a gate oxide film 10b with a film thickness of 200 to 400 nm is formed.
Via floating@[! Lower gate electrode 12b with a film thickness of 500 to 3000 Å and made of the same polysilicon layer as 12a.
is formed. On this lower gate electrode 12b, there is a control type f#! An upper gate electrode 16b is formed of the same silicide layer as 16a and has a thickness of 500 to 5,000. The stacked lower gate electrode 12b and upper gate electrode 16b together constitute the gate electrode 18.

Furthermore, on the floating type I#M 12a and the control electrode 16a,
An An (aluminum) wiring layer 24a serving as a bit line is formed through a stacked silicon oxide film 20 and PSG (phosphorous glass) film 22. And this A
The j wiring layer 24a is connected to n+ through the contact window 26a.
It is connected to type impurity region 8a.

Similarly, silicon oxide 11 is also formed on the gate electrode 18.
A20 and PS (J122 are formed, and then A
A J wiring layer 24b is formed. The Ajl wiring layer 24a is connected to the n4 type impurity region 8b and the gate electrode 18 as source and drain regions, respectively, through contact windows 26b, 26c, and 26d.

In this way, FLASHEPROM is formed and
A MOS transistor is formed in its peripheral circuit.

Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be explained using FIG. 2.

FIG. 2 shows the FLASHEPROM Xl-
X1m cross section, Y1-Yi line cross section, and Figure 1 (b
) MOS transistor X2-X2 line cross section and Y2-
Each cross section corresponding to the Y22 line break is shown.

A field oxide film 4 is formed on the semiconductor substrate 2, and FLA
The element region 6 forming the MOS transistor of the SHEPROM and its peripheral circuit is separated (see FIG. 2(a)).
. Then, on the semiconductor substrate 2 in these element regions 6, gate oxidation film J110b with a film thickness of 200 to 400 is formed using a thermal oxidation method.
(see Fig. 2(b)).

Next, using photolithography technology, a resist 32 is formed only on the gate oxide film 1110b of the element region 6 of the MOS transistor, and using this resist 32 as a mask, the gate oxide film 10 of the element region 6 of the FLASHEPROM is formed.
selectively etching away only b (see FIG. 2(c)), I! After removing the resist 32, thermal oxidation is performed to form a gate oxide film 10a to a desired thickness of 100 to 200 mm on the surface of the semiconductor substrate 2 in the element region 6 of the FLASHEPROM (see FIG. 2(d)). ).

Next, using CVD (chemical vapor deposition), a polysilicon layer 12 with a thickness of 500 to 3,000 layers is grown over the entire surface (see FIG. 2(e)), and a predetermined layer is formed on this polysilicon layer 12. After introducing the impurity, patterning is performed to form a floating electrode 12a on the gate oxide film 10a (see FIG. 2(f)).

Next, by thermal oxidation, a film thickness of 100 to 50 mm is applied to the entire exposed surface of the floating electrode 12a and the polysilicon layer 12.
Grow an interlayer insulating film 14 made of a thermal oxide film (
(See Figure 2(g)). Further, using photolithography technology, only the interlayer mM14 on the polysilicon layer 12 is selectively removed to expose the surface of the polysilicon layer 12 again (see FIG. 2<h)).

Next, a silicide layer 16 with a thickness of 500 to 5000 Å is grown on the entire surface (see FIG. 2(i)).

At the same time as this silicide layer 16, an interlayer insulating film 14
By etching and patterning the polysilicon layer 12, an interlayer insulating film 14 is formed on the floating electrode 12a.
At the same time, the control electrode 16a is formed via the lower gate electrode 12b and the upper gate electrode [! 16b are directly laminated. The lower gate electrode 12 stacked in this way
b and upper gate voltage &16b to gate voltage [i18
(see Figure 2 (j)).

Note that at this time, a polysilicon layer doped with impurities at a high concentration may be used instead of the silicide layer 16.

Next, although not shown, the control electrode 16a and the floating electrode 1
2a, upper gate electrode 16b and lower gate tli
Implanting impurity ions using i12b as a mask,
On the surface of the semiconductor substrate 2 in the element region 6, n+ type impurity regions are formed as source and drain regions, respectively. Furthermore, after sequentially laminating a silicon oxide film and a PSG film on the floating electrode 12a, the control electrode 16a, and the gate electrode 18, an Aj wiring layer as a bit line, an n+ type impurity region as a source and drain region, and the gate electrode 18 are deposited. An AJ wiring layer is formed following this. In this way, FLASHEP
MOS transistors of the ROM and its peripheral circuits are formed.

According to this embodiment, after forming the gate oxide film M10b with a thickness of 200 to 400 mm on the semiconductor substrate 2 in the element region 6, only the gate oxide film 10b in the element region 6 of the FLASHEPROM is selectively removed. Then, by forming the gate oxide film 10a again to a thickness of 100 to 200, gate oxidation 1! of the FLASHEPROM and MOS transistors is completed. 10a and 10b can be formed by controlling each to a desired thickness.

Therefore, since the gate oxide film 10a through which the tunnel current flows is formed after the gate oxide film 1110b, which requires high-temperature heat treatment, is formed, the occurrence of leakage current in a low electric field is suppressed, and the reliability of the FLASHEPROM is improved. be able to.

In addition, by thermally oxidizing the surface of the floating quadrupole 12a made of the polysilicon layer 12 into which impurities are not introduced at a very high concentration to grow the interlayer insulating film 14, the film thickness of the interlayer insulating film 14 can be increased by 100 to 500 mm. It can be controlled with high precision. Therefore, the film thicknesses of the gate oxide film 10a and the interlayer insulating film 14 can be controlled with high precision, and their capacitance ratios can be controlled with high precision.
It is possible to stabilize the characteristics of the ROM and improve reliability. The thickness of the gate oxide film 10b can also be controlled with high precision, and the performance of the MOS transistor can also be improved.

Furthermore, since the film thicknesses of these gate oxide films 10a, 10b and interlayer insulating film 14 are controlled independently, the design process can be completed in a much shorter time than in the past, and costs can be reduced. can.

Further, the gate electrode 18 is made into a two-layer structure of the lower gate electrode 12b and the upper gate electrode 16b, and the upper gate electrode '11
Since the gate electrode 6b and the control electrode 16a are formed simultaneously using the same silicide layer 16, the resistance of the gate electrode 18 can be reduced. Therefore, the gate voltage of the MOS transistor in the peripheral circuit [! 18 gate delays can be eliminated and high-speed operation can be achieved.

In the above embodiment, the interlayer insulating film 14 made of a thermal oxide film is grown on the floating electrode 12a made of the polysilicon layer 12 by a thermal oxidation method (see FIG. 2(g)).
), a silicon nitride film having a multilayer structure such as a silicon oxide film/silicon nitride film or a silicon oxide film/silicon nitride film/silicon oxide film may be used as the interlayer insulating film 14. In this case, The film thickness can be made sufficiently thicker than in the case of a thermal oxide film, and current leakage can be prevented. In addition, since silicon nitride films can be formed at low temperatures, the already formed gate oxide film 10a through which tunnel current flows is suppressed from generating leakage current in low electric fields due to high-temperature heat treatment, improving reliability. can be done.

In addition, in the above embodiment, floating electric charges [! 12 a and the lower gate 'f4 pole 12 in the subsequent process.
After growing the interlayer insulating film 14 on the entire exposed surface of the polysilicon layer 12, which becomes b, only the interlayer insulating film 14 on the polysilicon layer 12 is selectively removed and the surface of the polysilicon layer 12 is grown again. After exposing, a silicide layer 16 is grown on the entire surface (see FIG. 2(g) to (i)).
, may be a process as shown in FIG.

Here, Fig. 3 (a>, (b)) corresponds to Fig. 2 (g) to (i).
It is a process cross-sectional view corresponding to the FLAS of FIG. 1(a).
Xl-Xi line cross section and Yl-Ylli cross section of HEPROM and X2-X of MoS transistor in FIG. 1(b)
2-2 line cross section and a cross section corresponding to Y2-Y22 line are shown, respectively.

That is, after growing the interlayer insulating film 14 on the entire exposed surface of the floating electrode 12a and the polysilicon layer 12, successively, for example, a polysilicon layer 34 is thinly deposited on the entire surface (
(See Figure 3(a)).

Next, the polysilicon layer 34 and interlayer insulating film 14 on the polysilicon layer 12 are selectively removed to expose the surface of the polysilicon layer 12 again, and then a silicide layer 16 is formed on the entire surface.
(See Figure 3(b)).

In this case, since the polysilicon layer 34 is deposited over the entire surface following the growth of the interlayer insulating film 14, it is possible to prevent contamination of the interlayer insulating film 14 and prevent deterioration of device characteristics.

Further, in the above embodiment, the interlayer insulating film 14 on the polysilicon layer 12, which will become the lower gate electrode 12b in a later step,
is removed, and an upper gate electrode 16 is formed on the entire surface in a later process.
By growing the silicide layer 16, which serves as b, the lower gate electrode &12b and the upper gate electrode 16b are directly laminated (see FIGS. 2(h) to (j)). It may be a process as shown.

Here, FIGS. 4(a) to (d) are similar to FIGS. 2(g) to (j).
It is a process cross-sectional view corresponding to the FLAS of FIG. 1<a).
Xl-Xi line cross section and Yl-Yl line cross section of HEPROM and X2-X2 of MOS transistor in FIG. 1(b)
A line cross section and a cross section corresponding to the Y2-Y22 line are shown, respectively.

That is, after growing the interlayer insulation M14 on the polysilicon layer 12 which will become the floating electrode 12a and the lower gate electrode 12b in a later step by a thermal oxidation method (see FIG. 4(a)), The interlayer insulating film 14 is not removed entirely, but only the portion of the interlayer insulating film 14 on the polysilicon layer 12 that extends onto the field oxide film 4 is removed (see FIG. 4(b)).

Next, after growing a silicide layer 16 on the entire surface (the fourth
By etching and patterning the silicide layer 16, interlayer insulating film 14, and polysilicon layer 12 at the same time, a control electrode 16a is formed on the floating electrode 12a via the interlayer insulating film 14. , a lower gate electrode 12b and an upper gate electrode 16b are formed. At this time, the lower gate electrode 12b and the upper gate electrode 1
6b is stacked directly on the field oxide film 4 to form the gate electrode 18. j, In the element region 6, the lower gate electrode 12b and the upper gate electrode 16b
There is an interlayer insulation WA14 between the two (see FIG. 4(d)).

Therefore, the lower gate voltage [! Even if there is a pinhole in 12b, the gate oxide film 10b under the lower gate electrode 12b is not damaged by etching to remove the interlayer insulation 814, and deterioration of device characteristics can be prevented. Further, even if the area of the element region 6 becomes smaller due to higher density of elements, it is possible to easily open a window in the interlayer insulating film 14 for connection to the upper gate electrode 16b.

Alternatively, the process may be as shown in FIG.

Here, FIGS. 5(a) to (d) are similar to FIGS. 2(g) to (j).
It is a process cross-sectional view corresponding to the FLAS of FIG. 1(a).
XI-XI line cross section and Yl-Yl line cross section of HEPROM and X2-X2 of MOS transistor in FIG. 1(b)
A line cross section and a cross section corresponding to the Y2-Y22 line are shown, respectively.

That is, after growing the interlayer insulating film 14, a thin polysilicon layer 36 is formed on the entire surface (see FIG. 5(a)), and the polysilicon layer 36 on the field oxide film 4 and the interlayer insulating film 14 are selectively grown. (see FIG. 5(b)), and then, after growing a silicide layer 16 on the entire surface (see FIG. 5(c)), at the same time as this silicide layer 16, a polysilicon layer 36 and an interlayer insulating film are grown. By selectively etching and patterning the polysilicon layer 14 and the polysilicon layer 12,
A gate electrode 18 consisting of a lower gate electrode 12b and an upper gate electrode I#116b is formed (FIG. 5('c)).

At this time, the lower gate electrode 12b and the upper gate electrode 16b are directly laminated only at a predetermined portion on the field oxide film 4 in the peripheral circuit or the like.

As a result, etching for patterning the control electrode 16a and gate electrode 18 is performed on the silicide layer 16, polysilicon layer 36, and interlayer insulating film 14 for both cells and peripheral circuits.
, polysilicon layer 12 will be formed at the same time.

Therefore, contamination and damage to the interlayer insulation 814 can be prevented, and uniform etching of the gate electrode 18 and the like can be achieved.

Furthermore, although the above embodiments have been explained in the case of FLASHEPROM, the present invention is also applicable to the case of EPROM, for example.

In this case, the structure is almost the same as that shown in FIG.
It's just J. Therefore, although not shown in the drawings, in the manufacturing method, the gate oxide film of the EPROM and the gate oxide film of the MOS transistor of the peripheral circuit are formed in the steps shown in FIGS. The film thickness may be controlled to a desired thickness based on the characteristics of each transistor. In this case, the gate oxide film of the EPROM and the gate oxide film of the MOS transistor of the peripheral circuit may have the same thickness.

Further, the present invention is also applicable to the case of E'PROM.

This case is shown in FIG. 6 as another embodiment of the present invention.

That is, in the steps shown in FIGS. 2(a) and 2(b) in the above embodiment, the gate oxide film 1 of the E2PROM 38 is
0c and the gate oxide film 10b of the MOS transistor 40 of the peripheral circuit are formed to have the same thickness.
A part of the gate oxide film 10C of No. 8 is selectively etched away. Then, thermal oxidation is performed again, and E'PROM3
A tunnel oxide film 10d having a desired thickness, for example, 100 layers, may be formed on a part of the gate oxide layer 1110c of No. 8.

Thereafter, in the same manner as in the above embodiment, the gate oxide film 10 is
The floating electrode 12c on the tunnel oxide film 10d and the lower gate electrode 12b on the gate oxide film 10b are formed in the same layer. In addition, the control electrode 16c and the upper gate electrode &12
b and are formed in the same layer. In this way, as shown in FIG. 6, a semiconductor memory device including an E2PROM 38 to which the present invention is applied and a MOS transistor 40 of its peripheral circuit can be formed.

[Effects of the Invention] As described above, according to the present invention, a floating electrode provided on a semiconductor substrate via a first gate insulating film and a control electrode formed on the floating electrode via an interlayer insulating film. and a transistor having a gate electrode provided on the semiconductor substrate with a second gate insulating film interposed therebetween, the gate electrode of the transistor being formed by laminating a lower gate electrode and an upper gate electrode. A layered structure is formed, and the first and second gate insulating films of the memory cell and transistor are controlled to desired thicknesses, respectively, and a floating electrode and a lower gate electrode are formed on the first and second gate insulating films, respectively. are formed in the same layer, an interlayer insulating film of a desired thickness is formed on the floating electrode, and a control electrode and an upper gate electrode are formed in the same layer. The gate insulating film of the memory cell and the interlayer insulating film of the memory cell can be controlled to desired thicknesses, the resistance of the upper gate electrode of the transistor can be lowered, and the number of design steps can be shortened.

This makes it possible to stabilize element characteristics, improve reliability, enable high-speed operation, and further reduce costs.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a process cross-sectional view showing a method for manufacturing the semiconductor device in FIG. 1, and FIG. 3 is a manufacturing method according to the process cross-sectional view in FIG. 4 is a process sectional view explaining another modification of the manufacturing method according to the process sectional view in FIG. 2; FIG. 5 is a manufacturing process sectional view according to the process sectional view in FIG. FIG. 6 is a cross-sectional view showing a method for manufacturing a semiconductor device according to another embodiment of the present invention; FIG. 7 is a cross-sectional view showing a conventional semiconductor device. . In the figure, 2...Semiconductor substrate, 4...Field oxide film, 6...Element region, 8a, 8b...N" type impurity region, 10a ,1
0b, 10c, 52.60...Gate oxide film, 10d...Tunnel oxide film, 12.34.36...Polysilicon layer, 12a
, 12c, 54... floating electrode, 12b...
...Lower gate electrode, 14.56...Interlayer insulating film, 16...Silicide layer, 16a, 16c, 58...Control electrode, 16b
... Upper gate electrode, 18.62 ... Gate electrode, 20 ... Silicon oxide film, 22 ... PSG film, 24a, 24b ... --Aj wiring layer, 26a, 26
b, 26c, 26 d --- Contact window, 32 --- Resist, 38 --- E2 FROM. 40. 66...MOS transistor, 64...
・FLASH EPROM.

Claims (1)

[Claims] 1. A memory cell having a floating electrode provided on a semiconductor substrate with a first gate insulating film interposed therebetween and a control electrode formed on the floating electrode with an interlayer insulating film interposed therebetween; In a semiconductor device including a transistor having a gate electrode provided on a semiconductor substrate via a second gate insulating film, the gate electrode has a two-layer structure in which a lower gate electrode and an upper gate electrode are laminated, The floating electrode and the lower gate electrode are formed in the same layer, the control electrode and the upper gate electrode are formed in the same layer, and the first and second gate insulating films and the interlayer insulating film are each formed as desired. A semiconductor device characterized in that the film thickness is controlled to . 2. The semiconductor device according to claim 1, further comprising a thinned tunnel insulating film in a portion of the first gate insulating film of the memory cell. 3. Form a field oxide film on the semiconductor substrate and
and a first step of separating a second element region; a second step of forming a gate insulating film on the semiconductor substrate in the first and second element regions, respectively; and a first conductive film on the entire surface. After depositing the layer, the third layer is patterned into a predetermined shape to form a floating electrode and a lower gate electrode made of the first conductive layer on the gate insulating film in the first and second element regions, respectively. a fourth step of forming an interlayer insulating film on the entire surface and then removing part or all of the interlayer insulating film on the lower gate electrode; and depositing a second conductive layer on the entire surface, and then removing a predetermined amount of the interlayer insulating film on the entire surface. patterning to form a control electrode made of the second conductive layer on the floating electrode via the interlayer insulating film, and an upper gate electrode made of the second conductive layer on the lower gate electrode. a fifth step of laminating layers. 4. The method according to claim 3, wherein the second step comprises:
After selectively etching away either one of the gate insulating films in the first or second element region, a gate insulating film thinner than the other gate insulating film is formed, and the first and second gate insulating films are removed by selective etching. A method of manufacturing a semiconductor device, comprising the step of forming first and second gate insulating films each having a desired thickness on the semiconductor substrate in an element region. 5. The method according to claim 3 or 4, wherein the second step includes the step of selectively forming a tunnel insulating film after removing a part of the gate insulating film of the memory cell. A method for manufacturing a semiconductor device. 6. The method according to any one of claims 3 to 5,
The fourth step includes forming the interlayer insulating film on the entire surface, forming a polysilicon layer on the entire surface, and then removing at least a portion of the polysilicon layer on the lower gate electrode. A method for manufacturing a semiconductor device, characterized in that: