JPH021176A - Nonvolatile semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase the degree of integration of an EEPROM by forming the gate electrode of a selective transistor in a laminated structure consisting of a first conductive film formed simultaneously with the floating gate of a memory transistor and a second conductive film formed simultaneously with the control gate of the memory transistor, and causing them to be in direct contact with each other, thereby reducing an internal between cells. CONSTITUTION:A second layer polycrystalline silicon film 7, an interlayer insulating film 5, and a first layer polycrystalline silicon film 4 are selectively etched sequentially to form patterns of a floating gate 41 and a contact gate 71 of a memory transistor, and laminated gate electrodes 42, 72 of a selective transistor. With these gate electrodes as masks, ion implantation is performed to form n<+>-type layers 81 to 83 which will serve as sources and drains of each of the transistors. Finally, the entire surface is covered with an insulating film 9 and a contact hole 9 is formed to arrange a bit line 11 made of an Al film. Accordingly, the laminated electrodes 42, 72 of the selective transistor ST are kept in direct contact with each other through an opening 6 arranged in a gate region. This allows redundant spaces to be eliminated and higher degree of integration of EEPROMs to be achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a nonvolatile semiconductor memory device using a rewritable memory transistor having a floating gate and a control gate, and a method for manufacturing the same.

(Prior Art) An electrically rewritable nonvolatile semiconductor memory device (EEPROLvl) is known in which a memory cell is configured by connecting a memory transistor having a structure in which a floating gate and a control gate are stacked and a selection transistor for address selection in series. ing.

FIG. 8 is a plan view showing a memory cell structure of an example of such an EEFROM, and its AA' and BB' cross-sectional views. A floating gate 34 made of a first layer polycrystalline silicon film is formed on a p-type St substrate 31. A memory transistor M in which a control gate 36° and a second layer polycrystalline silicon film are laminated.
A memory cell is configured by connecting a transistor T and a selection transistor ST in series. The gate structure of the selection transistor ST includes a gate electrode 342 made of a first layer polycrystalline silicon film and a second gate electrode 342, which is basically the same as that of the memory transistor MT.
It has a stacked structure of gate electrodes 36□ made of layered polycrystalline silicon films. After depositing a first layer polycrystalline silicon film, an interlayer insulating film 35 is formed, a second layer polycrystalline silicon film is deposited thereon, and then these laminated films are sequentially selectively etched to form a memory. This is because the gate portions of the transistor MT and the selection transistor ST are formed. However, as is clear from FIG. 8(b), the gate insulating film is
Of the first gate insulating film 32, the memory transistor M
A thin second gate insulating film 33 is formed in the rewriting region partially overlapping the drain on the T side. After forming gate electrodes for each part, ion implantation is performed using this as a mask to
An n+ type layer 37 that becomes a drain is formed, and then the entire surface is covered with CVD insulation H38 and a bit line 40 made of Al1m is formed.
is installed. FIG. 8(a) shows two memory cells adjacent in the direction orthogonal to the bit line, but the floating gates 34 of each memory transistor MT are independent, and the control gate 36° is common in this direction. It is located in Gate electrode 342.36 of selection transistor ST
□ is also arranged continuously in this direction. However, in order to short-circuit the gate electrodes 34□ and 362, the upper gate electrode 36□
is partially removed on the field area.

That is, the stacked gate electrode 34 of the selection transistor ST
2.36□ is short-circuited between the contact hole 41 and the short-circuit conductor film 42 outside the cell area.

The operation of this EEFROM cell is as follows.

During writing, a high positive voltage is applied to the gate of the selection transistor ST, a ground potential is applied to the drain, and the memory transistor M
Apply a high positive voltage to the ηi control gate of T. The sauce is 5
Heat to about 50 mph or in the oven. At this time, a high electric field is applied to the thin gate insulating film 33 of the memory transistor MT,
Electrons are injected from the drain to the floating gate 34 by a tunnel current. As a result, the threshold value of memory transistor MT moves in the positive direction. During erasing, a high positive voltage is applied to the gate and drain of the selection transistor ST,
The control gate 36 of the memory transistor MT is set to the ground potential, and the source is set to about 5V or oven. At this time, a positive high voltage is transmitted to the drain of the memory transistor MT via the selection transistor ST, and a high electric field opposite to that during writing is applied to the thin gate insulating film 33. This allows the floating gate 34. electrons are emitted, and the threshold shifts in the negative direction. Reading is performed by turning on the selection transistor ST, keeping the control gate of the memory transistor MT Ov, and reading its conductance.

In such an EEFROM, the selection transistor ST
Only the first layer polycrystalline silicon film is originally required as the gate electrode. Nevertheless, as mentioned above, the stacked structure of two layers of polycrystalline silicon films for memory transistors is used as the gate electrode of this selection transistor, and these are short-circuited outside the memory cell area as follows. Due to reasons such as. When etching the first layer polycrystalline silicon film, it is common to expose it to the etching atmosphere for an additional 30% of the etching time required to prevent etching residue. The thicker the first polycrystalline silicon film, the longer the time required for overetching.
As a result, a situation arises in which the exposed gate insulating film is etched and scraped down to the substrate. In order to prevent this, the first layer polycrystalline silicon film should be thinner. However, if the first layer polycrystalline silicon film is made thinner, the resistance of the gate electrode of the selection transistor using this film increases. In the first place, the first layer polycrystalline silicon film needs to have a low concentration of impurities such as phosphorus in order to ensure sufficient breakdown voltage of the interlayer insulating film formed on its surface by thermal oxidation, and the sheet resistance is usually 100Ω. / It's more expensive than my mouth. Therefore, for the selection transistor as well, a laminated structure of a first layer polycrystalline silicon film and a second layer polycrystalline silicon film is used, and these are short-circuited using a metal film on the field region as described above.

Incidentally, the bit line 40 is formed of an Ag film as described above. In addition, the first layer gate electrode 34 of the selection transistor
A short-circuiting conductor film 42 is used to short-circuit □ and the second layer gate electrode 362, and this is made of A47, which is the same as the bit line 40.
If a film is used, the distance between adjacent bit lines 40 requires a region width necessary to form the shorting conductor 42 and a minimum processing dimension width necessary to separate the Al pattern. This is a major factor hindering higher integration of memory cells.

(Problems to be Solved by the Invention) As described above, in the conventional EEFROM cell, the substantial The problem was an increase in cell size.

An object of the present invention is to provide an EEPROM that solves these problems and a method for manufacturing the same.

[Structure of the Invention] (Means for Solving the Problems) The EEFROM according to the present invention has the gate electrode of the selection transistor connected to the first layer conductor 1 which is formed simultaneously with the floating gate of the memory transistor and the control gate of the memory transistor. It is characterized by having a laminated structure of a second layer conductor film formed at the same time, and in direct contact between these layers.

The present invention also provides, when manufacturing such an EEPROM,
A first layer conductor film is formed on a semiconductor substrate via a necessary gate insulating film, an interlayer insulating film is formed thereon, and an opening is formed in a region where a gate electrode of the selection transistor is provided.
A second layer conductor film is formed in direct contact with the first layer conductor film through this opening, and then the second layer conductor film, the interlayer insulating film, and the first layer conductor film are sequentially selectively etched to form the floating gate of the memory transistor. The present invention is characterized in that the control gate and the gate electrode of the selection transistor are formed separately.

(Function) According to the present invention, by directly contacting the laminated film of the first layer conductor film and the second layer conductor film constituting the gate electrode of the selection transistor, they can be connected using an Alp film as in the conventional method. Compared to the structure and method of short-circuiting, the cell spacing can be reduced and the EEPROM can be highly integrated.

(Example) The present invention will be explained in detail below.

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along line AA' of the memory cell structure of one embodiment.

This is shown in FIGS. 2(a) to 2(f), which are cross-sectional views of the manufacturing process (
The manufacturing process will be explained with reference to FIG. 1(b) (corresponding to FIG. 1(b)). Using a p-type Si substrate 1, a first gate insulating film 2 is formed by thermal oxidation, and a resist pattern 21 having an opening in the rewriting area of the memory transistor is formed thereon by light exposure technology (see FIG. 2(a)). )). Using this resist pattern 21, the first gate insulation IJ! 2 and remove the resist pattern 21, a thin second gate insulating film 3 is formed on the exposed surface of the substrate 1 by thermal oxidation.
After that, a phosphorus-doped first layer polycrystalline silicon film 4 is deposited on the entire surface. The first polycrystalline silicon film 4 is then patterned to separate floating gates in a direction perpendicular to the bit lines. The structure does not appear in the cross section of the figure. Thereafter, an interlayer insulating film 5 is formed on the surface of the first layer polycrystalline silicon film 4 by, for example, thermal oxidation, and a resist pattern 22 having an opening in the gate region of the selection transistor is formed thereon again by light exposure technology. (FIG. 2(b)) Using this resist pattern 22, the interlayer insulating film 5 is selectively etched, an opening 6 is opened in the gate region of the selection transistor, and a phosphorus-doped first polycrystalline silicon film 7 is deposited. The second layer polycrystalline silicon film 7 is
Direct contact is made with the first layer polycrystalline silicon film 4 through the opening 6. After that, this second layer polycrystalline silicon film 7
A resist pattern 23 for separating the gate part of the memory transistor and the gate part of the selection transistor is formed thereon again by the light exposure technique (FIG. 2(C)). Then, using this resist pattern 23 as a mask, the second layer polycrystalline silicon film 7, the interlayer insulating film 5, and the first layer polycrystalline silicon film 4 are sequentially selectively etched by reactive ion etching, thereby forming the floating gate 41 of the memory transistor and the control layer. Gate 7, stacked gate electrode 4 of selection transistor
2.72 is patterned (FIG. 2(d)). Using these gate electrodes as a mask, ion implantation is performed to form the sources of each transistor.

n+ type layers 81 to 8, which become drains; (Fig. 2(e)). Finally, the entire surface is covered with a CVD insulating film 9, a contact hole 10 is opened, and a bit line 11 made of an Al1 film is provided (FIG. 2(f)).

As is clear from FIG. 1, in this embodiment, the stacked gate electrodes 4° and 72 of the selection transistor ST are in direct contact through the opening 6 provided in the gate region. Therefore, compared to the conventional example shown in FIG. 8 in which the stacked gate electrodes are short-circuited by the AFi film outside the cell region, there is no need for wasted occupying area between the bit lines, and the memory cells can be highly integrated.

In the above embodiment, only a portion of the gate insulating film of the memory transistor MT that overlaps with the drain is formed into a thin second gate insulating film 3, and the rest is the same as that of the selection transistor ST. However, the entire gate insulating film of the memory transistor is The present invention is also effective when using a thin second gate insulating film through which a tunnel current can flow. FIGS. 3(a) to 3(f) are sectional views showing the manufacturing process of the EEFROM of such an embodiment, corresponding to FIGS. 2(a) to 2(f) of the previous embodiment. In this example, after forming the first gate insulating film 2, a resist pattern 21' is formed with an opening over the entire memory transistor area, and thereby the second gate insulating film 2 in the memory transistor area is removed. Afterwards, a second gate insulating film 3 is formed here. The rest is the same as in the previous embodiment.

Furthermore, although the above embodiment shows the case where there is only one memory transistor MT, the present invention can also be applied to a NAND cell structure in which a plurality of memory transistors are connected in series.

FIG. 4 is a plan view of one cell section when the present invention is applied to an EEPROM having such a NAND cell.

In this example, four memory transistors MT, ~M
A NAND cell is constituted by T4 and two selection transistors ST, ST2. Each memory transistor has a floating gate 41. made of a first layer polycrystalline silicon film.
~414, and control gates 711 to 714 made of a second layer polycrystalline silicon film, selection transistors ST, .
ST2 is a stacked gate electrode 421, 7□3.42 of a first layer polycrystalline silicon film and a second layer polycrystalline silicon film, respectively.
It has □, 7□2. And each of these selection transistors S
As in the previous embodiment, an opening 6 is provided between the stacked gate electrodes of T.
．． ．． 6□ allows direct contact I.

This embodiment also provides the same effects as the previous embodiment.

In the above embodiment, the two-layer gate electrode of the selection transistor is brought into direct contact on its channel region, but in this case the contact region width must be smaller than the gate length. Therefore, if the gate length is small, it is difficult to make good contact. Also opening 6. ．． When opening 62, damage caused by RIE may cause deterioration of the dielectric strength of the gate insulating film 2 and decrease in reliability. In such cases, it is desirable to make contact over the field area.

FIGS. 5(a) and 5(b) show an EEPROM of such an embodiment.
FIG. 2 is a plan view and a cross-sectional view taken along the line AA'. Components corresponding to those in FIG. 1 are given the same reference numerals as in FIG. 1. As shown in the figure, the gate electrodes 42, 7□ of selection transistors successively arranged for adjacent memory cells are brought into direct contact through an opening 6 provided on the field insulating film.

FIGS. 6(a) to 6(c) show a manufacturing process focusing only on the selection transistor section of the EEPROM. First, a field insulating film 24 is formed on a p-type silicon substrate 1 using the usual LOCO3 method, and after forming a gate oxide film 2 of approximately 400 layers using HCII oxidation at 900°C, a first layer polycrystalline silicon film 4 is formed. is deposited by thermal CVD. This polycrystalline silicon film 4 was heated at 900° C. in a POCΩ3 atmosphere.

Perform phosphorus diffusion for 10 minutes (Figure 6(a)). The field region is doped with a p-type impurity in advance to form an anti-inversion layer 25. Next, after forming an interlayer insulating film 5 on the surface of the first layer polycrystalline silicon film 4 by thermal oxidation, a photoresist pattern 26 is formed thereon to selectively cover the interlayer insulating film 5 over the field region. The opening 6 is provided by removing the opening 6 (FIG. 6(b)). Then, the photoresist pattern 26 is removed, and a second layer polycrystalline silicon film 7 is deposited.
This is doped with phosphorus (Fig. 6(C)).

Thereafter, in the same manner as in the previous embodiment, the first and second layer polycrystalline silicon films 4 and 7 are patterned to form the floating gate and control gate of the memory transistor as well as the gate electrode of the selection transistor.

According to this embodiment, in addition to obtaining the same effect as the embodiment shown in FIG. 1, even when the gate length of the selection transistor is short, contact between the two-layer gate electrodes can be made reliably, and the EEFROM can be made reliable. The effect of improving sexual performance can be obtained.

Direct contact of the double-layer gate electrode of the selection transistor on the field region can be similarly applied to NAND cell type memo type EEFROM. The $14 configuration of the example is shown in Figure 4.
The corresponding figures are shown in FIG. Both the selection transistor ST on the bit line side and the selection transistor ST2 on the source side,
Openings 68 and 6□ provided on the field insulating film provide direct contact/tact for the two-layer gate electrode.

In the above embodiments, the case where the interlayer insulating film is a thermal oxide film-layer was explained, but if this is made into a laminated structure of, for example, a silicon oxide film-silicon nitride film, or a silicon oxide film-silicon nitride film-silicon oxide film, The present invention is also effective when the membrane has a three-layer structure.

A tantalum oxide film or the like can also be used as an interlayer insulating film. In addition, POC is used for doping polycrystalline silicon films.
In addition to Ω3, ion implantation can also be used, and as the doping species, in addition to P, As, Sb, etc. can be used.

Furthermore, a conductor film other than a polycrystalline silicon film can be used as the gate electrode material.

Other vehicle inventions can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, by bringing the stacked gate electrodes of the selection transistors into direct contact with each other, it is possible to eliminate wasted space and realize a highly integrated EEPROM. .

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are a plan view showing a memory cell structure according to an embodiment of the present invention and its AA' cross-sectional view, and FIGS. 2(a) to 2(b) are
(f) is a sectional view of the manufacturing process, FIGS. 3(a) to (f) are sectional views of the manufacturing process of other embodiments, FIG. 4 is a 11ε side view of another embodiment applied to a NAND cell, 5(a) and 5(b) are an if''-plane view showing the memory cell structure of another embodiment and its AA' cross-sectional view, and FIGS. 6(a) to 5(b) are
(C) is a cross-sectional view showing the manufacturing process of the selection transistor part, Figure 7 is a plan view showing another embodiment applied to a NAND cell, and Figures 8 (a), (b), and (c) are conventional memory It is a top view which shows a cell structure, and its AA', BB' cross-sectional view. DESCRIPTION OF SYMBOLS 1...p-type Si substrate, 2...1st gate insulating film, 3
... Second gate insulating film, 4... First layer polycrystalline silicon film, 41... Floating gate, 4□... First layer gate electrode of selection transistor, 5... Interlayer insulating film, 6...
・Contact opening, 7... second layer polycrystalline silicon film,
7. ...Control gate, 7□...Second layer gate electrode of selection transistor, 8...N+ type layer, 9...CVD
Insulating film, 10... Contact hole, 11... Bit line, 24... Field insulating film, MT... Memory transistor, ST... Selection transistor. Applicant's agent Patent attorney Takehiko Suzue (b) (c) Figure (b) (a) (b) (C) Figure (b) Figure (b) Figure Figure (b) Small diagram

Claims (4)

[Claims] (1) A non-volatile semiconductor memory in which a memory cell consisting of at least one memory transistor in which a floating gate and a control gate are stacked via an interlayer insulating film and a selection transistor connected in series with the memory cell is formed on a semiconductor substrate. In the device, the gate electrode of the selection transistor includes a first layer conductor film formed at the same time as the floating gate of the memory transistor, and a second layer conductor film formed at the same time as the control gate of the memory transistor. A non-volatile device having a structure in which the first layer conductor film and the second layer conductor film are in direct contact through an opening made in the interlayer insulating film. Semiconductor storage device. (2) The nonvolatile semiconductor memory device according to claim 1, wherein the gate electrode of the selection transistor is in direct contact with a channel region. (3) The nonvolatile semiconductor memory device according to claim (1), wherein the gate electrode of the selection transistor is in direct contact with a field insulating film. (4) A non-volatile semiconductor memory in which a memory cell consisting of at least one memory transistor in which a floating gate and a control gate are stacked via an interlayer insulating film and a selection transistor connected in series with the memory cell is formed on a semiconductor substrate. A method for manufacturing a device, the method comprising: forming a gate insulating film with a required thickness in each of a memory transistor region and a selection transistor region on a semiconductor substrate, and then forming a first layer conductor film; An interlayer insulating film is formed on the conductor film, an opening is selectively formed in the gate electrode region of the selection transistor in the interlayer insulating film, and a second layer conductor film is formed to make direct contact through the opening. and a step of sequentially selectively etching the second layer conductor film, the interlayer insulating film, and the first layer conductor film to form a floating gate, a control gate, and a gate electrode of the selection transistor of the memory transistor. A method for manufacturing a nonvolatile semiconductor memory device.