JPH0750396A - Nand type non-volatile semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a NAND non-volatile semiconductor memory device which is much smaller in cell area than a non-volatile semiconductor device provided with a floating gate. CONSTITUTION:A non-volatile semiconductor memory device is equipped with gate electrodes 36 and 38 and a gate insulating film 34 provided under the gate electrodes 36 and 38, and data are stored by accumulating electric charge in the gate insulating film 34, wherein the gate electrodes 36 and 38 are arranged in parallel adjacent to each other on the gate insulating film 34. A second gate electrode layer 38 is arranged between first gate electrode layers 36 overlapping them, whereby the first gate electrode layers 36 and the second gate electrode layers 38 are alternately arranged adjacent to each other in parallel. An gate insulating film is formed of ONO film. The gate insulating layer is formed on a semiconductor layer formed on the SOT insulating layer. A side wall may be provided to the side of a first gate electrode layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a NAND type non-volatile semiconductor memory device and a method of manufacturing the same, and more particularly, to significantly reduce the cell area as compared with a non-volatile semiconductor memory device having a floating gate. And a method for manufacturing the same.

[0002]

2. Description of the Related Art As a nonvolatile semiconductor memory device capable of electrically writing and erasing information, FIGS.
There is known a NOR type E ² PROM having a floating gate as shown in FIG. In the NOR type E ² PROM, the gate insulating film 4, the floating gate 6, the intermediate insulating film 8 and the control gate 10 are laminated on the surface of the semiconductor substrate 2. An element isolation region (LOCOS) 15 is formed on the surface of the semiconductor substrate 2.
On the surface of the semiconductor substrate 2 surrounded by the OS 15, the drain diffusion region 11 and the source diffusion region 13 are formed in self-alignment with the control gate 10. The drain diffusion region 11 and the source diffusion region 13 are composed of n ⁺⁺ diffusion layers.

An interlayer insulating layer 12 made of silicon oxide or the like is deposited on the control gate 10. A contact hole 14 for contacting the drain diffusion region 11 is formed in the interlayer insulating layer 12. Bit line 1 through this contact hole 14
6 is connected to the drain diffusion region 11.

In the NOR type, as shown in FIG. 17B, the bit line 16 is formed in the drain diffusion region 11 formed between the two memory cell transistors in order to extract information for each memory cell. Contacts are formed. That is, the NOR type requires one bit line contact for every two bits. Therefore, in the NOR type, the area required to form one bit line contact is divided into two memory cells.

A NAND type E ² PROM is known as a non-volatile semiconductor memory device capable of further reducing the cell area as compared with the NOR type non-volatile semiconductor memory device. As shown in FIGS. 18 and 19, the NAND type E ² PROM has a gate insulating film 4, a floating gate 6, an intermediate insulating film 8 and a control gate 10 stacked on the surface of a semiconductor substrate 2, and has a plurality of cell transistors MT. (8 bits in the figure) are connected and arranged in series.
Select transistors ST are arranged at both ends of the cell transistors MT grouped into a plurality of groups. On the surface of the semiconductor substrate 2 located on both sides of the cell transistor MT and the select transistor ST, N shown in FIG.
Source / drain diffusion regions 20, 22a, 22b are formed so as to have an AND type memory cell structure.
These diffusion regions 20, 22a and 22b are composed of n ⁺⁺ diffusion layers.

In FIG. 19, W1 to W8 indicate word lines which become the control gate 10 shown in FIG. 18, and S1 and S2 indicate word lines which become the gate electrode of the selection transistor ST. In addition, in FIG.
B1 and B2 correspond to the bit line 16.

In the case of such a NAND type E ² PROM, the contact of the bit line 16 is, as shown in FIG. 18A, one of the select transistors through the contact hole formed in the interlayer insulating layer 12. This is performed for the ST diffusion region 22a and is not performed for each cell transistor MT. That is, in the case of the NAND type E ² PROM, two selection transistors ST are required, but the occupied area thereof is divided into the number of grouped cell transistors ST (the number of bits, 8 bits in the figure). To be Since the recent NAND type memory has a 16-bit configuration, it is possible to further reduce the cell area per bit as compared with the NOR type memory.

[0008]

However, the NAND memory also has some structural improvements as described below. First, as shown in FIGS. 18 (B) and 19 (B), the floating gate 6 is formed on the LOCOS 15 so as to extend by the overlap length l in order to increase the coupling ratio regarding capacitance. ing. That is, the cell area is increased in the word line (control gate 10) direction by the overlap length l.

Secondly, when the normal LOCOS 15 is formed, a bird's beak occurs at the end of the LOCOS 15, and the transistor width must be designed in consideration of this bird's beak length ψ. Therefore, the cell area is increased by the amount corresponding to the length of the bird's beak length ψ.

Third, in the process using the normal LOCOS 15, the contact hole 14a (see FIG. 18) is used.
(See (A)) when forming the contact hole 14a
The margin μ is necessary to prevent the edge of the above from riding on the LOCOS 15, and this margin μ is a factor for enlarging the memory cell.

Fourth, in the case of a NAND type memory,
The function of the n ⁺⁺ layer corresponding to the source / drain regions 20, 22a, 22b is that the memory states of the memory cell are "1", "0".
To pass the current to determine. Therefore,
The presence of the n ⁺⁺ layer for passing the signal current increases the cell area.

The present invention has been made in view of the above circumstances, and a NAND type non-volatile semiconductor memory device capable of significantly reducing the cell area as compared with a non-volatile semiconductor memory device having a floating gate, and a manufacturing method thereof. The purpose is to provide.

[0013]

In order to achieve the above object, a first nonvolatile semiconductor memory device according to the present invention comprises:
A non-volatile semiconductor memory device having a gate electrode and a gate insulating film disposed under the gate electrode, storing electric charges in the gate insulating film to store information, wherein a plurality of gate electrodes are provided. It is characterized in that it has a NAND type memory cell structure which is arranged closely in parallel on the gate insulating film.

By arranging the gate electrode of the second layer so as to overlap between the gate electrodes of the first layer, the gate electrode of the first layer and the gate electrode of the second layer are close to each other and alternately arranged in parallel. It is preferable to arrange them. The gate insulating film is
It is preferable to have a thin film layer having an electron trap function. This thin film layer is preferably a silicon nitride film or a multilayer film including a silicon nitride film.

It is preferable that the gate insulating layer is formed on the semiconductor layer formed on the SOI insulating layer, and the element isolation region is formed by the SOI technique. A second non-volatile semiconductor memory device according to another aspect of the present invention has a gate electrode and a gate insulating film arranged under the gate electrode, and stores charges in the gate insulating film to store information. And a plurality of gate electrodes adjacent to each other in parallel on the gate insulating film, and between the gate electrodes of the first layer so as to have a NAND type memory cell structure. The second-layer gate electrodes are arranged so as to overlap each other, and sidewalls are formed on the sides of the first-layer gate electrodes.

It is preferable that the sidewall is made of polysilicon. The manufacturing method for manufacturing the second non-volatile semiconductor memory device includes: a step of forming a first gate insulating film on a semiconductor substrate, in which charges are stored and information can be written; and a first gate insulating film. On top of the,
The step of forming the first conductive layer, the resist film having a predetermined pattern is formed on the surface of the first conductive layer, and the first conductive layer is processed by etching using the resist film, and at a predetermined interval. From the step of forming the first-layer gate electrode at a predetermined interval, the step of forming a sidewall on the side portion of the first-layer gate electrode, and the step of forming the sidewall on the first-layer gate electrode, Forming a second gate insulating film capable of writing information by accumulating charges;
On the second gate insulating film, a second-layer gate electrode is formed in a gap between the first-layer gate electrodes, and the first-layer gate electrode and the second-layer gate electrode are NAND type. And alternately arranging them in parallel so as to form memory cells.

In the above manufacturing method, the channel length formed by the gate electrode of the first layer and the channel length formed by the gate electrode of the second layer are substantially equal to each other. The pattern of the resist film for patterning the gate electrode is preferably thinned by plasma treatment.

[0018]

In the first and second nonvolatile semiconductor memory devices of the present invention, the cell transistors for storing information by accumulating charges in the gate insulating film are arranged in a NAND type, and the gate electrodes are arranged close to each other. As a result, it is not necessary to form a diffusion layer for the source / drain regions between the cell transistors, as compared with a normal NAND type memory having a floating gate. This is because the diffusion layer for the source / drain regions is simply a conductive layer for passing a signal current. Therefore, if the gate electrode is placed close to the gate insulating film having a memory effect, a NAND type circuit is formed. This is because it can be configured and the diffusion layer is unnecessary. Therefore, in the present invention, as much as this diffusion layer is eliminated,
The memory cell can be reduced.

The arrangement of the gate electrodes close to each other can be easily realized by arranging the gate electrodes of the second layer so as to overlap each other between the gate electrodes of the first layer. Further, in the present invention, since the structure does not have a floating gate, the floating gate and the element isolation region do not overlap each other, and the cell area can be reduced also in this respect.

Further, according to the present invention, as compared with the nonvolatile semiconductor memory device having the floating gate, it is possible to write information at a low voltage, and the number of times of writing / erasing can be made equal to or more than that of the conventional structure. it can. Furthermore, in the present invention, the gate insulating film is formed of a multilayer film including a silicon nitride film and a tunnel oxide film, and the thickness of the tunnel oxide film is set to 2.6 to 3.0 nm. The disturb phenomenon can be reduced to a level without problems.

According to the present invention, the gate insulating layer is formed on the semiconductor layer formed on the SOI insulating layer, and the element isolation region is formed by the SOI technique. It is possible to prevent the cell area from increasing. Further, by adopting the SOI structure, when forming the contact hole for the bit line contact, even if the contact hole is slightly displaced from the semiconductor layer, the SOI insulating layer is formed below the semiconductor layer. Therefore, it is possible to prevent the bit line from being electrically connected to the semiconductor substrate.

In particular, in the second nonvolatile semiconductor memory device of the present invention, the gate electrode of the first layer can be processed with the minimum processing size without considering the misalignment of the resist film, and the memory cell can be processed. The area of can be further reduced. Further, since the gate insulating film for the second-layer gate electrode covers the sidewall, the breakdown voltage between the first-layer gate electrode and the second-layer gate electrode is improved.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A NAND type nonvolatile semiconductor memory device according to the present invention will be described below in detail with reference to the embodiments shown in the drawings. 1 is a cross-sectional view of a main part of a nonvolatile semiconductor memory device according to a first embodiment of the present invention, FIG. 2A is a plan view of a main part of a nonvolatile semiconductor memory device of the same embodiment, and FIG. 3A is a cross-sectional view of a main part taken along the line BB in FIG. 3A, and FIG. 3A is a cross-sectional view of the main part showing a reduction in the bit line direction of the nonvolatile semiconductor memory device of the same embodiment. 4A is a cross-sectional view of an essential part showing a conventional example with respect to FIG. 4A, FIG. 4A is a cross-sectional view of an essential part showing reduction in the word line direction of the nonvolatile semiconductor memory device of the same embodiment, and FIG. [Fig. 4] is a cross-sectional view of essential parts showing a conventional example with respect to Fig. 1A.

As shown in FIG. 2B, in the nonvolatile semiconductor memory device 30 according to this embodiment, an element isolation region (LOCOS) 33 is formed on a semiconductor substrate 32. The LOCOS 33 is composed of a silicon oxide film formed by a selective oxidation method using a silicon nitride film.

Semiconductor substrate 32 surrounded by LOCOS 33
A gate insulating film 34 is formed on the surface of the. On the gate insulating film 34, as shown in FIG. 1, first-layer gate electrodes 36 and second-layer gate electrodes 38 are alternately arranged close to each other in parallel. The first-layer gate electrode 36 and the second-layer gate electrode 38 are composed of a first-layer polysilicon layer and a second-layer polysilicon layer, respectively. The wiring structure of these gate electrodes 36 and 38 is similar to that of the CCD. These gate electrodes 36 and 38 are shown in FIG.
, The word lines S1 and S2 of the select transistors ST1 and ST2 and the cell transistors MT1 to MT8.
Of the word lines W1 to W8.

In the present embodiment, the gate insulating film 34 is composed of a thin film having a memory effect of accumulating charges and storing information, that is, a thin film layer having an electron trap function,
Specifically, it is composed of an ONO film (a multilayer film in which a silicon nitride film is sandwiched between silicon oxide films) including a silicon nitride film and a tunnel oxide film. That is, in this embodiment, M
The ONOS cell transistors MT1 to MT8 are arranged in a NAND type in an 8-bit configuration, and select transistors ST1 and ST2 are arranged on both sides thereof.

Gate electrodes 36 and 38 of the cell transistors MT1 to MT8 and select transistors ST1 and ST2.
Can be easily formed by inserting the second polysilicon layer between the first polysilicon layers. In the present embodiment, the cell transistors MT1 to MT8.
No impurity diffusion layer is formed between them, and the impurity diffusion layers 40 and 42 are formed only on one side of the select transistors ST1 and ST2. The impurity diffusion layer is composed of an n ⁺⁺ diffusion layer.

An interlayer insulating layer 43 is laminated on the gate electrodes 36 and 38. A contact hole 44 is formed in the interlayer insulating layer 43. The interlayer insulating layer 43 is composed of, for example, a silicon oxide layer. Bit lines 46 are formed in a predetermined pattern on the interlayer insulating layer 43, and the bit lines 46 are connected to one of the impurity diffusion layers 40 through the contact holes 44. Bit line 46 is made of, for example, aluminum metal.

In this embodiment, as shown in FIG.
It is not necessary to form the N ⁺⁺ diffusion layer 20 for the source / drain region between the cell transistors, as compared with the normal NAND type memory having the floating gate 6 (FIG. 3B). Because the N ⁺⁺ diffusion layer 20 for the source / drain region is simply a conductive layer for passing a signal current, the gate electrodes 36 and 38 are arranged close to each other on the gate insulating film 34 having a memory effect. NAND
This is because a mold circuit can be configured and a diffusion layer is unnecessary. Therefore, in the present invention, the memory cell can be reduced in the bit line direction by the amount of the diffusion layer removed.

Specifically, as shown in FIG. 3, the conventional structure requires 4.0 μm per 4 bits.
In the structure of the present embodiment, the size is 2.9 μm, and the size can be reduced by about 72.5% in the bit line direction. Note that FIG. 3 (B)
Among the members shown in FIG. 18, the same members as those shown in FIG. 18 are designated by the same reference numerals and the description thereof will be omitted.

Further, as shown in FIG. 4A, a NAND type memory having a normal floating gate 6 (see FIG.
Compared to (B)), it is possible to reduce the size in the word line direction by about 64%. Note that in FIG.
The same reference numerals are given to members common to the members shown in (B),
The description is omitted.

When the reduction in the bit line direction shown in FIG. 3 and the reduction in the word line direction shown in FIG. 4 are combined, about 46.4%.
The cell area will be reduced, and it will be possible to reduce the cell area by less than half that of the conventional structure. Next, a nonvolatile semiconductor memory device according to the second embodiment of the present invention will be described.

FIG. 5 is a cross-sectional view of a main part of a non-volatile semiconductor memory device according to a second embodiment of the present invention, and FIGS. 6 to 11 show a manufacturing process of the non-volatile semiconductor memory device shown in FIG.
12A is a cross-sectional view of the main part along the bit line direction, FIG. 12B is a cross-sectional view of the main part along the word line direction, and FIGS.
13A and 13B are cross-sectional views showing an essential part of a bit line contact having an SOI structure, FIGS. 13A and 13B are cross-sectional views showing an essential part of a bit line contact having a conventional structure, and FIG.
FIG. 6B is a sectional view of an essential part showing a problem caused by another conventional bit line contact.

As shown in FIG. 5, in the nonvolatile semiconductor memory device 50 according to this embodiment, a NAND memory is formed on a semiconductor substrate having a so-called SOI structure. That is, in this embodiment, the semiconductor layer 52 is formed on the SOI insulating layer 53 made of CVD silicon oxide or the like. A polysilicon layer 54 and a BP are provided below the insulating layer 53.
The SG layer 55 and the support substrate 56 are laminated. Such an SOI structure is manufactured by, for example, a bonded polishing SOI technique.

A first gate insulating film 58 and a second gate insulating film 59 are formed on the semiconductor layer 52, and the first layer gate electrode 60 and the second gate insulating film 59 are formed on the respective gate insulating films 58 and 59. The second-layer gate electrode 62 is laminated. The first and second gate insulating films 58 and 59 are composed of ONO films having a memory effect. The first and second layer gate electrodes 60 and 62 are composed of first and second polysilicon layers, respectively. The second-layer gate electrode 62 is formed so as to enter between the first-layer gate electrodes 60.

An interlayer insulating layer 64 is formed on these gate electrodes 60 and 62. The interlayer insulating layer 64 is
For example, it is made of silicon oxide. Interlayer insulating layer 64
A contact hole 66 is formed in the. Bit lines 68 are formed in a predetermined pattern on the interlayer insulating layer 64, and the semiconductor layer 5 is formed through the contact holes 66.
2 to the impurity diffusion layer 70 formed in
8 is connected. Bit line 68 is made of, for example, aluminum metal.

In this embodiment, the cell transistors MT1 to MT1.
Between MT8 (only MT1 to MT6 are shown in FIG. 5),
The impurity diffusion layer is not formed, and the select transistors ST1,
The impurity diffusion layer 70 is formed only on one side of ST2 (only the select transistor ST1 is shown in the figure). The impurity diffusion layer 70 is composed of an n ⁺⁺ diffusion layer.

Next, a method of manufacturing the nonvolatile semiconductor memory device 50 of this embodiment will be described. First, FIG.
As shown in (A) and (B), a semiconductor substrate having an SOI structure is obtained. The semiconductor substrate having the SOI structure is manufactured by, for example, the bonded polishing SOI method, and is formed on the support substrate 56 by B
PSG layer 55, polysilicon layer 54, SOI insulating layer 5
3 and the semiconductor layer 52 are laminated. Semiconductor layer 52
As shown in FIG. 6B, the elements are isolated by the element isolation insulating layer 57. The element isolation insulating layer 57 is formed integrally with the underlying insulating layer 53. The semiconductor layer 52 is
It is formed by selective polishing using the element isolation insulating layer 57 as a polishing stopper. Therefore, bird's beak does not occur in the element isolation insulating layer 57, which also contributes to the reduction of the memory cell.

Next, as shown in FIGS. 7 (A) and 7 (B),
The surface of the semiconductor layer 52 is washed, and the first gate insulating film 58 is formed on the surface. The first gate insulating film 58 is composed of an ONO film in this embodiment. The ONO film is 850
After forming a tunnel oxide film (SiO ₂ ) having a thickness of about 2 nm by dilution oxidation at ° C, a silicon nitride film (Si _{3 having a} thickness of about 4 nm at 750 ° C is formed by thermal nitriding or CVD.
N ₄ ) is formed, and after cleaning, a silicon oxide film (SiO ₂ ) having a thickness of about 3 nm is formed by the CVD method. Next, after cleaning the surface of the first gate insulating film 58, the first-layer gate electrode 60 is formed. The gate electrode 60 of the first layer is made of C of the first layer polysilicon of about 100 nm.
It is obtained by forming a film by the VD method and growing it at a temperature of 600 ° C. After cleaning, the first-layer polysilicon is doped with phosphorus. The doping of phosphorus is POCl
Heat treatment is performed at 800 ° C. for 60 minutes using ₃ gases.

After that, a resist film is formed on the first-layer polysilicon, photolithography is performed, and then RIE is performed to process the first-layer polysilicon into a predetermined pattern to obtain a first-layer gate electrode 60. Then, after removing the resist film, the surface is washed. Next, as shown in FIGS. 8A and 8B, the first gate insulating film 58 other than the portion below the first-layer gate electrode 60 is removed by etching. The upper silicon oxide layer and the lower tunnel oxide film of the first gate insulating film 58 are removed by an etching process using hydrofluoric acid, and the intermediate silicon nitride layer is removed by plasma etching.

Next, after cleaning the surface, as shown in FIGS.
As shown in FIG.
A gate insulating film 59 is formed. Second gate insulating film 59
Is composed of an ONO film in this embodiment. For the ONO film, a tunnel oxide film (SiO ₂ ) of about 2 nm is formed by diluted oxidation at 850 ° C., and then a silicon nitride film (Si ₃ N ₄ ) of about 4 nm is formed by thermal nitriding at 750 ° C. or a CVD method. Is formed, and after cleaning, a silicon oxide film (SiO ₂ ) having a thickness of about 3 nm is formed by the CVD method.

Next, after cleaning the surface of the second gate insulating film 59, the second-layer gate electrode 62 is formed. The second-layer gate electrode 62 is made of C-based second-layer polysilicon of about 100 nm.
It is obtained by forming a film by the VD method and growing it at a temperature of 600 ° C. Then, the second-layer polysilicon is doped with phosphorus. The doping of phosphorus is POCl
Heat treatment is performed at 800 ° C. for 60 minutes using ₃ gases.

After that, a resist film is formed on the second-layer polysilicon, photolithography is performed, and then RIE is performed to process the second-layer polysilicon into a predetermined pattern to obtain a second-layer gate electrode 62. Then, after removing the resist film, the surface is washed. Next, as shown in FIGS. 10A and 10B, an interlayer insulating layer 64 is formed. Interlayer insulating layer 64
Is composed of a silicon oxide layer obtained by a CVD method at 800 ° C. for 10 minutes. Next, after cleaning the surface, a resist film is formed on the interlayer insulating layer 64, and after the photolithography, the interlayer insulating layer 64 is etched by RIE or the like, as shown in FIGS. Then, a contact hole 66 for a bit line contact is formed.

After that, the resist film is removed, and an aluminum metal layer to be the bit line 68 is formed on the interlayer insulating layer 64 by sputtering. At that time, the aluminum wiring layer is embedded in the contact hole 66. The film thickness of the aluminum wiring layer serving as bit line 68 is, for example, 0.5 μm. Next, a resist film is formed on the aluminum wiring layer, and after photolithography, the aluminum wiring layer is subjected to RIE etching and processed into a bit line pattern to obtain a bit line 68.

Next, after removing the resist film and cleaning the surface, sintering treatment is performed at 400 ° C. for 60 minutes, and the cell transistors MT1 to MT8 and the selection transistor ST are formed.
A non-volatile semiconductor memory device having ST1 and ST2 is obtained.
According to the nonvolatile semiconductor memory device 50 of the present embodiment, it has the same operation as the embodiment shown in FIGS.
Since the NAND type memory cell is formed on the semiconductor substrate having the I structure, the design rule related to the bit contact can be reduced as shown below.

That is, as shown in FIGS. 12A and 12B, after forming a resist film 72 on the interlayer insulating layer 64 and forming a bit contact opening 74 in the resist film 72, A contact hole 66 is formed in the interlayer insulating layer 64 by RIE. When the contact hole 66 is formed, a groove 76 may be formed in the inter-element isolation insulating layer 57 and the insulating layer 53 below it due to mask misalignment with the impurity diffusion layer 70 formed in the semiconductor layer. In this embodiment, even if the groove 76 is formed, the contact hole 6
The bit line 68 entering 6 is not electrically connected to any portion other than the impurity diffusion layer 70.

On the other hand, as shown in FIGS. 13A and 13B, in the memory cell using the LOCOS 15 having the conventional structure, the resist film 78 is formed on the interlayer insulating layer 12 to obtain the bit line contact. When the film is formed, the opening 80 is formed by photolithography, and the contact hole 14a is formed in the interlayer insulating layer 12, there are the following problems. That is, as shown in FIG.
Due to the misalignment between the contact hole 14a and the impurity diffusion layer 22a, a groove 82 is formed on the surface of the semiconductor substrate 2 and the bit line 16 is electrically connected to the semiconductor substrate 2. In FIG. 13, reference numeral 77 is a channel stopper region.

As shown in FIGS. 14A and 14B, the trench type element isolation region 8 is formed on the surface of the semiconductor substrate 2.
Even when No. 4 is formed, it has the same problem as the conventional example shown in FIG. In this conventional example, a resist film 88 is formed on the interlayer insulating layer 87, an opening 89 is formed by a photolithography method, and the resist film 88 is used as R.
A contact hole 89 is formed in the interlayer insulating layer 87 by IE. At that time, a mask misalignment may occur, which causes the trench type element isolation region 84.
A groove 90 is formed in the groove. This groove 90 allows the bit line 1
6 is electrically connected to the surface of the semiconductor substrate 2 below the impurity diffusion layer 86.

As shown in FIGS. 13 and 14, in the conventional structure, there is a possibility that the bit line 16 and the semiconductor substrate 2 become conductive due to the misalignment of the mask, and it is necessary to secure a large design margin for the contact. It was On the other hand, in the present embodiment, as shown in FIG. 12, even if the mask 76 is misaligned and the groove 76 is formed, the bit line 68 entering the contact hole 66 has the impurity diffusion layer 70.
There is no conduction with other parts. Therefore, SOI
In this embodiment adopting the structure, the design rule for the bit line contact can be made small, which also contributes to the reduction of the cell area.

Next, a third embodiment of the present invention will be described. 15A is a cross-sectional view of a main part of a nonvolatile semiconductor memory device according to a third embodiment of the present invention, FIG. 15B is a cross-sectional view of the main part of a comparative example of FIG. 15A, and FIG. ~
15E is a sectional view of a key portion showing the method for manufacturing the nonvolatile semiconductor memory device shown in FIG.

As shown in FIG. 15A, the third aspect of the present invention is provided.
The non-volatile semiconductor memory device 92 according to the second embodiment relates to the improvements of the first and second embodiments. As shown in FIG. 15A, the nonvolatile semiconductor memory device 92 of this embodiment is
A first-layer gate electrode 98 is stacked on the surface of the semiconductor substrate 94 via a first gate insulating film 96, and a second-layer gate electrode 98 is formed between the first-layer gate electrodes 98 via a second gate insulating film 101. The gate electrode 102 is laminated. Moreover, in this embodiment, the sidewall 100 is formed on the side portion of the first-layer gate electrode 98.

The semiconductor substrate 94 is made of, for example, a P-type silicon substrate, but may be a semiconductor layer having an SOI structure. First gate insulating film 96 and second gate insulating film 1
01 is formed of, for example, an ONO film having a memory function. The first-layer gate electrode 98 and the second-layer gate electrode are composed of first-layer polysilicon and second-layer polysilicon, respectively. The sidewall 100 is formed of a conductive layer such as a polysilicon layer, but may be formed of an insulating layer such as silicon oxide.

Next, a method of manufacturing the nonvolatile semiconductor memory device 92 of this embodiment will be described. As shown in FIG. 16A, a first gate electrode 96 composed of an ONO film is formed on the surface of the semiconductor substrate 94 in the same manner as in the first and second embodiments. On top of that, the first layer polysilicon 10
4 is deposited by the CVD method. The first layer polysilicon 104 is doped with phosphorus in order to improve conductivity.

Next, on the first layer polysilicon 104,
A resist film 106 is formed. This resist film 106
Are processed so as to have a minimum line width M and a minimum space L of photolithography. Using this resist film 106, the first-layer polysilicon 104 is etched by RIE to form a first-layer gate electrode 98 as shown in FIG. 16B. At this time, in order to protect the first gate insulating film below the sidewalls, the first layer polysilicon 104 located between the first layer gate electrodes 98 is left to have a thickness of about 50 nm to form the protective layer 104a. To do. Then, the resist film 106 is removed.

Next, as shown in FIG. 16C, a sidewall forming layer 108 is formed on the first-layer gate electrode 98 and the protective layer 104a. The sidewall forming layer 108 is preferably made of polysilicon from the viewpoint of ease of manufacturing. In addition, the gate electrode 98 of the first layer
From the viewpoint of enhancing the insulating property between the gate electrode 102 and the second layer, the sidewall formation layer 108 is preferably made of an insulating material such as silicon oxide. When the sidewall forming layer 108 is composed of polysilicon deposited by the CVD method, phosphorus is doped into this polysilicon.

For the purpose of improving the contact property between the first-layer gate electrode 98 and the sidewall forming layer 108, hydrofluoric acid treatment is performed to remove the natural oxide film before depositing the sidewall forming layer 108. But the first gate electrode 9
Since 6 is covered with the protective layer 104a, it is not damaged.

Next, as shown in FIG. 16D, RIE
Then, the entire surface of the sidewall forming layer 108 is etched back by using, to form the sidewall 100 on the side portion of the first gate electrode 98. At this time, the protective layer 104a other than the lower part of the sidewall 100 is also removed by etching. Also,
When forming the sidewall 100, the width β of the sidewall 100 is set to be equal to or larger than the mask misalignment margin α. After that, the first gate insulating film 96 other than the portion to be the memory cell transistor on the lower layer side is removed by etching.

After that, as shown in FIG. 16E, the first
A second gate insulating film 101 is formed on the entire surface of the semiconductor substrate 94 on which the gate electrode 98 and the sidewall 100 are formed. The second gate insulating film 101 is composed of an ONO film. After that, by depositing the second-layer polysilicon and etching the second-layer polysilicon, the second-layer gate electrode 102 can be formed between the first-layer gate electrodes 98.

In this embodiment, the sidewall 100 is formed on the side portion of the gate electrode 98 of the first layer, so that the following action is obtained. First, by smoothing the shoulder portion of the first gate electrode 98 by the sidewall 100, the breakdown voltage with respect to the gate electrode 102 of the second layer laminated on the sidewall 100 via the second gate insulating film 101 is improved. Can be made.

Second, as shown in FIG. 15A, the first
If the processing width M of the gate electrode 98 of the layer can be set to the minimum line width and the distance between the gate electrodes 98 of the first layer excluding the sidewall 100 is L, the size of the memory cell per bit is ( L + M) / 2, and the size of the memory cell can be reduced.

On the other hand, as shown in FIG.
In the non-volatile semiconductor memory device of the first and second embodiments, the width of the gate electrode 60 of the first layer is the minimum line width M + 2 ×
The alignment margin α had to be set. If the space between the gate electrodes 60 of the first layer and the gate electrode 62 of the second layer is the minimum space L, the cell size per bit is ((M + 2 × α) + L) / 2 = α + (M +
L) / 2.

The width of the gate electrode of the first layer had to be M + 2 × α. The reason for this is that if there is no margin of 2 × α, the gate electrode 6 of the second layer will be misaligned due to mask misalignment.
2 is likely to be formed without overlapping with the gate electrode 60 of the first layer. In addition,
In FIG. 15B, reference numeral 52 is a semiconductor layer and reference numeral 58 is a first layer.
A gate insulating film, reference numeral 59 indicates a second gate insulating film.

On the other hand, in this embodiment, FIG.
As shown in FIG. 6, the width of the gate electrode 98 of the first layer can be processed with the minimum line width M, and the width β (β ≧ α) of the sidewall 100 is used as a substitute for the misalignment margin of the mask. So there is no problem. Moreover, in this embodiment, the cell size per bit is as described above.
Since (M + L) / 2, the cell size can be reduced as compared with the comparative example shown in FIG.

How much the cell size can be reduced in the case of designing with the 0.35 μm rule will be examined. M
= 0.35 μm, L = 0.4 μm, and α = 0.15 μm, the cell size per bit in the comparative example shown in FIG. 15B is (0.35 + 0.4) /2+0.1.
5 = 0.525 μm.

On the other hand, in the embodiment shown in FIG. 15A, the cell size per bit is (0.35 + 0.
4) /2=0.375 μm. Therefore, in this example, compared with the comparative example, (0.375 / 0.525) ×
Reduction of 100 = 71.4% is possible.

In the above 0.35 μm rule, the first
Channel length C1 due to the gate electrode 98 of the layer (see FIG.
(See (E)) is 2 × 0.15 + 0.35 = 0.65μ
m, and the channel length C2 due to the second-layer gate electrode
(See FIG. 16E) is 0.4-2 × 0.15 = 0.
It becomes 10 μm, and the channel length varies. However, in this calculation, the film thicknesses of the gate insulating films 96 and 101 are ignored.

In order to bring the characteristics of these two cell transistors close to each other, after the step shown in FIG. 16A, the resist 106 is isotropically etched by oxygen plasma to thin the resist film 106 (resist ashing). ), The electrode width of the first-layer electrode 98 obtained by etching the first-layer polysilicon 104 may be reduced to the minimum line width M or less.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the present invention. For example, although the ONO film is used as the gate insulating film and the cell transistor having the MONOS structure is used in the above-described embodiment, the gate insulating film may include a thin film layer having a memory function, such as a silicon nitride film and a silicon nitride film. It may be formed of a laminated film of a film and a silicon oxide film, a laminated film of an aluminum oxide and a silicon oxide film, or the like. That is, a cell transistor having an MNS, MNOS, or MAOS structure can also be used.

[0069]

As described above, according to the present invention, it is not necessary to form a diffusion layer for source / drain regions between cell transistors, as compared with a normal NAND type memory having a floating gate. . Therefore, in the present invention, the memory cell can be reduced by the amount of the diffusion layer removed.

Arranging the gate electrodes close to each other can be easily realized by arranging the gate electrodes of the second layer so as to overlap each other between the gate electrodes of the first layer. Further, in the present invention, since the structure does not have a floating gate, the floating gate and the element isolation region do not overlap each other, and the cell area can be reduced also in this respect.

Further, according to the present invention, as compared with a nonvolatile semiconductor memory device having a floating gate, information can be written at a low voltage, and the number of times of writing / erasing can be made equal to or more than that of the conventional structure. it can. Furthermore, in the present invention, the gate insulating film is formed of a multilayer film including a silicon nitride film and a tunnel oxide film, and the thickness of the tunnel oxide film is set to 2.6 to 3.0 nm. The disturb phenomenon can be reduced to a level without problems. In the present invention, the gate insulating layer is formed on the semiconductor layer formed on the SOI insulating layer, and the element isolation region is formed by the SOI technique, so that the bird's beak is eliminated and the cell area due to the bird's beak is reduced. The increase can be prevented.

Further, by using the SOI structure, when forming a contact hole for a bit line contact,
Even if the contact hole is slightly displaced from the semiconductor layer, since the SOI insulating layer is formed in the lower layer of the semiconductor layer, it is possible to prevent the bit line from being electrically connected to the semiconductor substrate. it can.

Particularly, in the nonvolatile semiconductor memory device of the present invention in which the sidewall is formed on the side portion of the gate electrode of the first layer, the gate electrode of the first layer is minimized without considering the misalignment of the resist film. It becomes possible to process with the processing size, and the area of the memory cell can be further reduced. Further, since the gate insulating film for the second-layer gate electrode covers the sidewall, the breakdown voltage between the first-layer gate electrode and the second-layer gate electrode is improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

2A is a plan view of relevant parts of the nonvolatile semiconductor memory device of the same embodiment, and FIG. 2B is a cross-sectional view of relevant parts taken along line BB of FIG. 2A.

FIG. 3A is a cross-sectional view of essential parts showing reduction in the bit line direction of the nonvolatile semiconductor memory device of the same embodiment, FIG.
(B) is a cross-sectional view of essential parts showing a conventional example with respect to (A) of the same figure.

FIG. 4A is a cross-sectional view of essential parts showing reduction in size in the word line direction of the nonvolatile semiconductor memory device of the same embodiment, FIG.
(B) is a cross-sectional view of essential parts showing a conventional example with respect to (A) of the same figure.

FIG. 5 is a cross-sectional view of essential parts of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

6A and 6B show a manufacturing process of the nonvolatile semiconductor memory device shown in FIG. 5, FIG. 6A is a sectional view of a main part taken along the bit line direction, and FIG. 6B is a sectional view of the main part taken along the word line direction. It is a figure.

7A and 7B show a manufacturing process of the nonvolatile semiconductor memory device shown in FIG. 5, FIG. 7A is a sectional view of a main part taken along the bit line direction, and FIG. 7B is a sectional view of the main part taken along the word line direction. It is a figure.

8A and 8B show a manufacturing process of the nonvolatile semiconductor memory device shown in FIG. 5, where FIG. 8A is a sectional view of a main part taken along the bit line direction, and FIG. 8B is a sectional view of the main part taken along the word line direction. It is a figure.

9A and 9B show a manufacturing process of the nonvolatile semiconductor memory device shown in FIG. 5, FIG. 9A is a sectional view of a main part taken along the bit line direction, and FIG. 9B is a sectional view of the main part taken along the word line direction. It is a figure.

10A and 10B show a manufacturing process of the nonvolatile semiconductor memory device shown in FIG. 5, FIG. 10A is a sectional view of a main part taken along the bit line direction, and FIG. 10B is a sectional view of the main part taken along the word line direction. It is a figure.

11 shows a manufacturing process of the nonvolatile semiconductor memory device shown in FIG. 5, (A) is a cross-sectional view of a main part along the bit line direction, and (B) is a cross-sectional view of the main part along the word line direction. It is a figure.

12A and 12B are cross-sectional views showing a main part of a bit line contact having an SOI structure.

13 (A) and 13 (B) are cross-sectional views of relevant parts showing problems caused by a bit line contact having a conventional structure.

14 (A) and 14 (B) are cross-sectional views of relevant parts showing problems caused by other conventional bit line contacts.

15A is a cross-sectional view of a main part of a nonvolatile semiconductor memory device according to a third embodiment of the present invention, and FIG. 15B is a cross-sectional view of a main part showing a comparative example of FIG. 15A. .

16A to 16E are cross-sectional views of essential parts showing a method for manufacturing the nonvolatile semiconductor memory device shown in FIG. 15A.

17A is a plan view of a NOR-type nonvolatile semiconductor memory device according to a conventional example, and FIG. 17B is a cross-sectional view of essential parts taken along the line BB of FIG. 17A.

18A is a cross-sectional view of a main part of a NAND-type nonvolatile semiconductor memory device according to a conventional example in the bit line direction, and FIG. 18B is a cross-sectional view of the main part taken along the line BB of FIG. 18A. Is.

19A is a circuit diagram showing an equivalent circuit of a NAND memory cell, and FIG. 19B is a plan view of the NAND memory cell.

[Explanation of symbols]

 30 ... Nonvolatile semiconductor memory device 32 ... Semiconductor substrate 33 ... LOCOS 34 ... Gate insulating film 36 ... First layer gate electrode 38 ... Second layer gate electrode 40, 42 ... Impurity diffusion layer 43 ... Interlayer insulating layer 44 ... Contact Hole 46 ... Bit line 52 ... Semiconductor layer 53 ... Insulating layer 57 ... Inter-element isolation insulating layer 58 ... First gate insulating layer 59 ... Second gate insulating layer 60 ... First layer gate electrode 62 ... Second layer gate electrode 64 ... Interlayer insulating layer 66 ... Contact hole 68 ... Bit line 92 ... Nonvolatile semiconductor memory device 94 ... Semiconductor substrate 96 ... First gate insulating film 98 ... First layer gate electrode 100 ... Side wall 101 ... Second gate insulating film 102 ... Second-layer gate electrode

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] November 12, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

[0008]

However, even the NAND type memory has some structural problems as described below. First, as shown in FIGS. 18 (B) and 19 (B), the floating gate 6 is formed on the LOCOS 15 so as to extend by the overlap length l in order to increase the coupling ratio regarding capacitance. ing. That is, the cell area is increased in the word line (control gate 10) direction by the overlap length l.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

By arranging the gate electrode of the second layer so as to overlap between the gate electrodes of the first layer with the insulating film interposed therebetween, the gate electrode of the first layer and the gate electrode of the second layer are close to each other. It is preferable that they are alternately arranged in parallel. It is necessary that the gate insulating film has a thin film layer having an electron trap function . This thin film layer is preferably a silicon nitride film or a multilayer film including a silicon nitride film.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0015

[Correction method] Change

[Correction content]

It is preferable that the gate insulating layer is formed on the semiconductor layer formed on the SOI insulating layer, and the element isolation region is formed by the SOI technique. A second non-volatile semiconductor memory device according to another aspect of the present invention has a gate electrode and a gate insulating film arranged under the gate electrode, and stores charges in the gate insulating film to store information. And a plurality of gate electrodes adjacent to each other in parallel on the gate insulating film, and between the gate electrodes of the first layer so as to have a NAND type memory cell structure. the gate electrode of the second layer
Overlapped via the insulating film, a sidewall is formed on the side portion of the first-layer gate electrode.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction content]

Placing the gate electrodes close to each other means that the gate electrode of the second layer is provided with an insulating film between the gate electrodes of the first layer.
By arranging overlap through, it can easily be realized. Further, in the present invention, since the structure does not have a floating gate, the floating gate and the element isolation region do not overlap each other, and the cell area can be reduced also in this respect.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

Further, according to the present invention, as compared with the nonvolatile semiconductor memory device having the floating gate, it is possible to write information at a low voltage, and the number of times of writing / erasing can be made equal to or more than that of the conventional structure. it can. Furthermore, in the present invention, the gate insulating film is formed of a multi-layered film including a silicon nitride film and a tunnel oxide film, and the tunnel oxide film has a thickness of 2.0 to 8.0 nm, so that information can be read out. The disturb phenomenon can be reduced to a level without problems.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0039

[Correction method] Change

[Correction content]

Next, as shown in FIGS. 7 (A) and 7 (B),
The surface of the semiconductor layer 52 is washed, and the first gate insulating film 58 is formed on the surface. The first gate insulating film 58 is composed of an ONO film in this embodiment. The ONO film is 850
° After the formation of about 2nm about the tunnel oxide film (SiO ₂₎ by dilution oxidation and C, formed approximately 4nm about silicon nitride film (Si ₃ N ₄₎ by C VD method 750 ° C, washed , About 3 nm silicon oxide film (SiO
₂ ) is obtained by forming a film by oxidation or a CVD method. This nitride film has a thick tunnel oxide film.
It can also be obtained by thermal nitriding. next,
After cleaning the surface of the first gate insulating film 58, a first-layer gate electrode 60 is formed. The gate electrode 60 of the first layer has about 1
It is obtained by depositing a first layer polysilicon of 00 nm by a CVD method and growing it at a temperature of 600 ° C. After cleaning, the first-layer polysilicon is doped with phosphorus. The phosphorus doping is performed by heat treatment using POCl ₃ gas at 800 ° C. for 60 minutes.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0040

[Correction method] Change

[Correction content]

After that, a resist film is formed on the first-layer polysilicon, photolithography is performed, and then RIE is performed to process the first-layer polysilicon into a predetermined pattern to obtain a first-layer gate electrode 60. Then, after removing the resist film, the surface is washed. Next, as shown in FIGS. 8A and 8B, the first gate insulating film 58 other than the portion below the first-layer gate electrode 60 is removed by etching. The upper silicon oxide layer and the lower tunnel oxide film of the first gate insulating film 58 are removed by an etching process using hydrofluoric acid, and the intermediate silicon nitride layer is subjected to plasma etching or
Remove by RIE .

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0041

[Correction method] Change

[Correction content]

Next, after cleaning the surface, as shown in FIGS.
As shown in FIG.
A gate insulating film 59 is formed. Second gate insulating film 59
Is composed of an ONO film in this embodiment. ONO film, after forming the approximately 2nm about the tunnel oxide film (SiO ₂₎ by dilution oxidation of 850 ° C, of 750 ° C C V
About 4 nm silicon nitride film (Si ₃ N
₄ ) is formed, and after cleaning, a silicon oxide film (SiO ₂ ) of about 3 nm is formed by oxidation or CVD method. In addition, the nitride film is thicker than the tunnel oxide film.
It can also be obtained by forming it and then thermally nitriding it.
It

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0053

[Correction method] Change

[Correction content]

Next, a method of manufacturing the nonvolatile semiconductor memory device 92 of this embodiment will be described. As shown in FIG. 16 (A), the surface of the semiconductor substrate 94, the first, in the same manner as in the second embodiment, the first gate insulation composed of an ONO film
The border film 96 is formed. On top of that, the first layer polysilicon 1
04 is deposited by the CVD method. First layer polysilicon 104
In order to improve conductivity, it is doped with phosphorus.

[Procedure Amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0056

[Correction method] Change

[Correction content]

For the purpose of improving the contact property between the first-layer gate electrode 98 and the sidewall forming layer 108, hydrofluoric acid treatment is performed to remove the natural oxide film before depositing the sidewall forming layer 108. However, since the first gate insulating film 96 is covered with the protective layer 104a, it is not damaged.

[Procedure Amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0071

[Correction method] Change

[Correction content]

Further, according to the present invention, as compared with a nonvolatile semiconductor memory device having a floating gate, information can be written at a low voltage, and the number of times of writing / erasing can be made equal to or more than that of the conventional structure. it can. Furthermore, in the present invention, the gate insulating film is formed of a multi-layered film including a silicon nitride film and a tunnel oxide film, and the tunnel oxide film has a thickness of 2.0 to 8.0 nm, so that information can be read out. The disturb phenomenon can be reduced to a level without problems. In the present invention, the gate insulating layer is formed on the semiconductor layer formed on the SOI insulating layer, and the element isolation region is formed by the SOI technique, so that the bird's beak is eliminated and the cell area due to the bird's beak is reduced. The increase can be prevented.

[Procedure Amendment 13]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

[Fig. 2]

[Procedure Amendment 14]

[Document name to be corrected] Drawing

[Correction target item name] Figure 15

[Correction method] Change

[Correction content]

FIG. 15

[Procedure Amendment 15]

[Document name to be corrected] Drawing

[Correction target item name] Fig. 16

[Correction method] Change

[Correction content]

FIG. 16

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical indication H01L 21/8247 29/788 29/792 H01L 29/78 371

Claims (9)

[Claims] 1. A non-volatile semiconductor memory device having a gate electrode and a gate insulating film disposed below the gate electrode, wherein the nonvolatile semiconductor memory device stores electric charge in the gate insulating film to store information. Having a NAND-type memory cell structure in which the gate electrodes of the above are arranged in parallel in close proximity to each other on the gate insulating film.
D-type non-volatile semiconductor memory device. 2. The gate electrode of the second layer is arranged so as to overlap between the gate electrodes of the first layer so that the gate electrode of the first layer and the gate electrode of the second layer are alternately arranged close to each other. The NAND-type non-volatile semiconductor memory device according to claim 1, which is arranged in parallel. 3. The NA according to claim 1, wherein the gate insulating film has a thin film layer having an electron trap function.
ND type non-volatile semiconductor memory device. 4. The NAND-type nonvolatile semiconductor memory device according to claim 3, wherein the thin film layer is a silicon nitride film or a multilayer film including a silicon nitride film and a tunnel oxide film. 5. The gate insulating layer is formed on a semiconductor layer formed on an SOI insulating layer, and the element isolation region is formed by an SOI technique.
5. The NAND type nonvolatile semiconductor device according to any one of 1. 6. A non-volatile semiconductor memory device having a gate electrode and a gate insulating film disposed below the gate electrode, wherein charges are stored in the gate insulating film to store information. -Type memory cell structure, a plurality of gate electrodes are closely arranged in parallel on the gate insulating film, and
A NAND-type non-volatile semiconductor memory in which a gate electrode of a second layer is arranged so as to overlap between gate electrodes of a first layer, and a sidewall is formed on a side portion of the gate electrode of the first layer. apparatus. 7. The NAND-type non-volatile semiconductor memory device according to claim 6, wherein the sidewall is made of polysilicon. 8. A step of forming, on a semiconductor substrate, a first gate insulating film in which electric charges are accumulated and in which information can be written, and a step of forming a first conductive layer on the first gate insulating film. A resist film having a predetermined pattern is formed on the surface of the first conductive layer, and the first conductive layer is processed by etching using the resist film, and the gate electrodes of the first layer are formed at predetermined intervals. And the step of forming a sidewall on the side portion of the first-layer gate electrode, and from the top of the first-layer gate electrode where the sidewall is formed, charges are accumulated to write information. A step of forming a possible second gate insulating film, and forming a second layer gate electrode in the gap between the first layer gate electrodes on the second gate insulating film, and forming the first layer gate The electrode and the gate electrode of the second layer are connected to N As the ND-type memory cell, method of manufacturing the NAND type nonvolatile semiconductor memory device having a placing in parallel alternately adjacent. 9. The gate electrode of the first layer is formed so that the channel length formed by the gate electrode of the first layer and the channel length formed by the gate electrode of the second layer are substantially the same. 9. The N according to claim 8, wherein the pattern of the resist film for patterning is narrowed by plasma treatment.
AND-type nonvolatile semiconductor memory device manufacturing method.