JP3097607B2 - Split gate flash memory cell and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a method of manufacturing a flash memory cell having a split gate structure.

[0002]

2. Description of the Related Art As a nonvolatile semiconductor memory device, an EPROM and a flash memory capable of erasing and writing information are known. However, these nonvolatile semiconductor memory devices are conventionally provided with a gate oxide film and a silicon oxide film on a silicon substrate surface. Forming a floating gate electrode layer for charge storage, an inter-electrode insulating film, and a control gate electrode layer serving as a word line of each memory cell,
After processing into a gate electrode having a laminated structure, a source / drain diffusion layer and a channel region are formed, and thereafter, a metal wiring to each electrode is formed.

However, 1994 IEDM Tech. Diges
As shown in t pp.847-850, a flash memory cell having such a stacked gate of a type in which a floating gate and a control gate are stacked has a problem of excessive erasing when erasing data. In a flash memory, data is generally erased by an operation of simultaneously extracting electrons from a floating gate in thousands or more memory cells. Therefore, the amount of electrons extracted from the floating gate varies in each memory cell, and as a result, the threshold voltage of the memory cell varies in a width of about 1 V. Generally, data is erased from a memory cell so that the threshold voltage becomes low. If the threshold voltage varies, the threshold voltage becomes 0 V or less.
That is, memory cells exhibiting depletion type transistor characteristics are also generated. When a memory cell having depletion-type transistor characteristics is present, a current always flows through the bit line connected to this memory cell even when the memory cell is not read, and the memory cell connected to this bit line Data cannot be read from other memory cells.

As a method for solving such a situation, a split type memory cell has been proposed. Unlike a memory cell having a general stacked gate electrode structure, a split type memory cell has a structure in which a floating gate electrode covers only a part of a channel region and a control gate electrode covers another part of the channel region. doing. In the case of a split type memory cell, even if electrons in the floating gate electrode are extracted too much after data is erased and the threshold voltage immediately below the floating gate electrode becomes 0 V or less, the threshold voltage immediately below the control gate electrode is set by the designer. Does not fluctuate from the designed threshold voltage, so that the characteristic of the split type memory cell obtained by adding both does not become the depletion type.

As a method of manufacturing the split type memory cell, a single-layer silicon oxide film is generally used as an interlayer insulating film for insulating and separating a control gate electrode and a floating gate electrode. On the other hand, in a recent flash memory cell, a silicon oxide film / silicon nitride film / silicon oxide film (ONO film) is required to realize a thin film interlayer insulating film for further enhancing the capacitive coupling between the control gate and the floating gate.
The method using a laminated film made of

When this ONO film is used for a split gate type memory cell, the following method as shown in FIG. 3 can be considered as a memory cell prototype process. First, on a silicon substrate 31 on which an insulating film for element isolation has been formed, the source
A drain diffusion layer 37 is formed. Next, a floating gate insulating film 32 (thickness: 100 °) is formed by thermal oxidation, and a polysilicon thin film 33 for a floating gate electrode (thickness: 150 °) is formed thereon.
0 °) and an interlayer insulating film (ONO film, silicon oxide film-equivalent thickness of 120 °) composed of a silicon oxide film 34 / silicon nitride film 35 / silicon oxide film 36 are sequentially formed by a CVD method. And the polysilicon for the floating gate electrode is processed into a stripe pattern using a dry etching technique of silicon and polysilicon (FIG. 3).
(A)).

Thereafter, as shown in FIG. 3B, a sidewall oxide film 38 and a control gate insulating film 39 of a control gate portion are formed on the polysilicon sidewall of the floating gate electrode by thermal oxidation to a thickness of 1 nm.
Formed at 00 °.

After that, a control gate electrode polysilicon film 40 (thickness 1500 °) is deposited and deposited as shown in FIG. 3 (c), and then the control gate electrode polysilicon film 40 is striped in the word line direction. The film and the polysilicon thin film 33 for the floating gate electrode are processed using photolithography technology and dry etching technology. Next, an insulating film is formed on the entire surface of the substrate 31 so as to cover these patterns, and contact holes to each electrode of the memory cell are formed.

[0009]

However, as shown in FIG. 3 (c), thermal oxidation of the side wall oxide film 38 on the side surface of the floating gate electrode at the contact portion 41 with the ONO film is suppressed, and the thickness thereof is reduced. Becomes thinner. When a positive voltage is applied to the control gate at the time of writing data to the memory cell, an electric field concentrates on the convex portion of the floating gate electrode, that is, the contact portion 41, so that accumulated electrons from the floating gate electrode to the control gate electrode are accumulated. It leaks out and deteriorates the data writing characteristics and the data holding characteristics.

As a method for avoiding this problem, Japanese Patent Laid-Open No.
In Japanese Patent Application Laid-Open No. 3-291474, after forming a photoresist pattern so that only the convex portion is exposed, an impurity is implanted only into the convex region, and the impurity in the floating gate polysilicon pattern is increased by accelerated oxidation by the impurity. A method of thickening an oxide film has been reported. However, when this method is used, impurities are implanted into the channel surface of the control gate section, and as a result, the threshold voltage of the control gate section fluctuates, and high-concentration impurities are implanted into the floating gate polysilicon pattern. As a result, there is a problem that excessive erasure of data occurs due to the presence of the high concentration impurity.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has been made in view of the followings. An object is to improve data writing characteristics and data holding characteristics by suppressing electron outflow.

[0012]

Means for Solving the Problems The present invention provides a floating gate insulating film on a device region of a semiconductor substrate, a floating gate electrode formed of a polysilicon film, and an interlayer insulating film provided on the floating gate electrode. When the floating and the sidewall silicon oxide film covering the side surfaces of the gate electrode, in the split gate type flash memory cell control gate electrode which is insulated from the floating gate electrode is provided by the interlayer insulating film and the sidewall silicon oxide film, the interlayer insulating The film is a silicon oxide film,
Product consisting of three layers of silicon nitride film and silicon oxide film
A layer film of polysilicon on the upper surface of the floating gate electrode.
At least the part near the side is gradually thicker toward the side
Is replaced by an oxide film,
The silicon oxide film is provided by a CVD silicon oxide film, and relates to a split gate type flash memory cell.

In the present invention, a thick insulating film exists near the interlayer insulating film on the side surface of the floating gate electrode. Therefore, when data is written to the memory cell, the electric field concentration at the contact portion 41 shown in FIG. 3C can be alleviated, and the outflow of accumulated electrons from the floating gate electrode to the control gate electrode can be suppressed. Data writing characteristics and data holding characteristics can be improved.

[0014]

In this case, a step of forming a floating gate insulating film on the element region of the semiconductor substrate, a step of forming a floating gate electrode polysilicon film on the floating gate insulating film, Forming an interlayer insulating film thereon, forming a silicon nitride film for a mask on the interlayer insulating film, processing the silicon nitride film for a mask and the interlayer insulating film into a predetermined electrode pattern, LOCOS-oxidizing the polysilicon film for the floating gate electrode using the silicon nitride film for a mask processed into a predetermined electrode pattern as a mask, and performing etching using the silicon nitride film for the mask as a mask, Forming the oxide film and the polysilicon film for the floating gate electrode into an electrode shape; Forming a film, subsequently removing the silicon nitride film for the mask, and depositing a polysilicon thin film for the control gate electrode, and forming the same into a control gate electrode shape by photolithography and dry etching. A split gate flash memory cell can be manufactured by a manufacturing method.

[0016]

In this case, a step of forming a floating gate insulating film on the element region of the semiconductor substrate, a step of forming a floating gate electrode polysilicon film on the floating gate insulating film, Forming an interlayer insulating film thereon, forming a silicon nitride film for a mask on the interlayer insulating film, processing the silicon nitride film for a mask and the interlayer insulating film into a predetermined electrode pattern, LOCOS-oxidizing the polysilicon film for the floating gate electrode using the silicon nitride film for a mask processed into a predetermined electrode pattern as a mask, and performing etching using the silicon nitride film for the mask as a mask, Forming an oxide film and a polysilicon film for a floating gate electrode into an electrode shape, and forming a CVD silicon oxide film on the entire surface of the electrode structure thus formed. After that, the silicon oxide film is etched back by anisotropic etching to form a silicon oxide film on the side wall of the floating gate electrode, subsequently, the silicon nitride film for the mask is removed, and the polysilicon for the control gate electrode is removed. A split gate flash memory cell can be manufactured by a manufacturing method including a step of depositing a silicon thin film and forming the silicon thin film into a control gate electrode shape by photolithography and dry etching.

In such a manufacturing method, when the polysilicon film is subjected to LOCOS oxidation, the LOCOS oxidation also proceeds to the polysilicon film below the interlayer insulating film serving as a mask, so that the LOCOS film has a bird's beak shape (bird's beak). ), An oxide film that gradually becomes thicker toward the side surface can be easily formed in the vicinity of the side surface of the polysilicon on the upper surface of the floating gate electrode.

Preferably, the interlayer insulating film is thinned so that the capacitive coupling between the control gate and the floating gate is as large as possible. Such thinning is performed by using a silicon oxide film, a silicon nitride film and a silicon oxide film. This can be achieved by a three-layered film.

In the case where such an interlayer insulating film including a silicon nitride film is used, among the above-described manufacturing methods,
It is particularly preferable to form the side wall silicon oxide film so as to cover the side surface of the silicon nitride film in the interlayer insulating film by using a method of providing a silicon oxide film on the side wall of the floating gate electrode using a CVD silicon oxide film. .

[0021]

[0022]

Embodiments of the present invention will be described below with reference to the drawings. The memory cell used in the embodiment uses a silicon substrate as a semiconductor substrate and an oxide film as a gate insulating film.

[Embodiment 1] FIGS. 1A to 1E show an embodiment of a memory cell forming process of the present invention. First, a buried diffusion layer (source / drain diffusion layer) 7 is formed in an element region on a silicon substrate 1 on which an element isolation region is formed by a LOCOS isolation method, and then, as shown in FIG. A silicon thermal oxide film having a thickness of 100 ° is formed as the film 2 by a thermal oxidation method.

Thereafter, a film thickness of 2000 for the floating gate electrode is used.
The polysilicon film 3 is formed by the CVD method. On this, a silicon oxide film 4 (film thickness of 40 °) / silicon nitride film 5 (film thickness of 80 °) as an ONO film for insulating the interlayer between the control gate electrode and the floating gate electrode (equivalent to a silicon oxide film thickness of 120 °). / Silicon oxide film 6 (thickness: 40 °) is formed. Further, a silicon nitride film 10 for mask (film thickness 1400 °) is formed on this substrate. Next, the mask silicon nitride film 10 and the ONO film are processed into a stripe shape by photolithography and dry etching of the silicon oxide film and the silicon nitride film to partially expose the polysilicon film 3 for the floating gate electrode.

Thereafter, as shown in FIG. 1B, the polysilicon film 3 for the floating gate electrode is LOCOS-oxidized,
A LOCOS oxide film 11 having a thickness of 1000 .ANG. Is formed in a portion not covered by the silicon nitride film 10 for a mask. In this step, a part of the LOCOS oxide film 11 has a bird's beak shape and partially enters immediately below the ONO film.

Subsequently, the silicon nitride film 10 for the mask is
The floating gate electrode is processed by etching the LOCOS oxide film 11, the polysilicon film 3 for the floating gate electrode, and the insulating film 2 for the floating gate using the mask as a mask. As a result, a bird's beak-like oxide film 12 remains in a portion of the side surface of the floating gate electrode polysilicon film 3 that is in contact with the ONO film (FIG. 1C).

Thereafter, thermal oxidation was performed at 900 ° C.
As shown in (d), a sidewall oxide film 13 is formed on the sidewall of the polysilicon film 3 for the floating gate electrode processed into an electrode shape, and at the same time, the oxide film 14 for the control gate insulating film (film thickness 200).
Å) is formed. At this time, the thickness of the sidewall oxide film 13 is
Although it largely depends on the impurity content of the polysilicon film 3 and the like, roughly, it is as thin as about 100 ° near the ONO and as thick as about 300 ° near the floating gate insulating film 2.

Next, the mask silicon nitride film 10 is removed by wet etching using phosphoric acid, and a control gate electrode polysilicon film 15 (thickness 1500 °) is deposited thereon. It is processed into a control gate electrode shape by dry etching of silicon (FIG. 1E).

Finally, an insulating film (not shown) is formed on the entire surface of the substrate 1 so as to cover these patterns, and contact holes to each electrode of the memory cell are formed. An advantage of the present invention is that data writing characteristics and data holding characteristics can be improved. According to this embodiment, since the bird's beak-like oxide film 12 exists in the contact portion of the floating gate polysilicon film with the ONO film, the oxide film thickness on the side surface of the floating gate polysilicon film in this portion is increased. As a result, the concentration of the electric field at the contact portion at the time of writing data to the memory cell is reduced, and the flow of accumulated electrons from the control gate electrode to the control gate electrode is suppressed. As a result, data writing characteristics and data holding characteristics can be improved.

[Embodiment 2] In this embodiment, FIG.
The processing up to the processing of the floating gate electrode shown in (c) is performed in the same manner as in the first embodiment. A thermal oxide film remains in a bird's beak shape in a portion 12 of the sidewall of the polysilicon film 3 for the floating gate electrode which is in contact with the ONO film.

Thereafter, as shown in FIG. 2A, a CVD oxide film 21 (thickness: 200 °) is formed on the entire surface of the silicon substrate 1. The thickness of the CVD oxide film 21 on the side surface of the polysilicon film 3 does not depend on the impurity content and the like of the polysilicon film 3, and is the same on both the side surface near the ONO film and the side surface near the tunnel gate oxide film 2. become.

Next, as shown in FIG. 2B, the entire surface of the CVD silicon oxide film is etched back by anisotropic etching in the vertical direction to expose the upper surface of the mask silicon nitride film 10 and the substrate surface. At this time, the polysilicon film 3
The side wall oxide film 22 remains on the side surface of.

Next, the mask silicon nitride film 10 is removed by wet etching using phosphoric acid. At this time,
By covering the side surface of the silicon nitride film 5 constituting the ONO film with the silicon oxide film 21, a part of the side surface is not removed by wet etching using phosphoric acid.

Next, an oxide film 24 for the control gate insulating film (thickness 100 °) is formed by thermal oxidation at 900 ° C., and subsequently, the polysilicon thin film 23 for the control gate electrode (thickness 1500).
Å) is deposited and processed into a control gate electrode shape by photolithography technology and polysilicon dry etching technology (FIG. 2C).

Finally, an insulating film (not shown) is formed on the entire surface of the substrate 1 so as to cover these patterns, and contact holes to each electrode of the memory cell are formed.

Also in this embodiment, since the bird's beak-like oxide film 12 exists in the contact portion of the floating gate polysilicon film with the ONO film, the oxide film thickness on the side surface of the floating gate polysilicon film in this portion is increased. The same effects as in the first embodiment can be obtained.

Further, in this embodiment, by using a CVD oxide film as the side wall oxide film, in addition to the effect of the first embodiment, it is possible to set the side wall oxide film to a uniform film thickness. Since the silicon nitride film constituting the interlayer insulating film is not eroded during wet etching when removing the silicon nitride film for a mask, it is possible to maintain good insulation of the interlayer insulating film, and furthermore, it is possible to maintain the thickness of the sidewall oxide film and the control gate. The gate oxide film thickness of each portion can be set independently, and a silicon oxide film having an optimum film thickness can be used.

[0038]

According to the present invention, since a bird's beak-like oxide film exists at the contact portion between the floating gate electrode polysilicon film and the interlayer insulating film, the oxide film thickness on the side surface of the floating gate polysilicon film in this portion is provided. Becomes thicker. As a result, the concentration of the electric field at the contact portion at the time of writing data to the memory cell is reduced, and the flow of accumulated electrons from the control gate electrode to the control gate electrode is suppressed. As a result, data writing characteristics and data holding characteristics can be improved.

Further, by using a CVD oxide film as the side wall oxide film, it is possible to set the side wall oxide film to a uniform thickness, and the silicon nitride film constituting the interlayer insulating film is made of silicon for mask. Since it is not eroded during wet etching when the nitride film is removed, it is possible to maintain good insulation of the interlayer insulating film.Furthermore, the side wall oxide film thickness and the gate oxide film thickness of the control gate portion are independently set, and Since a silicon oxide film having an optimum thickness can be used, data writing characteristics and data holding characteristics can be further improved.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing one example of a production method of the present invention.

FIG. 2 is a schematic sectional view showing an example of the production method of the present invention.

FIG. 3 is a schematic sectional view showing a conventional manufacturing method.

[Explanation of symbols]

 1, 31 silicon substrate 2, 32 floating gate oxide film 3, 33 polysilicon film for floating gate electrode 4, 6, 34, 36 silicon oxide film 5, 35 silicon nitride film 7, 37 buried diffusion layer (source / drain diffusion layer) 10) silicon nitride film for mask 11 LOCOS oxide film 12 bird's beak oxide film 13, 22, 38 sidewall oxide film 14, 24, 39 oxide film for control gate insulating film 15, 23, 40 polysilicon film for control gate 21 CVD silicon Oxide film

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (6)

(57) [Claims] An insulating film for a floating gate, a floating gate electrode formed of a polysilicon film, an interlayer insulating film provided on the floating gate electrode, and a side surface of the floating gate electrode on an element region of a semiconductor substrate. and the sidewall silicon oxide film covering, in the split gate type flash memory cell control gate electrode which is insulated from the floating gate electrode is provided by the interlayer insulating film and the sidewall silicon oxide film, the interlayer insulation
The edge film consists of silicon oxide, silicon nitride and silicon
A stacked film comprising three layers of oxide films, wherein the floating gate
At least a portion near the side surface of the polysilicon on the electrode upper surface,
Replaced by a thicker oxide film towards the sides
And the side wall silicon oxide film is formed by CVD silicon.
A split-gate type flash memory cell characterized by being provided with an oxide film . 2. The method according to claim 1, wherein the side wall silicon oxide film is formed by the interlayer insulation.
It is provided so as to cover the side surface of the silicon nitride film in the edge film.
2. The split according to claim 1, which is a CVD silicon oxide film.
Togate flash memory cell. 3. A floating gate on an element region of a semiconductor substrate.
Forming an insulating film for floating gate and floating on the insulating film for floating gate.
Forming a polysilicon film for a play gate electrode;
Forming an interlayer insulating film on the polysilicon film;
Forming a silicon nitride film for a mask on the insulating film;
The silicon nitride film for the mask and the interlayer insulating film are
Processing into a pattern, and processing into a predetermined electrode pattern.
Using the fabricated silicon nitride film for a mask as a mask, the floating
LOCOS oxidation of polysilicon film for play gate electrode
And then using the mask silicon nitride film as a mask.
LOCOS oxide film and floating gate
Forming a polysilicon film for an electrode into an electrode shape;
Extremely shaped polysilicon film for floating gate electrode
Forming a thermal oxide film on the side wall;
Removing the silicon nitride film;
Deposits a silicon thin film and photolithography
And control gate electrode shape by dry etching
Split-gate type flash memory cell
Manufacturing method. 4. A floating gate on an element region of a semiconductor substrate.
Forming an insulating film for floating gate and floating on the insulating film for floating gate.
And as factories for forming the Yu gate electrode polysilicon film, the
Forming an interlayer insulating film on the polysilicon film;
Forming a silicon nitride film for a mask on the insulating film;
The silicon nitride film for the mask and the interlayer insulating film are
Processing into a pattern, and processing into a predetermined electrode pattern.
Using the fabricated silicon nitride film for a mask as a mask, the floating
LOCOS oxidation of polysilicon film for play gate electrode
And then using the mask silicon nitride film as a mask.
LOCOS oxide film and floating gate
Forming a polysilicon film for an electrode into an electrode shape;
CVD silicon oxide is applied over the entire surface of the electrode structure
After forming an oxide film, silicon oxide is anisotropically etched.
The oxide film is etched back to form a silicon layer on the side wall of the floating gate electrode.
Forming a silicon oxide film, followed by the mask silicon
Removing the nitrided silicon film and a policy for the control gate electrode.
Deposit a silicon thin film and apply it to photolithography and
Forming into control gate electrode shape by light etching
Of the split gate type flash memory cell including
Production method. 5. The method according to claim 1, wherein the interlayer insulating film is a silicon oxide film,
Product consisting of three layers of silicon nitride film and silicon oxide film
5. The split gate according to claim 3, which is a layer film.
Manufacturing method of a flash memory cell. 6. The method according to claim 1, wherein the interlayer insulating film is a silicon oxide film,
Product consisting of three layers of silicon nitride film and silicon oxide film
A floating gate formed by the above-mentioned CVD
The silicon oxide film on the side wall of the
5. The switch according to claim 4, wherein the switch is formed so as to cover the side surfaces of the passivation film.
A method for manufacturing a split gate flash memory cell.