US20070272962A1 - Semiconductor Device with L-Shaped Spacer and Method of Manufacturing the Same - Google Patents
Semiconductor Device with L-Shaped Spacer and Method of Manufacturing the Same Download PDFInfo
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- US20070272962A1 US20070272962A1 US11/465,881 US46588106A US2007272962A1 US 20070272962 A1 US20070272962 A1 US 20070272962A1 US 46588106 A US46588106 A US 46588106A US 2007272962 A1 US2007272962 A1 US 2007272962A1
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- 125000006850 spacer group Chemical group 0.000 title claims abstract description 92
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 48
- 238000002955 isolation Methods 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000002131 composite material Substances 0.000 claims abstract description 13
- 238000007667 floating Methods 0.000 claims description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 15
- 239000000377 silicon dioxide Substances 0.000 claims description 15
- 235000012239 silicon dioxide Nutrition 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000007517 polishing process Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 2
- 238000007669 thermal treatment Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 230000015654 memory Effects 0.000 description 16
- 230000008878 coupling Effects 0.000 description 13
- 238000010168 coupling process Methods 0.000 description 13
- 238000005859 coupling reaction Methods 0.000 description 13
- 230000000694 effects Effects 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 230000010354 integration Effects 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- FRIKWZARTBPWBN-UHFFFAOYSA-N [Si].O=[Si]=O Chemical compound [Si].O=[Si]=O FRIKWZARTBPWBN-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- the subject invention relates to a semiconductor device and its manufacturing method, especially to a semiconductor device with an L-shape spacer and its manufacturing method.
- a corner thinning effect often occurs in the tunnel insulating layer of the device area of flash memory, lowering the coupling ratio thereby.
- a lower coupling ratio requires a higher gate voltage to erase the content of the memory, locally generating a high electric field at the edge of the device area and causing serious reliability problems in the devices. Problems include hot-carrier traps, damage to the oxide layers, reduction of write/erase tolerance, read interference, and a decrease of data retention, and thus inhibit the size reduction of flash memory.
- flash memory with a lower coupling ratio generates the Fowler-Nordheim tunneling (“F-N” tunneling) effect at a higher electric field.
- F-N Fowler-Nordheim tunneling
- the electron transporting rate between the floating gate and the source/drain becomes slower, thereby, decreasing the rate of the read/write property. Consequently, when manufacturing semiconductors, it is important to produce a flash memory that has a high coupling ratio without the detriment of the corner thinning effect in the tunnel insulating layer.
- the shallow trench isolation structure 11 and the active area 12 are formed onto the substrate 10 .
- a spacer 13 is formed from the insulating layer on the edge of the active area 12 and at the side of the shallow trench isolation structure 11 .
- the spacer 13 fails to effectively control the coupling ratio. Still referring to FIG. 1 , the spacer 13 will reduce the area of the tunnel 15 under the floating gate 14 , thus, reducing the channel current between the floating gate 14 and the substrate 10 and slowing down the read/write speed.
- the semiconductor industry consistently seeks to increase the integration of flash memories without increasing manufacturing costs and avoiding a low coupling ratio to enhance the speed and reliability of the read/write property. Therefore, the subject invention provides a solution that particularly addresses the above problems.
- One object of the subject invention is to provide a method for manufacturing a semiconductor device with an L-shape spacer so as to provide a flash memory with high integration and a high coupling ratio.
- the method comprises the following steps: forming a shallow trench isolation structure and an active area on a substrate, wherein the active area is covered by a first insulating layer; and depositing a second insulating layer to cover both the first insulating layer and the shallow trench isolation structure. Thereafter, a third insulating layer is deposited on the second insulating layer, followed by removing a portion from both the second insulating layer and third insulating layer to form an L-shape second insulating spacer and a third insulating spacer. Afterwards, the third insulating spacer is removed, leaving the L-shape second insulating layer spacer on the first insulating layer.
- the semiconductor device comprises a substrate, a composite spacer, and a tunnel insulating layer.
- the substrate comprises a shallow trench isolation structure and a neighboring active area.
- the composite spacer is located on a sidewall of the shallow trench isolation structure and comprises a first insulating spacer and an L-shape second insulating spacer.
- the first insulating spacer is located between the L-shape second insulating spacer and the substrate.
- the tunnel insulating layer is located on the substrate of the active area and connects to the first insulating spacer on its corresponding side.
- FIG. 1 shows a cross-section view of a spacer structure for reducing the corner thinning effect of the tunnel insulating layer in the prior art.
- FIGS. 2 to 8 show cross-sectional views of one embodiment method of the present invention for manufacturing a semiconductor device with an L-shape spacer according to the subject invention.
- FIG. 9 shows an embodiment of the steps subsequent to those depicted in FIG. 8 , the embodiment comprises both the formation of a floating gate with a patterned mask layer and the formation of a dielectric layer and a control gate.
- FIGS. 10 to 12 show another embodiment of the steps subsequent to those depicted in FIG. 8 , the embodiment comprises the formation of a floating gate by a chemical mechanical polishing process, and the formation of a dielectric layer and a control gate.
- FIG. 13 shows another embodiment of the steps subsequent to those depicted in FIG. 8 , the embodiment comprises the formation of a floating gate composed of a multilayered polysilicon.
- FIG. 14 shows an equivalent circuit of one embodiment of the semiconductor device according to the subject invention.
- FIG. 2 shows that a first insulating layer 110 and an insulating layer 120 are separately formed onto a silicon substrate 100 of a semiconductor.
- the first insulating layer 110 is a silicon dioxide layer formed by thermal oxidation and has a thickness ranging from about 10 ⁇ to about 1000 ⁇ .
- the insulating layer 120 is preferably a silicon nitride layer formed by a deposition process, with a thickness ranging from about 500 ⁇ to about 2000 ⁇ .
- a predetermined shallow trench isolation area and a predetermined active area are defined by performing an anisotropic or isotropic etching process with an appropriate photoresist (not depicted).
- Another insulating layer 130 is then deposited to cover the predetermined shallow trench isolation area and the predetermined active area located on the substrate 100 .
- a high density plasma oxide layer as the insulating layer 130 is deposited using a high density plasma process to cover the substrate 100 .
- the insulating layer 120 and portions of the high density plasma oxide layer on the regions other than the shallow trench isolation area are removed by a chemical mechanical polishing (“CMP”) process and an anisotropic etching process.
- CMP chemical mechanical polishing
- a second insulating layer 160 is deposited to cover the first insulating layer 110 and the shallow trench isolation structure 140 .
- a third insulating layer 170 is deposited on the second insulating layer 160 .
- the second insulating layer 160 is a silicon nitride layer formed by a deposition process, with a thickness ranging from about 10 ⁇ to about 500 ⁇ .
- the third insulating layer 170 is a silicon dioxide layer.
- the etching back step comprises the removal of a portion from the third insulating layer 170 by an anisotropic dry etching process so as to form the third insulating spacer 170 a , followed by the removal of a portion from the second insulating layer 160 with an isotropic or anisotropic etching process to form the second insulating spacer 160 a above the first insulating layer 110 .
- the etching back step may etch through the first insulating layer 110 and also removes a portion from layer 110 as shown in FIG. 5 .
- FIG. 6 shows the removal of the third insulating spacer 170 a of the two-layer spacer by an isotropic wet etching process.
- the time for removing the third insulating spacer 170 a and a portion of the first insulating layer 110 above the substrate 100 should be controlled to leave a portion of the first insulating layer 110 and form a first insulating spacer 110 a under the L-shape second insulating spacer 160 a .
- the first insulating spacer 110 a and the L-shape second insulating spacer 160 a located thereon are combined as a composite spacer.
- a tunnel insulating layer 180 is formed on the substrate 100 .
- the tunnel insulating layer 180 is identical in material to the first insulating spacer 110 a .
- the first insulating spacer 110 a described in the above-mentioned embodiment is made of a silicon dioxide layer formed by a thermal oxidation process; thus, thermal oxidation is also conducted to form a silicon dioxide layer as the tunnel insulating layer 180 .
- both sides of the tunnel insulating layer 180 connect to the corresponding first insulating layer spacers 110 a .
- the presence of the first insulating spacer 160 a effectively prevents the thinning effect of the tunnel layer that occurred in the prior art.
- a silicon dioxide layer 190 is generally formed on the L-shape second insulating layer spacer 160 a as the formation of the tunnel insulating layer.
- a first polysilicon layer is deposited and then patterned with a mask layer (not depicted) to form a floating gate 200 .
- a dielectric layer 210 is formed on the floating gate 200 , wherein the material of the dielectric layer 210 can be silicon dioxide, silicon nitride, a material with a high dielectric constant, or a combination thereof.
- the dielectric layer 210 has a sandwich structure, such as silicon dioxide-silicon nitride-silicon dioxide (Oxide-Nitride-Oxide, “ONO”).
- a second polysilicon layer is deposited on the dielectric layer 210 to form a control gate 220 so as to provide a flash memory according to the subject invention.
- the flash memory provided by the above-mentioned process is one embodiment of the subject invention.
- Various floating gates may be adopted to meet different requirements. For example, the following combination may be adopted to avoid alignment error that may be encountered in defining a floating gate.
- a process such as a chemical mechanical polishing process is used to remove a portion from the first polysilicon layer until the upper surface of the shallow trench isolation structure 140 is exposed to form a floating gate 300 .
- the insulating layer (high density plasma oxide layer) in the shallow trench isolation structure 140 is etched back to a predetermined depth by using an isotropic or anisotropic etching process.
- the predetermined depth should not be overly deep, as to keep the level of the remained insulating layer in the shallow trench isolation structure 140 higher than the lower portion of the L-shape second insulating spacer 160 a . Then, the portion of the L-shape second insulating spacer 160 a exposed on the sidewall of the floating gate 300 is removed to form a cornered L-shape second insulating spacer 160 a . Afterwards, the subsequent processes are substantially the same as those described in reference to FIG. 7 . Particularly, as depicted in FIG. 12 , a dielectric layer 310 , made of silicon dioxide, silicon nitride, a material with a high dielectric constant, or a combination thereof, is formed on the floating gate 300 .
- the dielectric layer 310 has an ONO structure.
- a second polysilicon layer is then deposited onto the dielectric layer 310 to form a control gate 320 .
- this embodiment can be accomplished with one less mask, and also avoid alignment error due to the self-alignment property of the floating gate 300 .
- a floating gate composed of a multilayered polysilicon can be employed. Specifically, as shown in FIG. 13 , a thin polysilicon layer 400 is deposited and then implanted with ions, followed by depositing a polysilicon layer 500 to substantially fill the region between the shallow trench isolation structures 140 . Afterwards, a thermal treatment, such as annealing, is conducted to produce a floating gate composed of a multilayered polysilicon.
- a semiconductor device with an L-shape spacer comprises a substrate, a shallow trench isolation structure, an active area, a composite spacer, and a tunnel insulating layer.
- the substrate comprises a shallow trench isolation structure 140 and a neighboring active area 150 .
- a composite spacer composed of a first insulating spacer 110 a and an L-shape second insulating spacer 160 a is formed on the sidewall of the shallow trench isolation structure 140 .
- the first insulating spacer 110 a is located between the L-shape second insulating spacer 160 a and the substrate 100 .
- the tunnel insulating layer 180 is located on the substrate portion of the active area 150 and connects to the first insulating spacer 110 a on its corresponding side.
- the above-mentioned semiconductor device can further comprise a floating gate 200 , a dielectric layer 210 , and a control gate 220 .
- the floating gate 200 can be a polysilicon layer that covers both the L-shape second insulating spacer 160 a and the tunnel insulating layer 180 located in the active area 150 .
- the dielectric layer 210 covers the floating gate 200 and the upper surface of the shallow trench isolation structure 140 between the floating gates 200 .
- the control gate 220 covers the dielectric layer 210 .
- the material of the dielectric layer 210 can be silicon dioxide, silicon nitride, a material with a high dielectric constant, or a combination thereof.
- the dielectric layer 210 is a composite dielectric layer with an ONO structure.
- the control gate 220 can be a polysilicon layer.
- FIG. 14 shows an equivalent circuit formed by the composite spacer (including the L-shape second insulating spacer 160 a and the first insulating spacer 110 a ), the tunnel insulating layer 180 , the floating gate 200 , the dielectric layer 210 , and the control gate 220 of the semiconductor device disclosed in the subject invention.
- the coupling ratio (“CR”) of said equivalent circuit can be calculated from the following equation (I):
- C 210 the capacitance formed by the control gate 220 , the dielectric layer 210 , and the floating gate 200 .
- C 160a/110a the capacitance formed by the floating gate 200 , the composite spacer that is composed of the L-shape second insulating spacer 160 a and the first insulating spacer 110 a , and the substrate 100 .
- C 180 the capacitance formed by the floating gate 200 , the tunnel insulating layer 180 , and the substrate 100 .
- C 160a/110a is effectively reduced, i.e., the denominator of the coupling ratio (“CR”) is reduced.
- CR the denominator of the coupling ratio
- the thickness of the L-shape second insulating spacer and that of the first insulating spacer can be controlled, unaffected by the variation of the height or thickness of the insulating layer in the shallow trench isolation area.
- the thickness is also unaffected by the etching-back conditions as evident in conventional semiconductor devices.
- the subject invention can effectively control the coupling ratio.
- the total thickness of the first insulating spacer and the L-shape spacer is thinner than that of the insulating spacer of conventional semiconductor devices, and thus, is sufficient enough to allow F-N tunneling. Consequently, the tunnel area under the floating gate is not substantially reduced.
- the semiconductor device with an L-shape spacer of the subject invention and its manufacturing method can increase and stably control the coupling ratio without reducing the tunnel area under the floating gate, and thus, improve the write/read speed and reliability.
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Abstract
Description
- This application claims priority to Taiwan Patent Application No. 095118551 filed on May 25, 2006.
- Not applicable.
- 1. Field of the Invention
- The subject invention relates to a semiconductor device and its manufacturing method, especially to a semiconductor device with an L-shape spacer and its manufacturing method.
- 2. Descriptions of the Related Art
- In recent years, high integration flash memories have been used in many industries. One reason is that the reduction of memory cell size significantly decreased the production cost. Conventional shallow trench isolation (“STI”) technologies have often been utilized in the production of flash memories because of the minimized size of the memory cells manufactured thereby and the high integration of the flash memories.
- However, a corner thinning effect often occurs in the tunnel insulating layer of the device area of flash memory, lowering the coupling ratio thereby. A lower coupling ratio requires a higher gate voltage to erase the content of the memory, locally generating a high electric field at the edge of the device area and causing serious reliability problems in the devices. Problems include hot-carrier traps, damage to the oxide layers, reduction of write/erase tolerance, read interference, and a decrease of data retention, and thus inhibit the size reduction of flash memory. Moreover, flash memory with a lower coupling ratio generates the Fowler-Nordheim tunneling (“F-N” tunneling) effect at a higher electric field. That is, the electron transporting rate between the floating gate and the source/drain becomes slower, thereby, decreasing the rate of the read/write property. Consequently, when manufacturing semiconductors, it is important to produce a flash memory that has a high coupling ratio without the detriment of the corner thinning effect in the tunnel insulating layer.
- Regarding the corner thinning effect of the tunnel insulating layer in the device area, a spacer in the device area of the flash memory device has been proposed. Referring to
FIG. 1 , the shallowtrench isolation structure 11 and theactive area 12 are formed onto thesubstrate 10. To reduce the corner thinning effect, aspacer 13 is formed from the insulating layer on the edge of theactive area 12 and at the side of the shallowtrench isolation structure 11. - However, the use of the
spacer 13 fails to effectively control the coupling ratio. Still referring toFIG. 1 , thespacer 13 will reduce the area of thetunnel 15 under thefloating gate 14, thus, reducing the channel current between thefloating gate 14 and thesubstrate 10 and slowing down the read/write speed. - Given the above limitations, the semiconductor industry consistently seeks to increase the integration of flash memories without increasing manufacturing costs and avoiding a low coupling ratio to enhance the speed and reliability of the read/write property. Therefore, the subject invention provides a solution that particularly addresses the above problems.
- One object of the subject invention is to provide a method for manufacturing a semiconductor device with an L-shape spacer so as to provide a flash memory with high integration and a high coupling ratio. The method comprises the following steps: forming a shallow trench isolation structure and an active area on a substrate, wherein the active area is covered by a first insulating layer; and depositing a second insulating layer to cover both the first insulating layer and the shallow trench isolation structure. Thereafter, a third insulating layer is deposited on the second insulating layer, followed by removing a portion from both the second insulating layer and third insulating layer to form an L-shape second insulating spacer and a third insulating spacer. Afterwards, the third insulating spacer is removed, leaving the L-shape second insulating layer spacer on the first insulating layer.
- Another object of the subject invention is to provide a semiconductor device with an L-shape spacer to resolve the reliability problems resulting from both the flash memory's low coupling ratio and the slowing down of the read/write speed as a result of a low channel current. The semiconductor device comprises a substrate, a composite spacer, and a tunnel insulating layer. The substrate comprises a shallow trench isolation structure and a neighboring active area. The composite spacer is located on a sidewall of the shallow trench isolation structure and comprises a first insulating spacer and an L-shape second insulating spacer. The first insulating spacer is located between the L-shape second insulating spacer and the substrate. The tunnel insulating layer is located on the substrate of the active area and connects to the first insulating spacer on its corresponding side.
-
FIG. 1 shows a cross-section view of a spacer structure for reducing the corner thinning effect of the tunnel insulating layer in the prior art. -
FIGS. 2 to 8 show cross-sectional views of one embodiment method of the present invention for manufacturing a semiconductor device with an L-shape spacer according to the subject invention. -
FIG. 9 shows an embodiment of the steps subsequent to those depicted inFIG. 8 , the embodiment comprises both the formation of a floating gate with a patterned mask layer and the formation of a dielectric layer and a control gate. -
FIGS. 10 to 12 show another embodiment of the steps subsequent to those depicted inFIG. 8 , the embodiment comprises the formation of a floating gate by a chemical mechanical polishing process, and the formation of a dielectric layer and a control gate. -
FIG. 13 shows another embodiment of the steps subsequent to those depicted inFIG. 8 , the embodiment comprises the formation of a floating gate composed of a multilayered polysilicon. -
FIG. 14 shows an equivalent circuit of one embodiment of the semiconductor device according to the subject invention. - One embodiment of the manufacturing method is provided below to illustrate how the subject invention resolves the problems and drawbacks encountered in the prior technologies.
FIG. 2 shows that a firstinsulating layer 110 and aninsulating layer 120 are separately formed onto asilicon substrate 100 of a semiconductor. Preferably, the firstinsulating layer 110 is a silicon dioxide layer formed by thermal oxidation and has a thickness ranging from about 10 Å to about 1000 Å. Theinsulating layer 120 is preferably a silicon nitride layer formed by a deposition process, with a thickness ranging from about 500 Å to about 2000 Å. Afterwards, a predetermined shallow trench isolation area and a predetermined active area are defined by performing an anisotropic or isotropic etching process with an appropriate photoresist (not depicted). Anotherinsulating layer 130 is then deposited to cover the predetermined shallow trench isolation area and the predetermined active area located on thesubstrate 100. In one preferred embodiment of the subject invention, a high density plasma oxide layer as theinsulating layer 130 is deposited using a high density plasma process to cover thesubstrate 100. Thereafter, theinsulating layer 120 and portions of the high density plasma oxide layer on the regions other than the shallow trench isolation area are removed by a chemical mechanical polishing (“CMP”) process and an anisotropic etching process. As shown inFIG. 3 , a shallowtrench isolation structure 140 and anactive area 150 are finally formed on thesubstrate 100, with the firstinsulating layer 110 located on theactive area 150. - Referring to
FIG. 4 , a secondinsulating layer 160 is deposited to cover the firstinsulating layer 110 and the shallowtrench isolation structure 140. Then, a thirdinsulating layer 170 is deposited on the secondinsulating layer 160. Preferably, the secondinsulating layer 160 is a silicon nitride layer formed by a deposition process, with a thickness ranging from about 10 Å to about 500 Å. The thirdinsulating layer 170 is a silicon dioxide layer. Afterwards, as shown inFIG. 5 , a portion from both the thirdinsulating layer 170 and secondinsulating layer 160 is removed by etching back to form athird insulating spacer 170 a and an L-shape secondinsulating spacer 160 a. Preferably, the etching back step comprises the removal of a portion from the thirdinsulating layer 170 by an anisotropic dry etching process so as to form thethird insulating spacer 170 a, followed by the removal of a portion from the secondinsulating layer 160 with an isotropic or anisotropic etching process to form the secondinsulating spacer 160 a above the firstinsulating layer 110. The etching back step may etch through the firstinsulating layer 110 and also removes a portion fromlayer 110 as shown inFIG. 5 . - Following
FIG. 5 ,FIG. 6 shows the removal of the thirdinsulating spacer 170 a of the two-layer spacer by an isotropic wet etching process. In this wet etching process, the time for removing the thirdinsulating spacer 170 a and a portion of the first insulatinglayer 110 above thesubstrate 100 should be controlled to leave a portion of the first insulatinglayer 110 and form afirst insulating spacer 110 a under the L-shape secondinsulating spacer 160 a. The firstinsulating spacer 110 a and the L-shape secondinsulating spacer 160 a located thereon are combined as a composite spacer. - Referring to
FIG. 7 , atunnel insulating layer 180 is formed on thesubstrate 100. In one preferred embodiment, thetunnel insulating layer 180 is identical in material to the firstinsulating spacer 110 a. In other words, the first insulatingspacer 110 a described in the above-mentioned embodiment is made of a silicon dioxide layer formed by a thermal oxidation process; thus, thermal oxidation is also conducted to form a silicon dioxide layer as thetunnel insulating layer 180. In addition, both sides of thetunnel insulating layer 180 connect to the corresponding first insulatinglayer spacers 110 a. The presence of the first insulatingspacer 160 a effectively prevents the thinning effect of the tunnel layer that occurred in the prior art. In addition, as shown in the partially enlarged view ofFIG. 7 provided inFIG. 8 , asilicon dioxide layer 190 is generally formed on the L-shape second insulatinglayer spacer 160 a as the formation of the tunnel insulating layer. - Referring to
FIG. 9 , after the formation of thetunnel insulating layer 180, a first polysilicon layer is deposited and then patterned with a mask layer (not depicted) to form a floatinggate 200. Thereafter, adielectric layer 210 is formed on the floatinggate 200, wherein the material of thedielectric layer 210 can be silicon dioxide, silicon nitride, a material with a high dielectric constant, or a combination thereof. Preferably, thedielectric layer 210 has a sandwich structure, such as silicon dioxide-silicon nitride-silicon dioxide (Oxide-Nitride-Oxide, “ONO”). Thereafter, a second polysilicon layer is deposited on thedielectric layer 210 to form acontrol gate 220 so as to provide a flash memory according to the subject invention. - The flash memory provided by the above-mentioned process is one embodiment of the subject invention. Various floating gates may be adopted to meet different requirements. For example, the following combination may be adopted to avoid alignment error that may be encountered in defining a floating gate. Referring to
FIG. 10 , after the deposition of the first polysilicon layer, a process such as a chemical mechanical polishing process is used to remove a portion from the first polysilicon layer until the upper surface of the shallowtrench isolation structure 140 is exposed to form a floatinggate 300. Then, as shown inFIG. 11 , the insulating layer (high density plasma oxide layer) in the shallowtrench isolation structure 140 is etched back to a predetermined depth by using an isotropic or anisotropic etching process. The predetermined depth should not be overly deep, as to keep the level of the remained insulating layer in the shallowtrench isolation structure 140 higher than the lower portion of the L-shape second insulatingspacer 160 a. Then, the portion of the L-shape second insulatingspacer 160 a exposed on the sidewall of the floatinggate 300 is removed to form a cornered L-shape second insulatingspacer 160 a. Afterwards, the subsequent processes are substantially the same as those described in reference toFIG. 7 . Particularly, as depicted inFIG. 12 , adielectric layer 310, made of silicon dioxide, silicon nitride, a material with a high dielectric constant, or a combination thereof, is formed on the floatinggate 300. Preferably, thedielectric layer 310 has an ONO structure. A second polysilicon layer is then deposited onto thedielectric layer 310 to form acontrol gate 320. In comparison with the aforementioned embodiment, this embodiment can be accomplished with one less mask, and also avoid alignment error due to the self-alignment property of the floatinggate 300. - In another embodiment, a floating gate composed of a multilayered polysilicon can be employed. Specifically, as shown in
FIG. 13 , athin polysilicon layer 400 is deposited and then implanted with ions, followed by depositing apolysilicon layer 500 to substantially fill the region between the shallowtrench isolation structures 140. Afterwards, a thermal treatment, such as annealing, is conducted to produce a floating gate composed of a multilayered polysilicon. - According to the above method, a semiconductor device with an L-shape spacer is provided. The semiconductor device comprises a substrate, a shallow trench isolation structure, an active area, a composite spacer, and a tunnel insulating layer. Using
FIG. 9 as an example, the substrate comprises a shallowtrench isolation structure 140 and a neighboringactive area 150. A composite spacer composed of a first insulatingspacer 110 a and an L-shape second insulatingspacer 160 a is formed on the sidewall of the shallowtrench isolation structure 140. The first insulatingspacer 110 a is located between the L-shape second insulatingspacer 160a and thesubstrate 100. Thetunnel insulating layer 180 is located on the substrate portion of theactive area 150 and connects to the first insulatingspacer 110 a on its corresponding side. - The above-mentioned semiconductor device can further comprise a floating
gate 200, adielectric layer 210, and acontrol gate 220. The floatinggate 200 can be a polysilicon layer that covers both the L-shape second insulatingspacer 160 a and thetunnel insulating layer 180 located in theactive area 150. Thedielectric layer 210 covers the floatinggate 200 and the upper surface of the shallowtrench isolation structure 140 between the floatinggates 200. Thecontrol gate 220 covers thedielectric layer 210. The material of thedielectric layer 210 can be silicon dioxide, silicon nitride, a material with a high dielectric constant, or a combination thereof. Preferably, thedielectric layer 210 is a composite dielectric layer with an ONO structure. Thecontrol gate 220 can be a polysilicon layer. - In the subject invention as shown in
FIG. 9 , the corner thinning effect of the tunnel oxide layer can be effectively prevented because of the presence of the first insulatingspacer 110 a in the corner of the active area.FIG. 14 shows an equivalent circuit formed by the composite spacer (including the L-shape second insulatingspacer 160 a and the first insulatingspacer 110 a), thetunnel insulating layer 180, the floatinggate 200, thedielectric layer 210, and thecontrol gate 220 of the semiconductor device disclosed in the subject invention. The coupling ratio (“CR”) of said equivalent circuit can be calculated from the following equation (I): -
CR=C 210/(C 210+2*C 160a/110a +C 180) (I) - wherein
- C210: the capacitance formed by the
control gate 220, thedielectric layer 210, and the floatinggate 200. - C160a/110a: the capacitance formed by the floating
gate 200, the composite spacer that is composed of the L-shape second insulatingspacer 160 a and the first insulatingspacer 110 a, and thesubstrate 100. - C180: the capacitance formed by the floating
gate 200, thetunnel insulating layer 180, and thesubstrate 100. - Because the first insulating layer at the corner of the active area of the subject invention is thicker than that of conventional devices, C160a/110a is effectively reduced, i.e., the denominator of the coupling ratio (“CR”) is reduced. Such reduction substantially raises the coupling ratio, and thus, improves the performance of the semiconductor device, especially the write/read speed and reliability of the flash memory.
- Moreover, in the method of the subject invention, the thickness of the L-shape second insulating spacer and that of the first insulating spacer can be controlled, unaffected by the variation of the height or thickness of the insulating layer in the shallow trench isolation area. The thickness is also unaffected by the etching-back conditions as evident in conventional semiconductor devices. Hence, the subject invention can effectively control the coupling ratio. Moreover, the total thickness of the first insulating spacer and the L-shape spacer is thinner than that of the insulating spacer of conventional semiconductor devices, and thus, is sufficient enough to allow F-N tunneling. Consequently, the tunnel area under the floating gate is not substantially reduced.
- Given the above, the semiconductor device with an L-shape spacer of the subject invention and its manufacturing method can increase and stably control the coupling ratio without reducing the tunnel area under the floating gate, and thus, improve the write/read speed and reliability.
- Although the above disclosure is provided, it is related to the preferred embodiments of the subject invention and not intended to limit the subject invention. People skilled in this field may proceed with changes and modifications without departing from the spirit and scope of the subject invention. Therefore, the scope of protection of the subject invention is based on the following claims as appended.
Claims (25)
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Cited By (3)
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US20090309151A1 (en) * | 2006-08-29 | 2009-12-17 | Micron Technology, Inc. | Semiconductor Constructions |
CN103579122A (en) * | 2012-08-09 | 2014-02-12 | 华邦电子股份有限公司 | Flash memory element manufacturing method |
CN104716099A (en) * | 2013-12-13 | 2015-06-17 | 旺宏电子股份有限公司 | Non-volatile memory and manufacturing method thereof |
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KR101831936B1 (en) | 2011-12-22 | 2018-02-26 | 삼성전자주식회사 | Method for forming a thin film and method for manufacturing a semiconductor device by using the same |
TWI499043B (en) * | 2012-07-19 | 2015-09-01 | Winbond Electronics Corp | Method for forming a flash memory device |
US9761662B1 (en) | 2017-02-03 | 2017-09-12 | Globalfoundries Inc. | Active area shapes reducing device size |
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US6022786A (en) * | 1997-02-27 | 2000-02-08 | Siemens Aktiengesellschaft | Method for manufacturing a capacitor for a semiconductor arrangement |
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US6022786A (en) * | 1997-02-27 | 2000-02-08 | Siemens Aktiengesellschaft | Method for manufacturing a capacitor for a semiconductor arrangement |
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CN103579122A (en) * | 2012-08-09 | 2014-02-12 | 华邦电子股份有限公司 | Flash memory element manufacturing method |
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