TWI499043B - Method for forming a flash memory device - Google Patents

Description

Flash memory device manufacturing method

The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a flash memory device.

Recently, flash memory has become a mainstream of non-volatile memory due to its high density, low cost, re-writable and erasable, and is widely used in various portable electronic devices. In the product. 1A~1F illustrate a method of fabricating a conventional NOR type flash memory device. Referring to Figure 1A, a substrate 102 is provided, such as a substrate. A shallow trench isolation structure 106 of tantalum oxide is formed in the substrate 102, wherein an upper portion of the shallow trench isolation structure 106 protrudes from the surface of the substrate 102, and thus the shallow trench isolation structure 106 includes a recess 108 therebetween. Next, a tunnel oxide 104 is formed on the substrate 102. Referring to FIG. 1B, a floating gate layer 110 of polysilicon is formed over the shallow trench isolation structure 106 and the substrate 102. Referring to FIG. 1C, a chemical mechanical polishing process is performed to remove portions of the floating gate layer 110 to form a floating gate 112 between the shallow trench isolation structures 106. Referring to FIG. 1D, a selective etching process is performed to remove a portion of the shallow trench isolation structure 106 such that the top surface of the shallow trench isolation structure 106 is lower than the surface of the floating gate 112. Referring to FIG. 1E, an insulating layer 114 including a first hafnium oxide layer, a tantalum nitride layer, and a second oxide layer is formed on the shallow trench isolation structure 106 and the floating gate 112. Referring to FIG. 1F, a control gate layer 116 is formed on the insulating layer 114.

With the miniaturization of the semiconductor process, when the process progresses to below 80 nm, the above-mentioned conventional NOR-type flash memory fabrication method may have the following problem: when the floating gate layer 110 composed of polysilicon is filled, since the polycrystalline germanium grains are too Large, the distance between the two adjacent shallow trench isolation structures 106 decreases with the process, which may result in the formation of voids or seams in the floating gate layer 110, which are exposed when the floating gate is subsequently ground. The underlying oxide oxide layer 104 is eroded by an acidic or alkaline solution in a subsequent cleaning step, resulting in electrical and reliability problems. Especially after entering the 80 nm process, the crystal grain diameter of the polycrystalline silicon is even larger than half the distance between the two adjacent shallow trench isolation structures 106. Therefore, the problem caused by the holes becomes more important.

Therefore, the industry needs a method for fabricating a flash memory device, which can solve the problem that the floating gate layer 110 is void due to too large a crystal grain.

According to the above, the present invention provides a method of fabricating a flash memory device, comprising: providing a substrate; forming a plurality of shallow trench isolation structures in the substrate, wherein an upper portion of the shallow trench isolation structure protrudes from a surface of the substrate Between the shallow trench isolation structures, including a recess; forming a tunneling oxide layer on the substrate; and forming a floating gate layer over the substrate and filling the recess, wherein forming the floating gate layer comprises forming a The first conductive layer acts as a seed layer and forms a second conductive layer on the first conductive layer.

In order to make the features of the present invention more comprehensible, the following detailed description of the embodiments and the accompanying drawings

Embodiments embodying the invention are discussed in detail below. It will be appreciated that the embodiments provide many applicable inventive concepts that can be implemented in a wide variety of variations. The specific embodiments discussed are merely illustrative of specific ways to use the embodiments and are not intended to limit the scope of the invention.

2A to 2G are views showing a method of fabricating a NOR type flash memory device according to an embodiment of the present invention. Referring to FIG. 2A, a substrate 202 is provided. The substrate 202 may be an insulating layer having germanium, a polymer substrate thereon, germanium, strain enthalpy, germanium, tantalum carbide and/or other materials. The substrate 202 is preferably germanium. . A shallow trench isolation structure 206 is formed in the substrate 202, wherein the upper portion of the shallow trench isolation structure 206 protrudes from the surface of the substrate 202, such that the shallow trench isolation structure 206 includes a recess 208 therebetween. The method of forming the shallow trench isolation structure 206 can include the steps of forming a plurality of trenches in the substrate 202 with suitable lithography and etching techniques, followed by filling the trenches with, for example, oxides, nitrides, or oxynitrides. Dielectric material. A chemical mechanical polishing process is performed to remove excess dielectric material beyond the surface of the substrate 202. Next, a selective etching process is performed such that the top surface of the substrate is lower than the surface of the shallow trench isolation structure 206, and a recess 208 is formed between the shallow trench isolation structures 206. A tunnel oxide 204 is formed on the substrate 202. The tunnel oxide layer 204 can be formed by thermal oxidation or chemical vapor deposition. The tunnel oxide layer 204 is preferably hafnium oxide.

Referring to FIG. 2B, a floating gate layer is formed over the shallow trench isolation structure 206 and the substrate 202. In order to improve the conventional technique, since the floating gate layer of the polysilicon is too large to cause voids, the present embodiment employs a plurality of floating gate structures, which will be described in detail below: first, to deposit a first conductive layer As a seed layer of the subsequently deposited layer, the first conductive layer 212 may be amorphous germanium or polycrystalline germanium, the first conductive layer 212 may have a thickness of 3 nm to 40 nm, and the first conductive layer 212 may be formed by a chemical vapor phase. Deposition method. Since the thickness of the first conductive layer 212 in the embodiment is relatively thin, the first conductive layer 212 having a small crystal grain size can be formed. Subsequently, an annealing process can be performed to convert the amorphous germanium into a polycrystalline germanium. If the first conductive layer 212 is deposited as a polycrystalline germanium, it is preferable to perform an annealing process. In an embodiment of the invention, the annealing process has a temperature of about 700 ° C to 1100 ° C. If the first conductive layer 212 is formed to be exposed to air, a cleaning process is performed to remove the native oxide. Subsequently, as shown in FIG. 2C, the second conductive layer 214 and the third conductive layer 216 are sequentially formed on the first conductive layer 212 as needed (for example, the thickness of the floating gate layer 218) to constitute the embodiment. Floating gate layer 218. It should be noted that although the floating gate layer 218 of the present embodiment is a structure including three conductive layers 212, 214, and 216, the present invention is not limited thereto, and the floating gate layer 218 may include more layers (for example, may be more A fourth conductive layer, a fifth conductive layer, a sixth conductive layer...), or fewer layers (eg, including only the first conductive layer and the second conductive layer).

Referring to FIG. 2D, a polishing process is performed to remove portions of the floating gate layer 218 to form a floating gate 220 between the shallow trench isolation structures 206. The polishing process of this embodiment may be a chemical mechanical polishing process or other suitable process. As shown in FIG. 2D, after the polishing process, the top surface of the floating gate 220 may be coplanar with the top surface of the shallow trench isolation structure 206. Referring to FIG. 2E, a selective etching process is performed to remove a portion of the shallow trench isolation structure 206 such that the top surface of the shallow trench isolation structure 206 is lower than the surface of the floating gate 220. The selective etching process of this embodiment can be adopted. For example, a wet etching method of immersing HF. In one embodiment, the top surface of the shallow trench isolation structure 206 after etching may be lower than the surface of the floating gate by 50 nm to 500 μm. Referring to FIG. 2F, an insulating layer 222 is formed on the shallow trench isolation structure 206 and the floating gate 220. The insulating layer 222 may be formed by a chemical vapor deposition method or the like, and the insulating layer 222 may be tantalum oxide, tantalum nitride, tantalum oxynitride or three layers including a first tantalum oxide layer, a tantalum nitride layer and a second oxide layer. Layer structure. Subsequently, please refer to FIG. 2G to form a control gate layer 224 on the insulating layer 222. The control gate layer 224 can be formed by chemical vapor deposition or the like, and the control gate layer 224 can be a polysilicon or other conductive layer.

In the above embodiment of the present invention, since the floating gate layer is formed, the seed layer having a smaller lattice size is formed first, so that the subsequent floating gate conductive layer can be formed into a smaller lattice size according to the lattice length of the seed layer. The layer, therefore, does not form a void when filling the groove between the shallow trench isolation structures, and can improve the problem of product electrical reliability and reliability due to the gap of the floating gate layer.

Although the preferred embodiments of the present invention are described above, it is not intended to limit the present invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. The scope of protection is subject to the definition of the scope of the patent application attached.

102‧‧‧Base

104‧‧‧ Tunneling Oxidation Layer

106‧‧‧Shallow trench isolation structure

108‧‧‧ Groove

110‧‧‧Floating gate layer

112‧‧‧Floating gate

114‧‧‧Insulation

116‧‧‧Control gate layer

202‧‧‧Base

204‧‧‧ Tunneling Oxidation Layer

206‧‧‧Shallow trench isolation structure

208‧‧‧ Groove

212‧‧‧First conductive layer

214‧‧‧Second conductive layer

216‧‧‧ third conductive layer

218‧‧‧Floating gate layer

220‧‧‧Floating gate

222‧‧‧Insulation

224‧‧‧Control gate layer

Figures 1A to 1F show cross-sectional views of various process stages in the fabrication of a conventional NOR type flash memory device.

2A to 2G are cross-sectional views showing a process of manufacturing a NOR flash memory device according to an embodiment of the present invention.

202‧‧‧Base

204‧‧‧ Tunneling Oxidation Layer

206‧‧‧Shallow trench isolation structure

212‧‧‧First conductive layer

214‧‧‧Second conductive layer

216‧‧‧ third conductive layer

218‧‧‧Floating gate layer

Claims (10)

A method of fabricating a flash memory device, comprising: providing a substrate; forming a plurality of shallow trench isolation structures in the substrate, wherein upper portions of the shallow trench isolation structures protrude from a surface of the substrate to make the shallow Between the trench isolation structures, including a recess; forming a tunneling oxide layer on the substrate; and forming a floating gate layer over the substrate and filling the recesses, wherein the floating gate is formed The step of forming includes forming a first conductive layer as a seed layer and forming a second conductive layer on the first conductive layer, and the first conductive layer abuts a sidewall of the upper portion of the shallow trench isolation structures. The method of fabricating a flash memory device according to claim 1, wherein the step of forming the floating gate layer further comprises forming at least one conductive layer on the second conductive layer. The method of manufacturing a flash memory device according to claim 1, wherein the first conductive layer is amorphous germanium or polycrystalline germanium. The method of manufacturing a flash memory device according to claim 1, wherein before the forming the second conductive layer, an annealing process is performed. The method of manufacturing a flash memory device according to claim 4, wherein the annealing process has a temperature of about 700 ° C to 1100 ° C. The method for manufacturing a flash memory device according to claim 4, further comprising performing a cleaning process. The method of manufacturing a flash memory device according to claim 1, further comprising: grinding the floating gate layer to form a plurality of floating gates. The method for manufacturing a flash memory device according to claim 7, further comprising: selectively etching the shallow trench isolation structures; forming an insulating layer on the shallow trench isolation structures and the floating And a control gate layer is formed on the insulating layer. The method of manufacturing a flash memory device according to claim 8, wherein the insulating layer comprises a first tantalum oxide layer, a tantalum nitride layer and a second tantalum oxide layer. The method of manufacturing a flash memory device according to claim 1, wherein the first conductive layer has a thickness of 3 nm to 40 nm.