^17351 A7 五、發明說明（ 复域： 本發明係有關於一種快閃記憶體（Flash memory)製 種’且更特别的是有關於一種具自對準（self-align )之快 閃記憶體製程。 复: 經 濟 部 智 慧 財 產 局 員 工 消費 合 作 社 印 製 當電腦微處理器之功能愈來愈強，軟體所進行之資料 計算也愈來愈龐大，當然記憶體之需求也就更高了。因此 更高積集度之發展意謂著更大容量之記憶體的產生。當 1980年代末期Intei以可電除且可程式唯讀記憶體 (Electrically Erasable Programmable R〇M?EEPROM) 相同之結構發展出”快閃記憶體，，（Flash mem〇ry)時，由於 貧料可以多次存入，讀出與清除，因此成爲發展最快速之 新一代記憶體。 非揮發性記憶體，尤其是快閃記憶體，在各種應用中 以漸增其重要性。在最近幾年，快閃記憶體之需求已漸高 於其他記憶體，因此，如何發展新世代之快閃記憶體技術， 及降低快閃記憶體之面積已成爲一重要課題。 快閃記憶體之結構類W EPR0M，也有控制閘和懸浮 閘之堆疊閘極，唯一的不同點爲在懸浮閘之下有一層高品 質之薄的穿隧二氧化石夕層。當程式寫入時，熱電子將；： (請先閱讀背面之注意事項再填寫本頁) --------訂------ 517351 A7 五、發明說明（） (TUnneling)此薄的穿隧二氧化矽層而進入 EPROM ;當記悻技p入眭 予閘，類似 田口己匕抹11于、時，只要將控制閘施以負 冷電子穿隧薄的穿陋一备办* & 、毛壓即可由 Η逐-乳化矽層而離開懸浮間到源極。 .....閃圯憶體之結構和EE：PR〇m相同，作由 記憶胞抹除機構和EEPR〇M不盡相同，豊= EEPR0M小得多；同時其資料之比 也比猶⑽用紫外光照射的大約2〇分鐘要快得多。因此 可以看出來快閃記憶體乃結合了 Ep議和eep 之優點。 m者 如第一圖中所示的爲依先前技術所製造的快閃記 體’其包括了在P型半導體底材10上，以光阻圖案（未圖 π )足義王動區1 6。接著，以乾式蝕刻法來形成_凹入半 導體晶圓内深約300_45〇 nm之淺溝渠隔離區〇 (Shallow Trench Is〇lation，STI )。接著去除光阻圖 案，並於其上形成一堆疊閘極結構。堆疊閘極包括了穿隧 一氧化矽層1 2，懸浮閘極層i 3。在薄的穿隧二氧化矽層 1 2和懸浮閘極層丨3形成之後，接著形成氧化矽/氮化矽/ 氧化石夕（〇N〇）之絶緣層14，和控制閘極層15。其中，在形 成懸浮閘極層13時，需以另一光罩加以定義其位置。因 此’在傳統之製程技術中，通常最少會要求兩道光罩來形 成懸浮閘極層1 3與主動區16。 假設將電壓V加在控制閘極層1 5上，並令半導體底 材1 0之電壓爲0時，由於半導體底材i 〇、懸浮閘極層i 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） Γ 請先閱讀背面之注意事項再填寫本頁} 訂--------- 經濟部智慧財產局員工消費合作社印製 517351 A7 ____________________ _______ B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 和控制閘極層15之間呈電容令、条,^ + 毛备人連（CapacitanceCoupling)狀態，所以加在懸浮閑極層i3上之電壓（Vfg) 可由下列公式算出： c +c. ^上式中，Cl爲半導體底材10與懸浮閘極層13間2 又連電容。C2懸浮間極層13和控制閑極層i5間之交連臂 容。 當快閃記憶體之製程技術將通道長度之尺寸降至 〇-18“m，甚至〇.13am時，對於先前非使用自對马 (Self-align )技術之快閃記憶體製程，會遭受到懸浮閑和 層13與主動區16間之對準問題。且另—方面，對以電弓 由源極注入懸浮閘極之快閃記憶體而言，懸浮閉極能覆^ 愈多口之源極面積或者穿隧二氧化矽層12愈薄，就有愈士 的程式化速度，然而減低穿隧二氧化矽層12的厚度會肩 資料保存時間的問題。 另一方面，當在外加電壓爲定値之情況下，爲了均 加懸浮閘極層13上之電壓（Vfg )，以達到可在最小外加 電壓情況下來產生穿隧二氧化矽層電流，可利用增加c 之宅谷値，造成大邵分之外加電壓均落在懸浮閘極層工: 上達成’亦即增加懸浮閘極層1 3和控制閘極層1 5間之通 (請先閱讀背面之注意事項再填寫本頁) ，裝--------訂----- 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297公釐） 517351 A7 五、發明說明（ 積。但由於微影蝕刻有其極限尺寸，俊户 、 J 便钟懸净閘極層間彼 此之分隔距離有其臨限値。因此若要利用增加面積之方式 來加大〇2之電容値，由於臨限値之限制，造成亦需使用 較大面積之淺溝渠隔離1 17’反而放大了整個快閃祀憶 體面積。雖然’傳统上有利„壁隙製程來克服微影㈣ 之極限尺寸，已進一步降低懸浮閘極層間彼此之分隔距 離。但由於其依然要使用微影触刻，因此在降低整 記憶體面積上仍爲有限。 、 因此如何解決懸浮閘極層13與主動區Μ間之 問題，和在不增加整個快閃記憶體面積之情況下增加C 之電容値，已成爲現今快閃記憶體製程技術所面臨θ 2 課題。 瑕大 發明目的及概述： (請先閱讀背面之注意事項再填寫本頁) ，裝---- 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 签於上述之發明背景中，依傳统技術所形成 憶體’由於其懸浮閘極層與主動區間’至少 二 同之光罩來分别形&，因此在進行光罩對準時 = 較精確的控制，因此本發明之—目的即爲使用-種自、= 式之快閃記億體製程，來解決上述問題。 玎+ ，本發明的另_目的在提供—種懸浮閉極層 製程万法，已在不犧牲快閃記憶體- /、Γ 故升懸浮閘 本紙張尺度適用中國國豕標準（CNS)A4規格（21〇 X 297公餐） 訂---------备- I I I _ 517351 A7 B7 五、發明說明（ 極層和控制閘極層間的耦合 容。 貝，以增加其間之交連電 依α本發明所揭露之製程方法，並勺八、 在半導體底材上形成隔離用之 :、c 3 (步驟爲首先 動區。録刻該淺溝渠隔離區以形：：離區，來分離出主 區，再形成-氧化石夕層於凹陷之淺^淺溝渠隔離 面上。利用非等向性乾触刻敍刻該氧區和晶圓之表 之側邊形成間壁隙。利用熱氧化 ^已於主動區 層，然後在於穿隨二氧化石牙随二氧化石夕 隔離區表面上形成 ’、’人凹^《淺溝渠 回瑱—氮化石夕層於此凹浮間極。接著 將未被氮化石夕層覆蓋之多晶石夕層氧 =用熱乳化珐 酸溶液Μ氮化"。以氧化=嶙 氮化石夕層和氧切層以完成__序、形人成氧化石夕層、 0Ν0介電層上形成多晶石夕掺雜閑極以°作二電層，然後在 % 專：了和敍刻方法將堆疊之閘極結構 形成子兀線，最後再以傳統之離子植入 以 雜區作爲源極和汲極後而完成此發明。 1所需之摻 以此方式所完成之快閃記憶體之懸 用微影製程，因此並不會如傳統技藝 並不需使 與主動區間，至少需使用兩面不同之光罩由來:=極層 常發生對準錯誤之情形。且本發明之懸浮刻： 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297公釐 517351 A7 B7 五、發明說明（ 極以 閘所 浮， 懸度 升深 提刻 欲 蚀 若加 此增 因 需 ， 僅 構 ， 結積 之面 起合 凸耦 有的 具間 成層 達極 來閘 區制 離控 隔和 渠層 電 連 交 之 間 其 加 增 下 形 情 積 面 總 體 憶 記 閃 快 牲 犧 不 在。 可容 明I 説 單 簡 式 圖 之 面 下： 考中 參其 如， 點解 優瞭 的易 隨容 伴加 多旻 許將 及後 況之 _ 圖 情付 述 前結 6V 6 並 明， 發述 本敘 細 詳 技 前 先 照 依 T 舉 例 圖 視 面 截 之 圓 ， 日00ί 導記 半閃 爲快 圖之 一成 第形 所 術 圖 視 面 截 之 k 隔 二渠 第溝 淺 成 形 上 圓 晶 體 導 半 1 於 術 技 明 發 本 照 依 爲 示 所 圖 昭叫 依 爲 示 所 圖 三 第溝 淺 成 形 上 圓 晶 體 導 半 1 於 術 技 明 發 本 圖 視 面 截 之 _、巨 隔 渠 本 昭叫 依 爲 示 所 圖 四 第溝 戔 刻 至 k 隔 渠 截 之 度 深 圓 晶 體 導 半- 於 術； 技圖 明視 發面 (請先閱讀背面之注意事項再填寫本頁) --訂------ 第 之 五行 第共 1 成 圖 形 上 圓 晶 體 導 半 1 於 術·， 技 圖 月視 發面 本 照 依 爲 示 所 截 之 層 電 介 經濟部智慧財產局員工消費合作社印製 六 - 第々矜 此 刻 蝕 上 圓 晶 體 導 半- 於 術 技 明 發 本 照 依 爲 示 所 圖 圖 視 面 截 之 後 層 電 介 層 所W 目S 七隧 第穿 1 成 形 上 圓 晶 ; 體圖 導視 半面 一 截 於之 術層 技矽 明、夺 發摻 本 照 依 爲 之 行 共 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 517351 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（） 第八圖所示爲依照本發明技術於一半導體晶圓上回 填一犧牲層之截面視圖； 第九圖所示爲依照本發明技術於一半導體晶圓上進 行熱製程後之截面視圖； 第十圖所示爲依照本發明技術於一半導體晶圓上蝕 刻此犧牲層後之截面視圖； 第十一圖所示爲依照本發明技術於一半導體晶圓上 I虫刻掺雜石夕層後之截面視圖； 第十二圖所示爲依照本發明技術於一半導體晶圓上 形成0/N /◦介電層後之截面視圖； 第十三A圖所示爲依照本發明技術於一〇/ N /〇介電 層上形成一導體層之截面視圖； 第十三B圖爲半導體晶圓之俯視圖。 圖號對照説明： 1 0半導體底材 13 懸浮閘極層 15控制閘極層 1 7淺溝渠隔離區 2 0半導體晶圓 24 氮化矽層 2 8 溝渠隔離區 1 2二氧化矽層 1 4絶緣層 1 6主動區 2 2墊氧化層 26主動區 3 0，3 2氧化矽層 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ▼裝--------訂---------. 517351 A7 B7 五、發明說明（ 34間壁隙 3 6穿隧二氧化矽層 3 8非晶矽或多晶矽層4 0氮化矽層 42氧化矽層 44懸浮閘極 46〇N〇介電層 48多晶矽層 5 0字元線 發明詳細説明：_ 在不限制本發明之精神及應用範園之下，以下即以 -實施例，介紹本發明之實施；熟悉此領域技藝者，在： 解本發明之精神後，當可應用本發明之製程方法於各種不 同（快閃記憶體製程上，來消除傳統上，由於懸浮閉極層 與王動區間，至少需使用兩面不 ,A ^ U <先罩來分别形成，以 致於在進行光罩對準時常發生 ^ n 玎+錯玦（缺點。同時，本 發明足快閃記憶體結構，在 ^ τ ^ 』彺4犧牲快閃記憶體總面積情 /下，裢升皤净閘極層和控制閘極 士甘叫、、七 Η丄臀間的耦合面積，以增 加其間 < 交連電容。本發明 實施例。 。用田不僅限於以下所述之 一如發明背景所述，當在 下，Α%、,、 Γ外加電壓爲定値之情況 爲b加綠、序閘極層上之電屢 iT a 4 、 FG ) ’可以增加懸浮閘 極層和控制閘極層間之交連電 1T a . ,. ♦運成，亦即增加懸浮閘 極層和控制閘極層間之面積。 f 寸，使得锊、、至問打叫从/、 一由於微影蝕刻有其極限尺 丁 便仔感/予閘極間彼此之分隖π命 刀1^距離有其臨限値。且當元^ 17351 A7 V. Description of the invention (complex field: The present invention relates to a kind of flash memory production), and more particularly to a kind of flash memory with self-align Re: The consumer cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs printed more and more powerful computer microprocessors, and the data calculations performed by the software became larger and larger. Of course, the memory requirements were even higher. Therefore, The development of higher accumulation means the production of larger capacity memory. In the late 1980s, Intei developed the same structure with Electrically Erasable Programmable ROM (EEPROM). "Flash memory, (Flash memory), because the poor material can be stored multiple times, read and clear, so it has become the fastest-growing new generation of memory. Non-volatile memory, especially flash memory Memory has become increasingly important in various applications. In recent years, the demand for flash memory has gradually increased over other memories. Therefore, how to develop a new generation of flash memory technology And reducing the area of flash memory has become an important issue. The structure of flash memory, W EPR0M, also has stacked gates for control gates and suspension gates. The only difference is that there is a layer of high quality under the suspension gates. Thin layer of tunneling dioxide. When the program is written, the hot electron will be: (Please read the precautions on the back before filling this page) -------- Order ------ 517351 A7 V. Explanation of the invention () (TUnneling) This thin tunneling silicon dioxide layer enters the EPROM; when the recording technique p is entered into the gate, similar to Taguchi's wiper 11,, as long as the control gate is applied to the negative Cold electron tunneling through thinning preparation * &, the gross pressure can be removed from the suspension chamber to the source by expulsion-emulsified silicon layer. ..... The structure of the flash memory body is the same as EE: PR〇m The mechanism for erasing by memory cells is different from EEPR0M. 豊 = EEPR0M is much smaller; at the same time, the data ratio is much faster than about 20 minutes of exposure to ultraviolet light. Therefore, it can be seen The flash memory is a combination of the advantages of Ep and eep. As shown in the first figure, the flash memory is manufactured according to the previous technology. The memory body includes a photoresist pattern (not shown in the figure) on the P-type semiconductor substrate 10, and the foot movement region 16 is formed. Next, a dry etching method is used to form a recessed semiconductor wafer with a depth of about 300_45. Shallow trench isolation (STI) of 0 nm. Then the photoresist pattern is removed and a stacked gate structure is formed thereon. The stacked gate includes a tunneling silicon oxide layer 12 suspended Gate layer i 3. After the thin tunneling silicon dioxide layer 12 and the suspended gate layer 3 are formed, an insulating layer 14 of silicon oxide / silicon nitride / stone oxide (ON) is formed, and a control gate layer 15 is then formed. Among them, when forming the floating gate layer 13, its position needs to be defined by another photomask. Therefore, in the traditional process technology, at least two photomasks are usually required to form the floating gate layer 13 and the active region 16. It is assumed that when the voltage V is applied to the control gate layer 15 and the voltage of the semiconductor substrate 10 is set to 0, since the semiconductor substrate i 〇 and the suspended gate layer i 3 are used, the Chinese paper standard (CNS) applies to this paper size. A4 specifications (210 X 297 mm) Γ Please read the notes on the back before filling out this page} Order --------- Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 517351 A7 ____________________ _______ B7 Wisdom of the Ministry of Economy Printed by the Consumer Cooperative of the Property Bureau. V. Invention Description (Capacitance order and bar between the control gate layer 15 and ^ + Capacitance Coupling, so the voltage (Vfg) applied to the floating idler layer i3 ) Can be calculated from the following formula: c + c. ^ In the above formula, Cl is the capacitance between the semiconductor substrate 10 and the suspended gate layer 13 and the capacitor. The cross-arm capacity between the C2 suspended interlayer 13 and the control idler layer i5. When the flash memory process technology reduces the channel length to 0-18 "m, or even 0.13am, the previous flash memory system process that does not use Self-align technology will suffer The problem of the alignment between the levitation layer 13 and the active area 16. And, on the other hand, for flash memory in which a pantograph is injected from a source into a floating gate, the floating closed electrode can cover more source areas or the thinner the silicon dioxide tunnel layer 12, the more The programming speed of Yushi, however, reducing the thickness of the tunneling silicon dioxide layer 12 will cause a problem of data storage time. On the other hand, when the applied voltage is fixed, in order to uniformly increase the floating gate layer 13 Voltage (Vfg) to achieve the tunneling silicon dioxide layer current at the minimum applied voltage. The increase of c's valley can be used to cause the applied voltage to fall on the floating gate layer: 'That is to increase the connection between the floating gate layer 13 and the control gate layer 15 (please read the precautions on the back before filling this page), install -------- order ----- this The paper size applies the Chinese National Standard (CNS) A4 specification (21 × χ297 mm) 517351 A7 V. Description of the invention (product. However, due to the lithographic etching has its limit size, Junto, J. Bell suspended gate layers between each other The separation distance has its limit. Therefore, if you want to increase the area to increase The capacitance of 2 is limited by the threshold, which also requires the use of a larger area of shallow trench isolation 1 17 ', which instead enlarges the entire flash memory area. Although' conventionally 'the wall gap process is used to overcome lithography The limit size of 已 has further reduced the separation distance between the floating gate layers. However, because it still needs to use lithographic touch, it is still limited in reducing the total memory area. Therefore, how to solve the floating gate layer 13 and The problems between the active area M and increasing the capacitance of C without increasing the entire flash memory area have become the theta 2 issues faced by today's flash memory system technology. The purpose and summary of the flawed invention: (Please read the precautions on the back before filling out this page), the equipment is printed and signed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs in the above background of the invention, formed by traditional technology. Because the suspension gate layer and the active section have at least two identical masks to shape & respectively, when the mask is aligned = more accurate control, the purpose of the present invention is to use = Flash memory system procedures to solve the above problems.玎 +, another purpose of the present invention is to provide a kind of process of suspended closed-polar layer process, which does not sacrifice flash memory.-/, Γ Soaring suspension sluice The paper size is applicable to China National Standard (CNS) A4 (21〇X 297 public meals) Order --------- preparation- III _ 517351 A7 B7 V. Description of the invention (coupling capacity between the electrode layer and the control gate layer. To increase the electrical connection between them α The process method disclosed in the present invention is used to form an isolation on a semiconductor substrate: c3 (the step is the first moving zone. Record the shallow trench isolation zone in the shape of :: off zone to isolate The main area is re-formed-a layer of oxidized stone is formed on the shallow ^ shallow trench isolation surface of the depression. An anisotropic dry contact is used to engrav the wall between the oxygen region and the surface of the wafer to form a gap. Thermal oxidation is used. ^ Already formed on the surface of the active area layer, and then formed on the surface of the isolation zone that penetrates with the dioxide and the stone. The shallow trench trench—the nitrided stone layer is formed here. Polycrystalline stone layer covered with nitride stone layer oxygen = nitriding with thermally emulsified enamel solution M " .oxidizing = The nitride stone layer and the oxygen-cut layer are completed to form a __ sequence, forming an oxide stone layer, and a polycrystalline silicon doped anode is formed on the 0N0 dielectric layer as a second electrical layer, and then in%: The engraving method forms the stacked gate structure into sub-lines, and finally completes the invention by the traditional ion implantation with the impurity region as the source and the drain. 1 The required flash doped in this way is completed. The lithography process of the memory is suspended, so it does not need to use the same active mask as the traditional technique. At least two different masks are required. = = Polarity often occurs in the polar layer. And the suspension of the present invention Engraving: This paper size is in accordance with Chinese National Standard (CNS) A4 specification (21〇χ 297 mm 517351 A7 B7. V. Description of the invention Only the structure, the surface of the build-up and the coupling of the interlayer stratified dynode to the gate control system and the channel-level electrical connection between the increase and decrease of the overall surface of the overall memory of the memory quickly lost. Tolerable I said below the simple diagram: For example, the easy-to-read companion of the easy-to-read companion, Xu Xuan, and the later situation _ Figures and descriptions of the previous 6V 6 and clear, according to the details of this example, according to the T view The circle of the truncation, day 00ί The semi-flash of the guide is one of the quick maps. The view of the map is cut by k. The second channel is shallowly formed. The round crystal guide is half. 1 Figure Zhao Yiyi is shown in Figure 3. The third round shallow formed upper circular crystal guide half 1 is cut off from the visual plane of this figure by Ju Jiming, and this picture is shown in Figure 4. The fourth groove is carved into k Divided by a deep circular crystal guide half-Yu Shu; technical view of the surface (please read the precautions on the back before filling out this page)-order ------ the fifth line of a total of 1 into graphics Upper Round Crystal Guide 1 Yu Shu ·, Technical Photo Monthly View this photo as shown in the layered print of the layered dielectric dielectric Ministry of Intellectual Property Bureau of the Intellectual Property Bureau Employee Consumption Cooperative Printed Sixth-The first etching of the upper round crystal guide- Yu Shuming issued this photo according to the instructions After the view is cut, the layer dielectric layer W mesh S seventh tunnel 1 is formed into a round crystal; the volume guide is cut on the half of the surface, the technology layer is bright, and the mixed photo is taken as a copy. Paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 517351 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () Figure 8 shows a semiconductor device according to the technology of the present invention. A cross-sectional view of a sacrificial layer backfilled on a wafer; FIG. 9 shows a cross-sectional view after performing a thermal process on a semiconductor wafer according to the technology of the present invention; and FIG. 10 shows a semiconductor wafer according to the technology of the present invention. A cross-sectional view after the sacrificial layer is etched; FIG. 11 is a cross-sectional view after I-etching a doped stone layer on a semiconductor wafer according to the technology of the present invention; FIG. 12 is a view according to the present invention A cross-sectional view after a 0 / N / ◦ dielectric layer is formed on a semiconductor wafer by technology; FIG. 13A shows a cross-section of a conductive layer formed on a 10 / N / 0 dielectric layer according to the technology of the present invention. View Three B picture shows a plan view of a semiconductor wafer. Comparative description of drawing numbers: 1 0 semiconductor substrate 13 floating gate layer 15 control gate layer 1 7 shallow trench isolation area 2 0 semiconductor wafer 24 silicon nitride layer 2 8 trench isolation area 1 2 silicon dioxide layer 1 4 insulation Layer 1 6 Active area 2 2 Oxide layer 26 Active area 3 0, 3 2 Silicon oxide layer The paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the notes on the back before filling (This page) ▼ Install -------- Order ---------. 517351 A7 B7 V. Description of the invention (34 wall gaps 3 6 tunneling silicon dioxide layer 3 8 amorphous silicon or Polycrystalline silicon layer 40 silicon nitride layer 42 silicon oxide layer 44 suspended gate 46oN0 dielectric layer 48 polycrystalline silicon layer 50 word line invention Detailed description: _ Without limiting the spirit and application of the invention, The following is an example to introduce the implementation of the present invention. Those skilled in the art will, after understanding the spirit of the present invention, apply the process method of the present invention to various (flash memory system processes) to eliminate the traditional On the other hand, due to the suspended closed polar layer and the Wang moving interval, at least two sides need to be used. A ^ U < first cover to form separately, so that ^ N 玎 + 玦 (disadvantages) often occur when performing photomask alignment. At the same time, the present invention has a sufficient flash memory structure. At the expense of ^ τ ^ 彺 彺 4, the total area of the flash memory is sacrificed. The coupling area between the gate electrode layer and the control gate electrode is called, to increase the cross-connection capacitance between them. The embodiment of the present invention. The field of use is not limited to one of the following, as described in the background of the invention, At the moment, when the applied voltage of Α% ,,, Γ is fixed, the voltage on the sequence gate layer is b plus green, iT a 4, FG) 'It can increase the cross-connection power between the floating gate layer and the control gate layer 1T a.,. ♦ Operation, that is, increasing the area between the suspended gate layer and the control gate layer. f inch, so that 锊 ,, to ask to call from /, one, due to the lithographic etching has its limit ruler feel / Yu gate between each other π life knife 1 ^ distance has its limit 且.
本紙張尺度顧_ gg^(CNS)A4職⑵G (請先閱讀背面之注音？事項再填寫本頁) ，裝--------訂----Gu gg ^ (CNS) A4 post G (please read the phonetic on the back? Matters before filling out this page), install -------- order ----
•1 I n n I 备· 五、發明說明（） 牛由0·18μηι再降至〇13μιη或更小，勢必要採取另 :種快閃記憶體結構來解決上述之問題。因此，本發明即 疋 '.十對上述之問題提供—利用淺溝渠隔離的製程中多製 造一些隸合面積之剞# 士、丄 1 _ -I筱万法，以達到增加懸浮閘極層和控 制閘極層間之交連電容之目的。 、由於快閃記憶體之製程包含許多已知的技術，例如爲 人所热知的微影遮罩和蝕刻製程，因此許多步驟將此 詳述。 纟明的細節内容可參表圖示來加以詳細説明。如 弟一圖所π (橫截面示意圖，首先，纟一半導體晶圓… 如矽晶圓)20之上表面以熱氧化製程形成墊氧化声以， 以緩和接著沉積之氮化石夕層24的應力。接著，：光阻圖 案（未圖示）定義主動區26。接著，以乾式敍刻法來形成 -凹入半導體晶圓内深約綱·45〇謂之溝渠隔離區 。先去除光阻圖案（未圖示），之後，再以化學氣相沉積 :，沉積另-氧化矽層30。並塡滿溝渠隔離區Μ。次以 ，化石夕層24爲終止層進行化學機械研磨製程。隨後，如 第二圖所示以以熱磷酸蝕刻氮化矽層2 4。再以η ρ :容液 蝕刻墊氧化層22。上述之溝渠隔離區28亦可以區域氧 化法形成之場氧化層代替之。 隨後，爲達到本發明之增加懸浮閑極層和控制閑極層 間之耦合面積。如第四圖所示之橫截面示意圖。利用一氟 化碳（CF4)電漿來執行氧化矽層3〇之選擇性乾式蝕刻， 10 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 丄 7351 五 經濟部智慧財產局員工消費合作社印製 A7 B7 替明說明（） 以除去部分之氧化矽層3 0，來形成一凹陷之淺溝渠隔離 區。触刻的冰度約爲2 〇 〇至4 0 0 n m，端視所欲增力^之舞 淳閘極層和控制閘極層間之耦合面積。 如第五圖所示，接著於主動區2 6和凹陷之淺溝渠隔 離區28之表面上沈積—層共形（c〇nf〇rmai)的介電層， 其中該介電層必須與矽層具有高蝕刻選擇比。介電層3 2 —般爲氧化梦層32,其厚度約爲400至1000埃。接著， 參閱第六圖，覆蓋有氧化矽層3 2之晶片，將被放入乾蝕 刻機，以非等向性的蝕刻方式（Ariis〇tr〇pic Etch)，形成 如第六圖所示之間壁隙（Spacer)34。進行如傳統閘極間 壁隙之蝕刻。此步驟，主要是利用乾蝕刻之非等向性，將 大邵分沈積在晶片上之氧化矽層3 2，以其所沈積之厚度 爲基準來加以去除，因爲位於主動區26側壁上之氧化矽 層3 2厚度較其他部分爲高，因此在非等向性乾蝕刻後， 邵分位於主動區2 6側壁上之氧化矽層3 2將不會完全被 去除，形成如第六圖所示之間壁隙（Spacer)34。 接著請爹考第七圖所示之橫截面示意圖，一氧化石夕 層在主動區26之表面上形成以作爲穿隧二氧化石夕層36。 在一實施例中，此穿隧二氧化矽層36是利用氧氣環境在溫 度800到100(TC之間熱生長氧化物而形成。並且此穿2 二氧化矽層3 6之厚度可以經由壓力和時間的控制而輕易 的到達所需之厚度，在一實施例中，穿隧二氧化矽層3 6 之厚度大約在80至100埃之間。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I— ft---------裝--------訂--------- (請先閱讀背面之注音？事項再填寫本頁) 517351 A7 五、 經濟部智慧財產局員工消費合作社印製 發明說明（ 、、仍參閱第七圖，接著一非晶石夕或多晶石夕層^以共行 〈万法沈積在晶圓之表面。非晶梦或多晶發層Μ可利用傳 統之化學氣相沉積法(CVD)而形成，㈣也可利用其它的 已知方法加以形成。此一掺雜之非晶矽或多晶石夕層38厚度 約爲200到綱埃之間。在快閃記憶體中，此非晶石夕或多 晶矽層38因爲未和其它的導體連接而稱爲懸浮閘極。同時 此懸浮閘極可用來儲存電荷。 再’人參閱第七圖，在非晶矽或多晶矽層3 8形成之 後，利用N型或P型雜質進行離子植入到此非晶石夕或多晶 矽層38之中。在一較佳實施例中，植入能量約在5至3〇 kV之間，植入之劑量則约爲ΐχι〇ΐ8至m〇2i㈣3。 凊參考第八圖所示之橫截面示意圖，再重新以化學氣 相儿積法（CVD ) ’沈積—氮化矽層4〇於凹陷之淺溝渠 同離區中作爲犧牲層，接著再以蝕刻法或化學機械研磨法 (Chermcal Mechanical P〇lish，CMp)，將超出溝渠 之部分去㉟。使用氮化石夕作爲回塡材料最主要之原因是因 爲氮化矽層具有很好夕P ^ & /、，很奵芡抗虱化性，以於其後之氧化製程 中’不會形成氧化石夕層於其上。 、請參考第九圖所示之橫截面示意圖。以高溫之熱氧 化法形成厚约1 〇 〇至3 〇 〇埃之氧化矽層4 2。由於氮化 矽層具^很好之抗氧化性，因此不會形成氧化矽層42於其 上接著，明爹考第十圖所示之橫截面示意圖，例如可以 使用熱磷酸溶液把氮化矽層4〇蝕刻掉。 12 本紙張尺度剌t關家鮮（CNS)A4規格(210^7^3---'—:- (請先閱讀背面之注意事項再填寫本頁) · i-i ϋ ϋ mmKMm ϋ ϋ 一 讎 am ιημ a·^ w 517351 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明（） 請參考第十一圖所示之橫截面示意圖。利用沈積於 多晶矽層3 8上之氧化矽層4 2爲罩幕，以非等向性的名虫 刻方式（Anisotropic Etch)，將未被氧化石夕層42所覆蓄 之多晶矽層進行非等向性的乾蝕刻，形成彼此分離之释浮 閘極4 4。此時所形成之懸浮閘極4 4已自對準於主動區 26 ’換句話説，使用本發明之方法於形成懸浮閘極斗4 時，並不像傳統製程般，需再進行一道微影製程，因此可 消除懸浮閘極44與主動區26間之對準錯誤問題。接著， 再將沈積於多晶矽層38上之氧化矽層42移除，此移除 之方法可以乾蝕刻法或利用氫氟酸溶液進行。 凊參考弟十二圖所示之橫截面示意圖。接著以氧化 層-氮化層-氧化層（〇N〇）的方式形成一介電層46。广 〇N〇的製程中，係先以高溫的熱氧化製程先形成〇n〇= 電層46之底層氧化矽層。此底層氧化矽層之厚度最好在；1 約40至120埃之間。接著再次利用傳統之低ς二學 沉積法（LPCVD)將氮化矽層沉積於底層氧化發層之上，並 再以熱氧化或類似之方法將頂層氧化矽層形成於氮化矽層 之上而構成完整之0Ν0介電層46。此氮化矽層^厚度田 好在大約60- 120埃之間，而頂端氧化矽層之厚瑕 2 0 - 8 0埃之間。 、爲 請參考第十三Λ圖所示之橫截面示意圖。_導触 48在ΟΝΟ介電層46之上形成。此導體層48也以傳：增 化學氣相沉積法（CVD)或者其它適當之方法所形成。广& 13 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------•裝--------^---------§ (*請先閱讀背面之注意事項再填寫本頁) 517351 A7 五 、發明說明（） 實施例中，其形成厚度大约在1G⑽_3嶋埃之間。導體層 48乃選自摻雜多晶石夕、摻雜非晶石夕或石夕化金屬層。立中 此矽化金屬層可由摻雜夕$ 0 、 此 、^ ，雅（多印矽和矽化鎢所組成。此導體 層48亦可稱爲控制閘極，用來控制資料之存取。 仍請參照第十三A圖所示之橫截面示意圖。接著， 使用-覆蓋處預定字元線之光阻圖案（圖中未展示出）覆 蓋所有區域來定義出字元線，並利用傳統之钱刻方法將多 晶矽層48加以触刻而形成字元線5〇,如第十三b圖所 示。第十三B圖示對應沿b-b，方向所視之俯視圖，其中 圖號50代表所定義出之字元線。 然後仍請參考第十三B圖所示沿b_b,的的俯視圖。 以另一曝露源極/汲極區之光阻圖案（圖中未展示出）， 於主動區26内定義出源極/汲極區。再施以n+ (若爲n 型基板則爲< P+)離子佈植，n型雜質是選自神和^ 組成的族群之一。能量和劑量分别約爲2〇_6〇keV和/ 1〇14至1 X 1〇16 /cm2。最後去除光阻圖案，#完成本 程0 Γ請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 隙 壁 間 有 具極方：製 7 製ς由來本旁 體罩由兩 Q般4經之 記：藝之，6 勺 成 ， 1 2 h 技同面 快幵統不方區 準來傳面一動 對法如兩另主 自方會用。於 之之不使形於 明明並需情由 發發此少之， 本本因至誤構 用，，錯結 利程間準體 下 有 具 程 不 並 浮所 懸别程 於分 述需極 成 成 完 於製區對憶些 由影fe生記這 ， 微主發閃， 點用與常快34 優使層而之 冒裝--------訂---------^9, 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公f ) ^7351 A7. ^-------B7 — 五、發明說明（） 間壁隙34主要是用來降低主動區26與懸浮閘極44間之 又連電容。 本發明之懸浮閘極44具有凸起之結構，他是利用蝕 刻溝渠隔離區28來達成，所以若欲提升懸浮閘極層和控 制閘極層間的耦合面積，僅需增加蝕刻深度，因此可在不 羲牲決閃e己憶體總面積情形下，增加其間之交連電容。 、 如熟悉此技術之人員所瞭解的，以上所述僅爲本發明 <較佳實施例而已，並非用以限定本發明之申請專利範 ，;、凡其它未脱離本發明所揭示之精神下所完成之等效： 欠或修飾，均應包含在下述之申請專利範圍内。 Γ請先閱讀背面之注意事項再填寫本頁)• 1 I n n I Preparation · V. Description of the invention () From 0 · 18μηι to 〇13μιη or smaller, it is necessary to adopt another flash memory structure to solve the above problems. Therefore, the present invention is to provide the above-mentioned problems.—Using a shallow trench isolation process to make more subordinate areas. 士 ， 1 _ -I Xiaowan method, in order to increase the suspension gate layer and The purpose of controlling the interconnection capacitance between the gate layers. 2. Since the flash memory manufacturing process includes many known technologies, such as the lithography masking and etching processes, which are well-known, many steps will detail this. You can refer to the table for details. As shown in Figure 1 (a cross-sectional view, first, a semiconductor wafer ... such as a silicon wafer), a pad oxidation sound is formed by a thermal oxidation process on the upper surface of the wafer 20 to relieve the stress of the subsequently deposited nitride layer 24. . Next, a photoresist pattern (not shown) defines the active area 26. Then, a dry engraving method is used to form a trench isolation region deep in the semiconductor wafer, which is about 45 ° deep. The photoresist pattern (not shown) is removed first, and then a chemical vapor deposition is performed to deposit another silicon oxide layer 30. And filled the trench isolation area M. Secondly, the chemical-mechanical polishing process is performed with the fossil evening layer 24 as a stop layer. Subsequently, as shown in the second figure, the silicon nitride layer 24 is etched with hot phosphoric acid. Then, the pad oxide layer 22 is etched with η ρ: the liquid holding capacity. The trench isolation region 28 described above may also be replaced by a field oxide layer formed by a regional oxidation method. Subsequently, in order to achieve the present invention, the coupling area between the suspended idler layer and the control idler layer is increased. A schematic cross-sectional view as shown in the fourth figure. Carbon monoxide (CF4) plasma is used to perform selective dry etching of the silicon oxide layer 30. 10 paper sizes are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm). 7351 Intellectual Property of the Ministry of Economic Affairs Bureau employee consumer cooperatives printed A7 and B7 instructions for Mingming () to remove a part of the silicon oxide layer 30 to form a recessed shallow trench isolation area. The engraved ice degree is about 2000 to 4000 nm, depending on the coupling area between the gate and control gate layers. As shown in the fifth figure, a layer of conformal (confomrma) dielectric layer is deposited on the surface of the active area 26 and the recessed shallow trench isolation area 28. The dielectric layer must be in contact with the silicon layer. With high etching selectivity. The dielectric layer 3 2 is generally an oxide dream layer 32 and has a thickness of about 400 to 1000 Angstroms. Next, referring to the sixth figure, the wafer covered with the silicon oxide layer 32 will be put into a dry etcher, and an anisotropic etching method (Ariis〇tr〇pic Etch) will be formed, as shown in the sixth figure. Between the wall gap (Spacer) 34. Etching is performed like a conventional gap between gates. In this step, the non-isotropic nature of dry etching is used to deposit the silicon oxide layer 32 on the wafer, which is removed based on the thickness of the deposited silicon oxide layer, because of the oxidation on the sidewall of the active region 26. The thickness of the silicon layer 32 is higher than that of other parts. Therefore, after the anisotropic dry etching, the silicon oxide layer 32 located on the side wall of the active area 26 will not be completely removed, as shown in the sixth figure. Between the wall gap (Spacer) 34. Next, please refer to the schematic cross-sectional view shown in the seventh figure. The oxide layer is formed on the surface of the active region 26 as the tunneling oxide layer 36. In one embodiment, the tunneling silicon dioxide layer 36 is formed by thermally growing oxides using an oxygen environment at a temperature of 800 to 100 ° C., and the thickness of the tunneling silicon dioxide layer 36 can be reduced by pressure and Time control can easily reach the required thickness. In one embodiment, the thickness of the tunneling silicon dioxide layer 3 6 is about 80 to 100 angstroms. This paper size is applicable to China National Standard (CNS) A4 specifications ( 210 X 297 mm) I— ft --------- Installation -------- Order --------- (Please read the phonetic on the back? Matters before filling out this page ) 517351 A7 V. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed an invention description (,, still refer to the seventh figure, and then an amorphous or polycrystalline layer) ^ Surface. The amorphous dream or polycrystalline layer M can be formed by conventional chemical vapor deposition (CVD), and rhenium can also be formed by other known methods. This doped amorphous silicon or polycrystalline stone The thickness of the evening layer 38 is about 200 to gangue. In the flash memory, the amorphous stone or polycrystalline silicon layer 38 is not connected to other conductors. It is a floating gate. At the same time, this floating gate can be used to store charges. Referring to the seventh figure, after the amorphous silicon or polycrystalline silicon layer 38 is formed, the N-type or P-type impurities are used to implant into the amorphous. Shi Xi or polycrystalline silicon layer 38. In a preferred embodiment, the implantation energy is about 5 to 30 kV, and the implantation dose is about ΐχι〇ΐ8 to m〇2i㈣3. 凊 Refer to the eighth figure The schematic cross-section shown is then deposited by chemical vapor deposition (CVD) '-a silicon nitride layer 40 is used as a sacrificial layer in the recessed shallow trench isolation area, and then etched or chemical mechanically polished The method (Chermcal Mechanical P0lish, CMp) will go beyond the trench. The main reason for using nitride nitride as the material is because the silicon nitride layer has a good quality. ^ &Amp;芡 Anti-lice, so that in the subsequent oxidation process, no oxidized stone layer will be formed on it. Please refer to the schematic cross-section diagram shown in Fig. 9. It is formed by thermal oxidation method with a high temperature to a thickness of about 1 〇 〇 至 300 〇 的 SiO2 层 4。 Because the silicon nitride layer has a very Because of its resistance to oxidation, a silicon oxide layer 42 will not be formed on it. Next, the cross-section diagram shown in Figure 10 of Ming Dao Kao, for example, the silicon nitride layer 40 can be etched away using a hot phosphoric acid solution. 12 This paper Standard 剌 t Guan Jiaxian (CNS) A4 specifications (210 ^ 7 ^ 3 ---'-:-(Please read the precautions on the back before filling out this page) · ii ϋ ϋ mmKMm ϋ ϋ 雠 am ιημ a · ^ w 517351 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention () Please refer to the cross-sectional diagram shown in Figure 11. Using the silicon oxide layer 42 deposited on the polycrystalline silicon layer 38 as a mask, the polycrystalline silicon layer not covered by the oxidized stone layer 42 is anisotropic in the anisotropic Etch method (Anisotropic Etch). Anisotropic dry etching forms floating gates 4 4 which are separated from each other. The suspended gate 44 formed at this time has been self-aligned to the active region 26. In other words, when the method of the present invention is used to form the suspended gate bucket 4, it is not like the traditional process, and another lithography is required. Therefore, the problem of misalignment between the floating gate 44 and the active area 26 can be eliminated. Then, the silicon oxide layer 42 deposited on the polycrystalline silicon layer 38 is removed, and the removal method can be performed by a dry etching method or a hydrofluoric acid solution.凊 Refer to the cross-section diagram shown in Figure 12. A dielectric layer 46 is then formed in the form of an oxide layer-nitride layer-oxide layer (ON). In the manufacturing process of Guangzhou, the first step is to first form the bottom silicon oxide layer of the electrical layer 46 by a high-temperature thermal oxidation process. The thickness of the underlying silicon oxide layer is preferably between 1 and 40 and 120 angstroms. Then, the traditional silicon nitride method (LPCVD) is used to deposit the silicon nitride layer on the bottom oxide layer again, and then the top silicon oxide layer is formed on the silicon nitride layer by thermal oxidation or the like. A complete ON0 dielectric layer 46 is formed. The thickness of this silicon nitride layer is between about 60-120 angstroms, and the thickness of the top silicon oxide layer is between 20 and 80 angstroms. Please refer to the schematic diagram of the cross section shown in the thirteenth figure. A conductive contact 48 is formed over the ONO dielectric layer 46. The conductor layer 48 is also formed by chemical vapor deposition (CVD) or other appropriate methods.广 & 13 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ------------- • Installation -------- ^ --- ------ § (* Please read the notes on the back before filling out this page) 517351 A7 V. Description of the invention () In the embodiment, its thickness is about 1G⑽_3 嶋. The conductive layer 48 is selected from a doped polycrystalline stone, a doped amorphous stone, or a petrified metal layer. This silicided metal layer can be composed of doped silicon, polysilicon and tungsten silicide. This conductive layer 48 can also be called a control gate, which is used to control data access. Please also Refer to the schematic cross-section diagram shown in Figure 13A. Next, use a photoresist pattern (not shown in the figure) of a predetermined word line at-to cover all areas to define the word line, and use traditional money to engrav Method: The polycrystalline silicon layer 48 is etched to form word lines 50, as shown in Figure 13b. Figure 13B corresponds to a top view viewed along the direction bb, where figure 50 represents the defined Character line. Then still refer to the top view along b_b, shown in Figure 13B. Another photoresist pattern (not shown in the figure) that exposes the source / drain region is defined in the active region 26 Out of the source / drain region, and then implanted with n + (< P + if n-type substrate), n-type impurities are one of the groups selected from the group consisting of God and ^. Energy and dose are about 2 〇_60〇keV and / 1014 to 1 X 1〇16 / cm2. Finally remove the photoresist pattern, # to complete this process 0 Γ Please read the note on the back first Please fill in this page for more details.) The printing of the gap between the printing and printing of the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs has the following formula: System 7 Origin. The side shield is composed of two Qs and 4 classics: Yizhi, 6 spoons, 1 2 h The technical support team will not be able to pass the information to each other. It will be used as if the two other parties are using it. It does not make it obvious and needs to be issued in the absence of circumstances. The book is misused, and there is a process that is inconsistent with the standard process. The process must be extremely accurate in detail. Finished in the production area to remember some of this by the shadow fe, remember that the micro-master flashed, and the use of 34 and the courier layer of the fast and posing as a -------- order --------- ^ 9, 4 This paper size applies to China National Standard (CNS) A4 (210 X 297 male f) ^ 7351 A7. ^ ------- B7 — V. Description of the invention () The wall gap 34 is mainly used This reduces the connection capacitance between the active area 26 and the floating gate 44. The floating gate 44 of the present invention has a convex structure, which is achieved by etching the trench isolation region 28, so if the coupling area between the floating gate layer and the control gate layer is to be increased, only the etching depth needs to be increased. Under the circumstance that the total area of the body has been determined, increase the cross-link capacitance between them. 2. As understood by those familiar with this technology, the above are only the preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all others that do not depart from the spirit disclosed by the present invention Equivalents completed below: Omissions or modifications shall be included in the scope of patent application described below. Γ Please read the notes on the back before filling this page)
· ·1_·1 I im§ 1 ϋ* · ϋ i^i n «Βϋ I 經濟部智慧財產局員工消費合作社印製· · 1_ · 1 I im§ 1 ϋ * · ϋ i ^ i n «Βϋ I Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs