JPH10247692A - Nonvolatile storage element - Google Patents
Nonvolatile storage elementInfo
- Publication number
- JPH10247692A JPH10247692A JP9048644A JP4864497A JPH10247692A JP H10247692 A JPH10247692 A JP H10247692A JP 9048644 A JP9048644 A JP 9048644A JP 4864497 A JP4864497 A JP 4864497A JP H10247692 A JPH10247692 A JP H10247692A
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- Prior art keywords
- oxide film
- film
- nitride
- nitride film
- nonvolatile memory
- Prior art date
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- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＭＯＮＯＳ（Meta
l-Oxide-Nitride-Oxide-Semiconductor)構造の不揮発性
記憶素子に関する。TECHNICAL FIELD The present invention relates to a MONOS (Meta
The present invention relates to a nonvolatile memory element having an l-Oxide-Nitride-Oxide-Semiconductor structure.
【０００２】[0002]
【従来の技術】図３に示すように、ＭＯＮＯＳ構造の不
揮発性記憶素子は、半導体基板１０１表面側の素子分離
領域１０２で分離された活性領域１０３に配置される。
この不揮発性記憶素子は、半導体基板１０１の表面層の
ソース１０４−ドレイン１０５間の上部に半導体基板１
０１側から順に、トンネル酸化膜１０６、窒化膜１０
７、上層酸化膜１０８を積層させ、さらに上層酸化膜１
０８上にゲート電極１０９を設けた構成になっている。
この上層酸化膜１０８は、正孔のトンネリングを防止で
きる程度の膜厚を有している。2. Description of the Related Art As shown in FIG. 3, a nonvolatile memory element having a MONOS structure is disposed in an active region 103 separated by an element isolation region 102 on the surface side of a semiconductor substrate 101.
This nonvolatile memory element is provided on the semiconductor substrate 101 on the surface layer of the semiconductor substrate 101 between the source 104 and the drain 105.
01 side, the tunnel oxide film 106 and the nitride film 10
7. The upper oxide film 108 is laminated, and the upper oxide film 1
08 and a gate electrode 109 is provided.
The upper oxide film 108 has such a thickness that hole tunneling can be prevented.
【０００３】上記構成のＭＯＮＯＳ構造の不揮発性記憶
素子では、ゲート電極１０９に正電圧を印加すると、電
子がトンネル酸化膜１０６を通過して窒化膜１０７側に
注入される。そして、トンネル酸化膜１０６−窒化膜１
０７界面及び窒化膜１０７−上層酸化膜１０８界面に存
在する捕獲準位に電子が蓄積される。一方、ゲート電極
１０９に負電圧を印加した場合には、上記捕獲準位に蓄
積された電荷が再びトンネル酸化膜１０６を通過して半
導体基板１０１に放出される。以上のように、書き込み
消去の動作にともなう電荷の注入及び放出は、トンネル
酸化膜１０６を介して行われる。また、上層酸化膜１０
８によって、ゲート電極１０９から窒化膜１０７側に余
分な正孔が注入されることが防止される。In the nonvolatile memory element having the MONOS structure described above, when a positive voltage is applied to the gate electrode 109, electrons pass through the tunnel oxide film 106 and are injected into the nitride film 107 side. Then, tunnel oxide film 106-nitride film 1
Electrons are accumulated at the trap level existing at the interface 07 and the interface between the nitride film 107 and the upper oxide film 108. On the other hand, when a negative voltage is applied to the gate electrode 109, the electric charge accumulated in the trap level passes through the tunnel oxide film 106 again and is discharged to the semiconductor substrate 101. As described above, the injection and release of the charge accompanying the write / erase operation are performed via the tunnel oxide film 106. The upper oxide film 10
8 prevents extra holes from being injected from the gate electrode 109 to the nitride film 107 side.
【０００４】[0004]
【発明が解決しようとする課題】近年、半導体装置の高
集積化にともない素子構造の微細化が進展している。こ
のため、上記構成の不揮発性記憶素子においては、半導
体基板表面に対する捕獲準位の配置面積が縮小され、蓄
積可能な電荷量を維持することが困難になってきてい
る。これは、不揮発性記憶素子における信号量（記憶機
能）を低下させる要因になっている。In recent years, as the integration of semiconductor devices has increased, the element structure has been miniaturized. For this reason, in the nonvolatile memory element having the above configuration, the area of the trap level with respect to the surface of the semiconductor substrate is reduced, and it becomes difficult to maintain the amount of charge that can be stored. This causes a reduction in the signal amount (storage function) in the nonvolatile memory element.
【０００５】[0005]
【課題を解決するための手段】本発明は上記課題を解決
するためになされた不揮発性記憶素子である。すなわ
ち、本発明の不揮発性記憶素子はＭＯＮＯＳ構造の不揮
発性記憶素子において、トンネル酸化膜と上層酸化膜と
の間に設けられる窒化膜は少なくとも２層の積層構造で
あり、これらの窒化膜間には、酸化膜が設けられている
ことを特徴としている。そして、窒化膜間に配置される
酸化膜は、正孔がトンネリング可能な膜厚を有している
こととする。SUMMARY OF THE INVENTION The present invention is a nonvolatile storage element for solving the above-mentioned problem. That is, in the nonvolatile memory element according to the present invention, in the nonvolatile memory element having the MONOS structure, the nitride film provided between the tunnel oxide film and the upper oxide film has a laminated structure of at least two layers, and between these nitride films. Is characterized in that an oxide film is provided. The oxide film disposed between the nitride films has a thickness that allows holes to tunnel.
【０００６】上記不揮発性記憶素子によれば、半導体基
板とゲート電極との間に半導体基板側から順に、トンネ
ル酸化膜、窒化膜、酸化膜、窒化膜、上層酸化膜が積層
される。このことから、半導体基板とゲート電極との間
には、酸化膜−窒化膜界面が４面設けられることにな
る。このため、形成面積が同一の従来構造の不揮発性記
憶素子と比較して、捕獲準位に蓄積可能な電荷量が２倍
になる。また、窒化膜間の酸化膜はトンネル酸化膜であ
ることから、ゲート電極への電圧の印加によって電子及
び正孔がこの酸化膜を通過する。したがって、上記各捕
獲順位に電荷が蓄積されることになり、不揮発性記憶素
子に蓄積可能な電荷量が従来の約２倍に増加する。ま
た、上記不揮発性記憶素子では、窒化膜は３層以上の積
層構造でも良く、積層数の増加にともなって酸化膜−窒
化膜界面の面数が増加し、蓄積可能な電荷量も増加す
る。According to the nonvolatile memory element, a tunnel oxide film, a nitride film, an oxide film, a nitride film, and an upper oxide film are sequentially stacked between the semiconductor substrate and the gate electrode from the semiconductor substrate side. From this, four interfaces between the oxide film and the nitride film are provided between the semiconductor substrate and the gate electrode. For this reason, the amount of charge that can be stored in the trap level is doubled as compared with the nonvolatile memory element having the same formation area and the conventional structure. Since the oxide film between the nitride films is a tunnel oxide film, electrons and holes pass through the oxide film when a voltage is applied to the gate electrode. Therefore, charges are accumulated in each of the above-mentioned capture orders, and the amount of charges that can be accumulated in the non-volatile memory element is increased about twice as compared with the conventional case. In the nonvolatile memory element, the nitride film may have a laminated structure of three or more layers. As the number of laminated layers increases, the number of oxide-nitride film interfaces increases, and the amount of charge that can be stored increases.
【０００７】[0007]
【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて説明する。尚、前述の従来技術と同一の構成
要素については、同一符号を付して説明を簡略化もしく
は省略するものとする。Embodiments of the present invention will be described below with reference to the drawings. Note that the same components as those in the above-described related art are denoted by the same reference numerals, and description thereof will be simplified or omitted.
【０００８】図１は、本発明を適用した不揮発性記憶素
子における実施の形態を示す図である。この不揮発性記
憶素子と従来の技術で説明したＭＯＮＯＳ構造の不揮発
性記憶素子との異なるところは、トンネル酸化膜１０６
と上層酸化膜１０８との間の窒化膜が酸化膜を挟んだ２
層構造になっているところにある。すなわち、本実施の
形態で示す不揮発性記憶素子は、半導体基板１０１上に
下層から順にトンネル酸化膜１０６、第１窒化膜２０
１、酸化膜２０２、第２窒化膜２０３、上層酸化膜１０
８を配置してなる。ここで、上記酸化膜２０２は、トン
ネル酸化膜であることとする。そこで本実施の形態で
は、トンネル酸化膜１０６を下層トンネル酸化膜１０６
とし、酸化膜２０２を中間トンネル酸化膜２０２とす
る。FIG. 1 is a diagram showing an embodiment of a nonvolatile memory element to which the present invention is applied. The difference between this nonvolatile memory element and the nonvolatile memory element having the MONOS structure described in the prior art is that the tunnel oxide film 106
Between the oxide film and the upper oxide film 108
It has a layer structure. That is, in the nonvolatile memory element described in this embodiment, the tunnel oxide film 106, the first nitride film 20
1, oxide film 202, second nitride film 203, upper oxide film 10
8 are arranged. Here, the oxide film 202 is a tunnel oxide film. Therefore, in the present embodiment, the tunnel oxide film 106 is
The oxide film 202 is referred to as an intermediate tunnel oxide film 202.
【０００９】図２は、上記不揮発性記憶素子の製造手順
の一例を示す工程図である。以下にこの図を用いて上記
不揮発性記憶素子の詳細な構成を製造工程順に説明す
る。先ず、図２（１）に示すように、単結晶シリコンか
らなる半導体基板１０１の表面側にＬＯＣＯＳ法により
素子分離領域１０２を形成する。その後、イオン注入及
び活性化熱処理を行うことによって、半導体基板１０１
の表面側にウェル拡散層を形成したり、しきい電圧調整
用の不純物を導入し、半導体基板１０１表面側の導電型
及び不純物濃度の調整を行う。FIG. 2 is a process chart showing an example of a procedure for manufacturing the above-mentioned nonvolatile memory element. The detailed configuration of the nonvolatile memory element will be described below in the order of manufacturing steps with reference to FIG. First, as shown in FIG. 2A, an element isolation region 102 is formed on a surface side of a semiconductor substrate 101 made of single crystal silicon by a LOCOS method. After that, by performing ion implantation and activation heat treatment, the semiconductor substrate 101
A well diffusion layer is formed on the surface of the semiconductor substrate 101, impurities for adjusting the threshold voltage are introduced, and the conductivity type and impurity concentration on the surface of the semiconductor substrate 101 are adjusted.
【００１０】次に、図２（２）に示すように、半導体基
板１０１の表面を熱酸化処理することによって、当該半
導体基板１０１の露出表面層に酸化シリコンからなる下
層トンネル酸化膜１０６を成長させる。この下層トンネ
ル酸化膜１０６は、電子と共に正孔がトンネリング可能
であり、かつ半導体基板１０１側からこの下層トンネル
酸化膜１０６をトンネリングした電子、正孔がそのまま
保持される程度の膜厚であることとし、２ｎｍ〜３ｎｍ
程度の膜厚に成膜する。Next, as shown in FIG. 2B, a lower tunnel oxide film 106 made of silicon oxide is grown on the exposed surface layer of the semiconductor substrate 101 by subjecting the surface of the semiconductor substrate 101 to thermal oxidation treatment. . The lower tunnel oxide film 106 is capable of tunneling holes together with electrons, and has such a thickness that electrons and holes tunneled from the lower tunnel oxide film 106 from the semiconductor substrate 101 side are retained as they are. 2 nm to 3 nm
The film is formed to a thickness of about
【００１１】次いで、図２（３）に示すように、下層ト
ンネル酸化膜１０６上に、ＣＶＤ法によって第１窒化膜
２０１を成膜する。この第１窒化膜２０１の膜厚は、不
揮発性記憶素子を作動させる際の電源電圧によって設定
される。ここでは、上記電源電圧が３Ｖ程度であること
とし、第１窒化膜２０１を５ｎｍ〜２０ｎｍ程度の膜厚
で成膜する。Next, as shown in FIG. 2C, a first nitride film 201 is formed on the lower tunnel oxide film 106 by a CVD method. The thickness of the first nitride film 201 is set by a power supply voltage when operating the nonvolatile memory element. Here, the power supply voltage is about 3 V, and the first nitride film 201 is formed to a thickness of about 5 nm to 20 nm.
【００１２】しかる後、この第１窒化膜２０１の表面を
熱酸化処理することによって、当該第１窒化膜２０１の
表面層に中間トンネル酸化膜２０２を成長させる。この
中間トンネル酸化膜２０２の膜厚は、電子と共に正孔が
トンネリング可能な膜厚であることとし、１．０ｎｍ〜
２．２ｎｍ程度の膜厚に形成する。Thereafter, by subjecting the surface of the first nitride film 201 to thermal oxidation treatment, an intermediate tunnel oxide film 202 is grown on the surface layer of the first nitride film 201. The thickness of the intermediate tunnel oxide film 202 is such that holes can be tunneled together with electrons, and is 1.0 nm to 1.0 nm.
It is formed to a thickness of about 2.2 nm.
【００１３】次に、この中間トンネル酸化膜２０２上
に、ＣＶＤ法によって第２窒化膜２０３を成膜する。こ
の第２窒化膜２０３の膜厚は上記第１窒化膜２０１と同
様に設定され、５ｎｍ〜２０ｎｍ程度の膜厚で成膜す
る。その後さらに、この第２窒化膜２０３の表面を熱酸
化処理することによって、当該第２窒化膜２０３の表面
層に上層酸化膜１０８を成長させる。この上層酸化膜１
０８の膜厚は、正孔のトンネリングが不可能な膜厚であ
ることとし、４ｎｍ〜５ｎｍ程度の膜厚に形成する。Next, a second nitride film 203 is formed on the intermediate tunnel oxide film 202 by a CVD method. The thickness of the second nitride film 203 is set in the same manner as the first nitride film 201, and is formed to a thickness of about 5 nm to 20 nm. Thereafter, the surface of the second nitride film 203 is further subjected to a thermal oxidation treatment, whereby the upper oxide film 108 is grown on the surface layer of the second nitride film 203. This upper oxide film 1
The film thickness of 08 is such that hole tunneling is impossible, and is formed to a thickness of about 4 nm to 5 nm.
【００１４】次に、図２（４）に示すように、上層酸化
膜１０８上にＣＶＤ法によって多結晶シリコン膜１０９
ａを成膜する。その後、ここでは図示を省略したレジス
トパターンを多結晶シリコン膜１０９ａ上に形成し、こ
のレジストパターンをマスクに用いたエッチングによっ
て、多結晶シリコン膜１０９ａをパターニングする。こ
れによって、多結晶シリコンからなるゲート電極１０９
を形成する。その後、引き続き上層酸化膜１０８、第２
窒化膜２０３、中間トンネル酸化膜２０２、第１窒化膜
２０１及び下層トンネル酸化膜１０６をパターニングす
る。Next, as shown in FIG. 2D, a polycrystalline silicon film 109 is formed on the upper oxide film 108 by CVD.
a is formed. Thereafter, a resist pattern (not shown) is formed on the polycrystalline silicon film 109a, and the polycrystalline silicon film 109a is patterned by etching using the resist pattern as a mask. Thereby, the gate electrode 109 made of polycrystalline silicon is formed.
To form Thereafter, the upper oxide film 108 and the second
The nitride film 203, the intermediate tunnel oxide film 202, the first nitride film 201, and the lower tunnel oxide film 106 are patterned.
【００１５】次いで、図２（５）に示すように、ゲート
電極１０９の両脇における半導体基板１０１の表面層に
不純物を導入することによって、ソース１０４及びドレ
イン１０５を形成する。Next, as shown in FIG. 2 (5), a source 104 and a drain 105 are formed by introducing impurities into the surface layer of the semiconductor substrate 101 on both sides of the gate electrode 109.
【００１６】以上によって、下層トンネル酸化膜１０６
と上層酸化膜１０８との間に、酸化膜（中間トンネル酸
化膜２０２）を挟んで２層の窒化膜（第１窒化膜２０１
と第２窒化膜２０３）を設けてなるＭＯＮＯＳ構造の不
揮発性記憶素子を得ることができる。As described above, the lower tunnel oxide film 106
Between the first oxide film 108 and the upper oxide film 108 with an oxide film (intermediate tunnel oxide film 202) therebetween.
And the second nitride film 203) can be obtained.
【００１７】しかる後、ここでは図示を省略したが、例
えば、ゲート電極１０９の側壁から下層トンネル酸化膜
１０６の側壁にかけて絶縁性のサイドウォールを形成
し、さらにソース１０４やドレイン１０５に接続される
配線を形成することによって不揮発性記憶装置を完成さ
せる。この不揮発性記憶装置は、７Ｖ〜８Ｖ程度のゲー
ト電圧を印加することで電荷の注入が行われる。Thereafter, although not shown here, for example, an insulating side wall is formed from the side wall of the gate electrode 109 to the side wall of the lower tunnel oxide film 106, and furthermore, wiring connected to the source 104 and the drain 105 To complete the non-volatile memory device. In this nonvolatile memory device, charges are injected by applying a gate voltage of about 7 V to 8 V.
【００１８】上記構成の不揮発性記憶素子では、半導体
基板１０１とゲート電極１０９との間に半導体基板１０
１側から順に、下層トンネル酸化膜１０６、第１窒化膜
２０１、中間トンネル酸化膜２０２、第２窒化膜２０
３、上層酸化膜１０８が積層される。このため、半導体
基板１０１とゲート電極１０９との間には、酸化膜−窒
化膜界面が４か所設けられる。そして、ゲート電極１０
９に電圧を印加することによって、半導体基板１０１中
の電荷が下層トンネル酸化膜２０１及び中間トンネル酸
化膜２０２を通過し、上記４か所の各捕獲順位に上記電
荷が蓄積される。この際の蓄積可能な電荷量は、形成面
積が同一の従来構造の不揮発性記憶素子と比較して約２
倍になる。したがって、不揮発性記憶素子における記憶
機能（信号量）を向上させることが可能になる。ただ
し、電荷の注入時間は、各捕獲順位を満たすのに十分な
時間に設定することとする。In the nonvolatile memory element having the above structure, the semiconductor substrate 10 is provided between the semiconductor substrate 101 and the gate electrode 109.
In order from the first side, the lower tunnel oxide film 106, the first nitride film 201, the intermediate tunnel oxide film 202, and the second nitride film 20
3. An upper oxide film 108 is stacked. Therefore, between the semiconductor substrate 101 and the gate electrode 109, there are provided four oxide film-nitride film interfaces. Then, the gate electrode 10
By applying a voltage to 9, the charges in the semiconductor substrate 101 pass through the lower tunnel oxide film 201 and the intermediate tunnel oxide film 202, and the charges are accumulated in each of the four capture orders. The amount of charge that can be stored at this time is about 2 times smaller than that of a nonvolatile memory element having a conventional structure having the same formation area.
Double. Therefore, the storage function (signal amount) of the nonvolatile storage element can be improved. However, the charge injection time is set to a time sufficient to satisfy each capture order.
【００１９】尚、上記実施の形態では、下層トンネル酸
化膜１０６と上層酸化膜１０８との間の窒化膜を第１窒
化膜２０１と第２窒化膜２０３との２層構造にした。し
かし、この窒化膜は３層以上の多層にしても良く、この
場合には中間トンネル酸化膜も２層以上に多層化され
る。このように、窒化膜が３層以上に多層化された不揮
発性記憶素子では、上記実施の形態の不揮発性記憶素子
よりもさらに蓄積可能な電荷量を増加させることが可能
になる。In the above embodiment, the nitride film between the lower tunnel oxide film 106 and the upper oxide film 108 has a two-layer structure of the first nitride film 201 and the second nitride film 203. However, the nitride film may have a multilayer structure of three or more layers. In this case, the intermediate tunnel oxide film has a multilayer structure of two or more layers. As described above, in the nonvolatile memory element in which the nitride film is multilayered into three or more layers, it is possible to further increase the amount of charge that can be stored compared to the nonvolatile memory element of the above embodiment.
【００２０】[0020]
【発明の効果】以上説明したように本発明の不揮発性記
憶素子によれば、トンネル酸化膜と上層酸化膜との間の
窒化膜を酸化膜を挟んだ多層構造にしたことによって、
半導体基板−ゲート電極間における酸化膜−窒化膜界面
の捕獲順位を増加させることが可能になる。このため、
微細化が進んだ不揮発性記憶素子における蓄積可能な電
荷量を増加させ、信号量（記憶機能）を向上させること
が可能になる。As described above, according to the nonvolatile memory element of the present invention, the nitride film between the tunnel oxide film and the upper oxide film has a multilayer structure with the oxide film interposed therebetween.
It is possible to increase the order of capture at the interface between the oxide film and the nitride film between the semiconductor substrate and the gate electrode. For this reason,
The amount of charge that can be stored in the miniaturized nonvolatile memory element can be increased, and the signal amount (storage function) can be improved.
【図１】本発明を適用した不揮発性記憶素子の構造図で
ある。FIG. 1 is a structural diagram of a nonvolatile memory element to which the present invention is applied.
【図２】本発明を適用した不揮発性記憶素子の製造工程
図である。FIG. 2 is a manufacturing process diagram of a nonvolatile memory element to which the present invention is applied.
【図３】従来の不揮発性記憶素子の構造図である。FIG. 3 is a structural diagram of a conventional nonvolatile memory element.
１０１ 半導体基板 １０６ 下層トンネル酸化膜
（トンネル酸化膜） １０８ 上層酸化膜 １０９ ゲート電極 ２０１ 第１窒化膜（窒化膜） ２０２ 中間トンネ
ル酸化膜（酸化膜） ２０３ 第２窒化膜（窒化膜）Reference Signs List 101 semiconductor substrate 106 lower tunnel oxide film (tunnel oxide film) 108 upper oxide film 109 gate electrode 201 first nitride film (nitride film) 202 intermediate tunnel oxide film (oxide film) 203 second nitride film (nitride film)
Claims (2)
半導体基板側から順にトンネル酸化膜、窒化膜、上層酸
化膜を設けてなる不揮発性記憶素子において、 前記窒化膜は、少なくとも２層の積層構造であり、 前記各窒化膜間には、酸化膜が設けられていること、 を特徴とする不揮発性記憶素子。1. A nonvolatile memory element comprising a tunnel oxide film, a nitride film, and an upper oxide film provided between a semiconductor substrate and a gate electrode in this order from the semiconductor substrate side, wherein the nitride film has at least two layers. A nonvolatile memory element having a laminated structure, wherein an oxide film is provided between the respective nitride films.
て、 前記窒化膜間に設けられている酸化膜は、正孔がトンネ
リング可能な膜厚を有していること、 を特徴とする不揮発性記憶素子。2. The nonvolatile memory element according to claim 1, wherein said oxide film provided between said nitride films has a film thickness capable of tunneling holes. Storage element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9048644A JPH10247692A (en) | 1997-03-04 | 1997-03-04 | Nonvolatile storage element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9048644A JPH10247692A (en) | 1997-03-04 | 1997-03-04 | Nonvolatile storage element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10247692A true JPH10247692A (en) | 1998-09-14 |
Family
ID=12809083
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9048644A Withdrawn JPH10247692A (en) | 1997-03-04 | 1997-03-04 | Nonvolatile storage element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10247692A (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100414211B1 (en) * | 2001-03-17 | 2004-01-07 | 삼성전자주식회사 | Non-volatile memory device having a metal-oxide-nitride-oxide-semiconductor gate structure and fabrication method thereof |
| JP2005260197A (en) * | 2004-03-11 | 2005-09-22 | Hynix Semiconductor Inc | Semiconductor element and its manufacturing method |
| JP2007184380A (en) * | 2006-01-05 | 2007-07-19 | Micronics Internatl Co Ltd | Nonvolatile memory cell, memory array having the same, and method of operating the cell and the array |
| JP2008004934A (en) * | 2006-06-22 | 2008-01-10 | Macronix Internatl Co Ltd | Stacked nonvolatile memory device, and method for fabricating the same |
| JP2008098602A (en) * | 2006-10-13 | 2008-04-24 | Macronix Internatl Co Ltd | Laminated thin film transistor type nonvolatile memory device and method of manufacturing thereof |
| US7592666B2 (en) | 2003-06-04 | 2009-09-22 | Kabushiki Kaisha Toshiba | Semiconductor memory |
| JP2009289823A (en) * | 2008-05-27 | 2009-12-10 | Renesas Technology Corp | Nonvolatile semiconductor storage device |
| JP2010062387A (en) * | 2008-09-04 | 2010-03-18 | Toshiba Corp | Nonvolatile semiconductor storage device |
| WO2010087265A1 (en) * | 2009-01-28 | 2010-08-05 | 株式会社 東芝 | Nonvolatile semiconductor storage device and method for manufacturing same |
| US8264028B2 (en) | 2005-01-03 | 2012-09-11 | Macronix International Co., Ltd. | Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays |
| EP3002779A3 (en) * | 2014-09-30 | 2016-05-04 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
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1997
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100414211B1 (en) * | 2001-03-17 | 2004-01-07 | 삼성전자주식회사 | Non-volatile memory device having a metal-oxide-nitride-oxide-semiconductor gate structure and fabrication method thereof |
| US7592666B2 (en) | 2003-06-04 | 2009-09-22 | Kabushiki Kaisha Toshiba | Semiconductor memory |
| JP2005260197A (en) * | 2004-03-11 | 2005-09-22 | Hynix Semiconductor Inc | Semiconductor element and its manufacturing method |
| US8264028B2 (en) | 2005-01-03 | 2012-09-11 | Macronix International Co., Ltd. | Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays |
| JP2007184380A (en) * | 2006-01-05 | 2007-07-19 | Micronics Internatl Co Ltd | Nonvolatile memory cell, memory array having the same, and method of operating the cell and the array |
| JP2008004934A (en) * | 2006-06-22 | 2008-01-10 | Macronix Internatl Co Ltd | Stacked nonvolatile memory device, and method for fabricating the same |
| JP2008098602A (en) * | 2006-10-13 | 2008-04-24 | Macronix Internatl Co Ltd | Laminated thin film transistor type nonvolatile memory device and method of manufacturing thereof |
| JP2009289823A (en) * | 2008-05-27 | 2009-12-10 | Renesas Technology Corp | Nonvolatile semiconductor storage device |
| JP2010062387A (en) * | 2008-09-04 | 2010-03-18 | Toshiba Corp | Nonvolatile semiconductor storage device |
| WO2010087265A1 (en) * | 2009-01-28 | 2010-08-05 | 株式会社 東芝 | Nonvolatile semiconductor storage device and method for manufacturing same |
| JP2010177323A (en) * | 2009-01-28 | 2010-08-12 | Toshiba Corp | Nonvolatile semiconductor memory device and manufacturing method thereof |
| US9391084B2 (en) | 2014-06-19 | 2016-07-12 | Macronix International Co., Ltd. | Bandgap-engineered memory with multiple charge trapping layers storing charge |
| EP3002779A3 (en) * | 2014-09-30 | 2016-05-04 | Renesas Electronics Corporation | Method of manufacturing semiconductor device |
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