JPH05129630A - Production of nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide the production of a nonvolatile semiconductor storage device which has a charge trap film which has a deep trap level and that allows excellent dielectric strength. CONSTITUTION:A tunnel oxide film 12 is formed on a silicon substrate 11 and after accumulating a polysilicon film on the film 12, the polysilicon film is thermally oxidized. Thus, a charge trap film 15 whose silicon grain 13 in the polysilicon film is covered with a thermal oxide film 14 is manufactured. After forming a conductive layer on the charge trap film 15, the tunnel oxide film 12, the charge trap film 15 and the conductive layer are patterned and a gate structure is provided. Impurity is ion-implanted using the gate structure as a mask and a drain and a source diffused layers 21 and 22 are formed by self- alignment. Since the thermal oxide film 14 allows excellent insulation, the charge trap film 15 is allowed to have high dielectric strength. The silicon grain 13 covered by the thermal oxide film 14 has a deep trap level and excellent signal charge maintaining characteristic is allowed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device having a charge trap film.

[0002]

2. Description of the Related Art Conventionally, as a non-volatile semiconductor memory device that stores information by holding charges in a charge trap film, a memory cell having a MNOS (Metal-Nitride-Oxide-Semiconductor) structure or a MONOS (Metal-Oxide) structure. -Nitride-
A memory cell having an Oxide-Semiconductor structure is known.

As shown in FIG. 10, a memory cell having a MNOS structure has a gate structure formed by laminating a tunnel oxide film 2, a silicon nitride film 3 and a gate electrode 4 on a P-type silicon substrate 1, for example. In this structure, a drain diffusion layer 5 and a source diffusion layer 6 which are N ⁺ regions are formed in the substrate on both sides of this gate structure. Further, as shown in FIG. 11, the memory cell having the MONOS structure has a gate structure in which a tunnel oxide film 7, a silicon nitride film 8, a top oxide film 9 and a gate electrode 10 are laminated.

Each of these memory cells uses the silicon nitride films 3 and 8 as charge trap films for accumulating signal charges, and a positive high voltage is applied to the gate electrodes 4 and 10 in writing. As a result, electrons are tunneled through the tunnel oxide films 2 and 7 from the channel region of the substrate 1 and injected into the silicon nitride films 3 and 8 to be trapped. Here, the silicon nitride films 3 and 8 as charge trap films are formed by a CVD (Chemical Vapor Deposition) method, and specifically, SiH ₄ gas or Si
It is generated by reacting H ₂ Cl ₂ gas and NH ₃ gas in an atmosphere of 700 to 900 ° C.

[0005]

However, the conventional example having such a structure has the following problems. That is, since the silicon nitride film as the charge trap film has a shallow trap level, charges are easily detrapped, and therefore, there is a problem that the signal charge retention property is poor.

[0006] Therefore, the present applicant has previously proposed that a film in which conductive silicon and insulating silicon dioxide are mixed (so-called S
A semiconductor memory device using an i-rich oxide film as a charge trap film is proposed (Japanese Patent Application No. 210610/1990).
issue). Since the Si-rich oxide film has a deep level in principle, it has excellent signal charge retention characteristics. However,
The previously proposed Si-rich oxide film is used for sputtering and C
Since it is formed by the VD method, there is a problem that it is difficult to control the insulating property between silicon crystal grains (hereinafter referred to as silicon grains) in the oxide film. In particular, when the Si-rich oxide film is thinned in order to reduce the write voltage, it is difficult to secure the dielectric strength voltage, and the electrons injected into the Si-rich oxide film at the time of writing the signal charge are directly released to the gate electrode. The inconvenient phenomenon of being lost sometimes occurred.

The present invention has been made in view of such circumstances, and is a method for manufacturing a nonvolatile semiconductor memory device having a deep trap level and a charge trap film having an excellent withstand voltage. Is intended to provide.

[0008]

The present invention has the following constitution in order to achieve such an object. That is, the present invention relates to a method for manufacturing a non-volatile semiconductor memory device in which information is stored by holding charges in a charge trap film, a step of forming an insulating film on a semiconductor substrate, and a step of forming polysilicon on the insulating film. Depositing a film, covering the silicon crystal grains in the polysilicon film with a thermal insulating film, depositing a conductive layer on the polysilicon film,
Patterning the insulating film, the polysilicon film, and the conductive layer to form a gate structure; and using the gate structure as a mask to form drain and source diffusion layers in a substrate on both sides of the gate structure by self-alignment And a process.

[0009]

According to the present invention, it is possible to obtain a semiconductor memory device having a charge trap film in which silicon crystal grains in a polysilicon film are covered with a thermal insulating film. The thermal insulating film that covers the silicon crystal grains in the polysilicon film has better film quality than the insulating film obtained by sputtering or the CVD method.
Has high withstand voltage. Moreover, since the silicon crystal grains covered with the thermal insulating film have a deep trap level, a nonvolatile semiconductor memory device having excellent signal charge retention characteristics can be obtained.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a structure of a charge trap film according to an embodiment of the present invention. In the figure, reference numeral 11 is a silicon substrate, and a tunnel oxide film 12 as an insulating film is formed on the silicon substrate 11. On this tunnel oxide film 12, there are a large number of silicon grains 13 functioning as a center for trapping signal charges, and these silicon grains 13 serve as a thermal insulating film, for example, the thermal oxide film 1.
They are covered with 4 and insulated from each other. A thermal silicon nitride film may be used instead of the tunnel oxide film 12 and the thermal oxide film 14 described above.

Since a thermal insulating film such as a thermal oxide film or a thermal silicon nitride film has a higher insulating property than an insulating film formed by sputtering or a CVD method, the silicon grain 13 is
They are well insulated from each other and from the silicon substrate 11 and the gate electrode (not shown) formed on the charge trap film 15. The charge trap film 15
If it is too thin, it may be difficult to secure the insulation even if the silicon grains 13 are covered with the thermal oxide film 14. In such a case, as shown in FIG.
5 may have a multilayer structure.

When a write voltage is applied to the charge trapping film as shown in FIGS. 1 and 2, a depletion layer is generated in the silicon grain 13 and the dielectric constant of the charge trapping film 15 may change. When the dielectric constant of the charge trap film 15 changes, the electric field applied to the tunnel oxide film 12 decreases and the writing efficiency decreases, so that it is necessary to set the writing voltage high, or the potential of the channel surface of the transistor changes. Therefore, there is a disadvantage that the threshold value of the transistor changes. Therefore, it is preferable to suppress the generation of the depletion layer by doping the silicon grains 13 with impurities such as phosphorus to increase the conductivity of the silicon grains 13.

FIG. 3 shows an example of the charge trap film 15 described above.
The nergi band structure is shown. E in the figure₁, E₂Is
Energy band of the tunnel oxide film 12 and the thermal oxide film 14
Do, E ₃Indicates the energy band of silicon grain 13
is doing. Silicon grain 13 and the oxide film 12, 1
The inter-band barrier with 4 is about 3.1 eV. silicon
While the trap level of the nitride film is about 0.3 eV,
The trap level of the charge trap film 15 of the embodiment is deep enough.
Compared to the one using a silicon nitride film as the charge trap film.
It can be understood that all of them have excellent signal charge retention characteristics.
It

An example of a method of manufacturing the above charge trap film will be described below with reference to FIG. First, FIG. 4 (a)
As shown in FIG.
A tunnel oxide film 12 having a thickness of about 00 angstrom is formed.

Next, as shown in FIG. 4B, the reduced pressure C
A thin polysilicon film 16 is deposited on the tunnel oxide film 12 by the VD method. Specifically, SiH ₄ is thermally decomposed in a temperature atmosphere of about 570 ° C. to deposit a polysilicon film 16 of about 600 Å.
It is not preferable to deposit the polysilicon film 16 thickly. Because, in the subsequent thermal oxidation step, the oxygen atoms become grain boundaries (grain boundaries) of the polysilicon film 16.
This is because it becomes difficult to diffuse inward along 16a and the insulation of the silicon grains 13 inside the polysilicon film 16 may become insufficient.

At the initial stage of depositing the polysilicon film 16, nuclei of polysilicon are generated, and the silicon grains 13 are grown around the nuclei by epitaxial growth or migration. Therefore, when the polysilicon film 16 is thin, as shown in FIG. 3B, the grain boundary 16a becomes the polysilicon film 16
Penetrate up and down. This grain boundary 16a is a lattice mismatch surface, and the diffusion rate of oxygen atoms is faster than that inside the silicon grain 13. Therefore, if the oxidation is performed in this state, the oxidation proceeds not only from the upper surface of the polysilicon film 16 but also from the side surface along the grain boundary 16a. As a result, the silicon grains 13 are completely covered with the thermal oxide film 14.

After depositing the polysilicon film 16, next,
As shown in FIG. 4C, POCl ₃ gas is supplied in an atmosphere at a temperature of about 900 ° C. to dope phosphorus into the polysilicon film 16 and increase the conductivity of the polysilicon film 16. The reason for this is as described above.

Next, as shown in FIG.
The silicon grains 13 in the polysilicon film 16 are thermally oxidized by performing wet oxidation in an atmosphere of about ° C.
Thermal oxide film 14 of about 300 Å on the surface
To form. Through the steps up to this point, the charge trap film 15 as described with reference to FIG. 1 is formed.

When the charge trap film 15 having the multi-layer structure as shown in FIG. 2 is formed, as shown in FIG. 4E, after forming the thermal oxide film 14, the thin polysilicon film is formed again. 17 is deposited. Then, after the phosphorus doping step (FIG. 4C) and the thermal oxidation step (FIG. 4D), as shown in FIG. 4F, the charge trap film 1 having a multilayer structure is formed.
Get 5.

FIG. 5 shows a manufacturing method for ensuring the insulation between the silicon grains 13 in the charge trap film 15. That is, FIG. 5A is the charge trap film 15 obtained by the steps of FIGS. 4A to 4D. Here, as shown in FIG. 5B, the thermal oxide film 14 is removed by a diluted HF solution.
Then, as shown in FIG. 5C, the substrate is thermally oxidized again to form a new thermal oxide film 14 a on the surface of the silicon grain 13. As a result, the silicon grains 13 are thinned and the periphery thereof is covered with the thermal oxide film 14a, so that the insulating property between the silicon grains 13 is further enhanced.

When a thermal silicon nitride film is used instead of the tunnel oxide film 12 and the thermal oxide film 14, the silicon substrate 11 or the substrate on which the polysilicon film 16 is deposited is placed in an atmosphere of N ₂ or NH _3. High temperature treatment may be performed inside.

Next, with reference to FIG. 6, the structure of the non-volatile memory using the charge trap film according to the above-described embodiment will be described. This nonvolatile memory is a P-type silicon substrate 1
1 has a gate structure in which a tunnel oxide film 12, a charge trap film 15 and a gate electrode 20 are laminated on each other, and a drain diffusion layer 21 and a source diffusion layer 22 which are N ⁺ regions are formed in the substrate on both sides thereof. ing. The charge trap film 15 is configured as described in FIG. 1 or 2.

Writing / erasing / reading of the signal charges to / from the nonvolatile memory is performed as follows. At the time of writing the signal charge, a positive high voltage is applied to the gate electrode 20 and the channel region 23 is grounded. This allows
Due to the electric field generated between the gate electrode 20 and the channel region 23, the electrons in the channel region 23 have high energy, and some of the electrons are in the tunnel oxide film 1.
2 is tunneled and injected into the charge trap film 15,
It is trapped in the silicon grains 13 in the charge trap film 15. As a result, the threshold value of the nonvolatile memory transistor shifts to the higher side, as shown in FIG.

To erase the signal charges, a positive high voltage is applied to the channel region 23 to generate an electric field in the direction opposite to the direction in which the signal charges are written, whereby the silicon grains 13 are removed.
The electrons trapped in are returned to the channel region 23. As a result, the threshold value of the nonvolatile memory transistor returns to the initial state as shown in FIG.

The signal charge is read out by the voltage V _{S which} is between the threshold value in the initial state and the threshold value after writing shown in FIG.
Is applied to the gate electrode 20 and to the drain diffusion region 21 by applying a positive voltage (for example, about 5 V). In the state where the electrons are trapped in the silicon grain 13, as shown in FIG. 8A, a channel is not formed between the source and the drain and the state becomes non-conductive. This state is read as data "0". Silicon grain 1
8 (b) when electrons are not trapped in 3
As shown in FIG. 5, a channel is formed between the source and the drain, and the channel becomes conductive, and this state is read as data "1".

Next, a method for manufacturing the nonvolatile memory shown in FIG. 6 will be described with reference to FIG. First, LOCOS
After the element region is formed separately on the silicon substrate by the (Local Oxidation of Silicon) method, as shown in FIG. 9A, a tunnel oxide film 12 of about 20 angstrom is formed on the P-type silicon substrate 11. .. And in FIG.
As shown in (b) of FIG.
A charge trap film 15 of about 0 Å is deposited. The method of forming the charge trapping film 15 will be described with reference to FIGS.
Since it is the same as that described above, the description here is omitted.
4000 as a gate electrode on the charge trap film 15
A polysilicon film of about angstrom is deposited, and impurities such as phosphorus are doped to provide conductivity. Next, the tunnel oxide film 12, the charge trap film 15 and the polysilicon film are patterned by photoetching,
A gate structure as shown in FIG. 9C is formed. Using this gate structure as a mask, N type impurities such as arsenic are ion-implanted into the silicon substrate 11 to form the drain diffusion layer 21 and the source diffusion layer 22 by self-alignment.

Although the N-channel non-volatile memory provided with the charge trapping film, which is the subject matter of the present invention, has been described in the above embodiments, the present invention is of course applicable to a P-channel non-volatile memory. Is.

[0028]

As is apparent from the above description, according to the present invention, after forming an insulating film (tunnel insulating film) on a semiconductor substrate and depositing a polysilicon film on this insulating film,
Since the charge trap film is formed by covering the silicon crystal grains in the polysilicon film with a thermal insulation film, the nonvolatile semiconductor has a high withstand voltage and is excellent in signal charge retention characteristics and highly reliable. A storage device can be realized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a structure of a charge trap film according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a structure of a charge trap film having a multilayer structure.

FIG. 3 is a band structure diagram of a charge trap film according to an example.

FIG. 4 is an explanatory diagram of the method for manufacturing the charge trap film according to the example.

FIG. 5 is an explanatory diagram of another embodiment of the method of manufacturing the charge trap film.

FIG. 6 is a cross-sectional view showing a configuration of a nonvolatile memory using a charge trap film according to an example.

FIG. 7 is an explanatory diagram showing a threshold shift state before and after writing in the nonvolatile memory shown in FIG. 6;

8 is an explanatory diagram of a read operation of the nonvolatile memory shown in FIG.

9 is an explanatory diagram of a method of manufacturing the nonvolatile memory shown in FIG.

FIG. 10 is a sectional view showing a structure of a MNOS element according to a conventional example.

FIG. 11 is a cross-sectional view showing the structure of a MONOS element according to a conventional example.

[Explanation of symbols]

 11 ... Silicon substrate 12 ... Tunnel oxide film 13 ... Silicon grain 14 ... Thermal oxide film 15 ... Charge trap film 16, 17 ... Polysilicon film 16a ... Grain boundary 20 ... Gate electrode 21 ... Drain diffusion layer 22 ... Source diffusion layer 23 ... Channel area

Claims (1)

[Claims] 1. A method of manufacturing a non-volatile semiconductor memory device in which information is stored by holding charges in a charge trap film, the method comprising: forming an insulating film on a semiconductor substrate; and forming a polysilicon film on the insulating film. A step of depositing a silicon crystal grain in the polysilicon film with a heat insulating film, a step of depositing a conductive layer on the polysilicon film, and a step of depositing the insulating film, the polysilicon film, and the conductive layer. Patterning to form a gate structure; and using the gate structure as a mask to form drain and source diffusion layers in the substrates on both sides of the gate structure by self-alignment. Of manufacturing a non-volatile semiconductor memory device.