KR100898752B1 - High density semiconductor memory device and method for manufacturing the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a highly integrated semiconductor memory device and a method of manufacturing the same, which are capable of accurately reading data by suppressing generation of leakage current due to high integration of the semiconductor memory device. And a source and drain electrode formed on the channel region and the schottky junction, and a floating gate formed on the substrate of the channel region and composed of a plurality of silicon nano-points. The present invention has an effect of providing a highly integrated semiconductor memory device capable of accurately reading data by suppressing generation of leakage current due to high integration.

Flash memory, short circuit junction, metal silicide

Description

High density semiconductor memory device and manufacturing method thereof {HIGH DENSITY SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a highly integrated semiconductor memory device capable of accurately reading data by suppressing generation of leakage current due to high integration of a semiconductor memory device and a method of manufacturing the same.

Among semiconductor memory devices, flash memory has exploded in the last few years due to the advent of mobile devices such as mobile phones, cameras and MP3s. Continues to attract attention as a storage medium.

1 is a cross-sectional view showing a flash memory according to the prior art.

Referring to FIG. 1, a flash memory according to the related art includes a substrate 100 and a channel region 160 having a source and a drain region 110 formed on both sides of the channel region 160 and the channel region 160. A tunneling dielectric layer 120 formed on the substrate 100 of the substrate 100, a floating gate 130 formed of poly-Si on the tunneling insulating layer 120, and a floating gate 130 on the floating gate 130 A gate dielectric layer 140 and a control gate 150 formed on the gate insulating layer 140 are included. The flash memory having such a configuration applies the phenomenon of changing the threshold voltage of the transistor by injecting or removing charges into the floating gate 130 as a memory operation principle.

However, as the design rule of the semiconductor device decreases recently, the gap between the source and drain regions 110 of the flash memory device is narrowed, and the doping concentration of the channel region 160 and the source and drain regions 110 is reduced. As is increased, the short channel effect (SCE) occurs. In particular, the threshold voltage of the transistor is changed due to the leakage current due to the short channel effect, making it difficult to accurately read data.

In addition, the flash memory device according to the related art uses a trap site formed inside the floating gate 130 to store electric charges, so that there is sufficient space for storing information, that is, a floating gate to secure a large number of trap sites. Since the 130 must be formed thick, there is a problem that makes it difficult to integrate the flash memory device. In addition, the charge trap by the trap site has a problem in that the time for storing information, that is, the retention time is short, because the trap is weak.

In addition, the flash memory device according to the related art uses hot electron injection or FN tunneling in order to inject or remove charges into the floating gate 130. The hot electron injection or FN tunneling is a high voltage. For example, since the process requires a voltage in the range of 14V to 20V, power consumption is large, and the tunneling insulating film (Stress) is applied to the tunneling insulating film 120 during the process of injecting or removing the charge into the floating gate 130. Deterioration of the 120 and data stored in the floating gate 130, that is, the leakage of charge is a problem.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems. The purpose is to provide.

Another object of the present invention is to provide a highly integrated semiconductor memory device and a method of manufacturing the same, which can simplify the manufacturing process of the highly integrated semiconductor memory device.

According to an aspect of the present invention, a highly integrated semiconductor memory device is formed on a substrate, a source and drain electrode forming a channel region and a schottky junction, and is formed on the substrate of the channel region. And a floating gate composed of a plurality of Si-nanodots. The gate insulating layer may further include a gate insulating layer formed on the floating gate. The display device may further include a tunneling insulating layer formed between the substrate of the channel region and the floating gate, and a control gate formed on the floating gate.

The channel region may be formed of silicon, and the source and drain electrodes may be formed of metal silicide. In this case, when the electron is used as a majority carrier, the source and drain electrodes are erbium (Er), ytterbium (Yb), samarium (Sm), yttrium (Y), and gadolium (Gd). It may include any one selected from the group consisting of terbium (Tb) and cerium (Ce), when the hole (hole) using a plurality of carriers, the source and drain electrodes are platinum (Pt), lead (Pb) And iridium (Ir) may include any one selected from the group consisting of.

The silicon nano dot may form a silicon compound as a basal body, and the silicon compound base may include any one selected from the group consisting of silicon oxide, silicon nitride, and silicon carbon.

The substrate may be a bulk silicon substrate or a silicon on insulator (SOI) substrate.

According to another aspect of the present invention, there is provided a method of fabricating a highly integrated semiconductor memory device, the method including: forming a channel region and a source and drain electrode forming a schottky junction with the channel region on a substrate; Forming a tunneling insulating film on the substrate; Forming a floating gate including a plurality of silicon nano dots on the tunneling insulating layer; Forming a control gate on the floating gate and selectively etching the control gate, the floating gate, and the tunneling insulating layer to expose the source and drain electrodes. The method may further include forming a gate insulating layer on the floating gate.

The channel region may be formed of silicon, and the source and drain electrodes may be formed of metal silicide. In this case, when the electron is used as a multi-carrier, the source and drain electrodes are erbium (Er), ytterbium (Yb), samarium (Sm), yttrium (Y), gadolium (Gd), terbium (Tb), and cerium. It can be formed using any one selected from the group consisting of (Ce), when the hole is used as a multi-carrier, the source and drain electrodes are a group consisting of platinum (Pt), lead (Pb) and iridium (Ir) It can be formed using any one selected from.

The silicon nano point may form a silicon compound as a base, and the silicon compound base may be formed as any one selected from the group consisting of silicon oxide, silicon nitride, and silicon carbon.

According to the present invention, since the source and drain electrodes are formed of metal silicide, leakage current is generated between the source and drain electrodes and between the floating gate and the source and drain electrodes as the semiconductor memory device is highly integrated, thereby changing the threshold voltage of the semiconductor memory device. Can be prevented, and through this, it is possible to enable accurate data reading.

In addition, by forming the floating gate with a plurality of silicon nano-points, the present invention can suppress the leakage current of the floating gate due to deterioration of the tunneling insulating film, and can significantly reduce the size of the floating gate and improve the degree of integration. In addition, due to the large charge trapping force of the silicon nano-point, there is an effect of increasing retention time.

In addition, according to the present invention, a silicon compound base for forming a floating gate acts as a gate insulating layer, thereby shortening a process step, thereby reducing the production cost of a semiconductor memory device.

In addition, the present invention can reduce the thickness of the tunneling insulating film by suppressing the occurrence of leakage current due to the high integration of the semiconductor memory device, thereby directing the charge (dirsct tunnelimg) when the charge is injected or removed in the floating gate It can be effective. In this case, when direct tunneling is used to inject or remove charges into the floating gate, the tunneling insulating layer may be improved in durability, an operation speed of the semiconductor memory device may be improved, and an operation voltage may be lowered.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. Also in the figures, the thicknesses of layers and regions are exaggerated for clarity, and if it is said that a layer is on another layer or substrate "it" can be formed directly on another layer or substrate, Alternatively, a third layer may be interposed therebetween. In addition, parts denoted by the same reference numerals throughout the specification represent the same element.

2 is a cross-sectional view illustrating a highly integrated semiconductor memory device according to an embodiment of the present invention.

As shown in FIG. 2, the highly integrated semiconductor memory device of the present invention is formed on a substrate, and source and drain electrodes 220A and channel regions 220B forming a schottky junction with the channel region 220B. And a floating gate 260A formed on the substrate of the substrate and configured of a plurality of silicon nano-points. In addition, the semiconductor device may further include a tunneling insulating film 250 formed between the substrate of the channel region 220B and the floating gate 260A and a control gate 280 formed on the floating gate 260A. The gate insulating layer 270 may be further included on the floating gate 260A.

In this case, the channel region 220B may be formed of silicon, and the source and drain electrodes 220A may be formed of metal silicide. As a result, a Schottky junction may be formed between the channel region 220B formed of silicon and the source and drain electrodes 220A. As such, by forming a schottky junction between the channel region 220B and the source and drain electrodes 220A, a schottky barrier can be formed between the channel region 220B and the source and drain electrodes 220A. Through this, leakage of current between the source and drain electrodes 220A may be suppressed.

Here, when electrons are used as the majority carrier, the source and drain electrodes 220A are materials having a low Schottky barrier for electrons, such as erbium (Er), ytterbium (Yb), samarium (Sm), and yttrium (Y). It can be formed using any one selected from the group consisting of, gadolium (Gd), terbium (Tb) and cerium (Ce). In addition, when holes are used as multiple carriers, the source and drain electrodes use any one selected from the group consisting of a material having a low Schottky barrier for holes, such as platinum (Pt), lead (Pb), and iridium (Ir). Can be formed.

The floating gate 260A formed of a plurality of silicon nano-points may form a silicon compound as a base body 260. In this case, the silicon compound base 260 may be formed of any one selected from the group consisting of silicon oxide, silicon nitride, and silicon carbon, and stores data while charge or injection is injected into the silicon nano point.

Here, since the silicon compound base 260, for example, silicon oxide, silicon nitride, or silicon carbon, is an insulating material, it may function as a gate insulating film.

On the other hand, if the insulating properties between the control gate 280 and the control gate 280 lower structure only by the insulating properties provided by the silicon compound base 260, as shown in the drawing, the control gate 280 and the silicon compound A gate insulating film 270 may be further formed between the base bodies 260.

The control gate 280 is any one selected from the group consisting of a metal material such as polysilicon, tungsten (W) or titanium (Ti), a conductive metal nitride such as titanium nitride, and a metal silicide such as tungsten silicide or titanium silicide It can be formed into a laminated film.

The substrate may be a bulk silicon substrate, and preferably, an SOI substrate is used to reduce leakage current and increase driving current of the highly integrated semiconductor memory device. At this time, the SOI substrate is a support substrate 200 for mechanical support, a buried oxide layer 210 formed on the support substrate 200, a silicon substrate-channel region 220B formed on the buried oxide layer 210. And a region in which the source and drain electrodes 220A are formed.

Here, the thickness of the silicon substrate is preferably formed so that the electric field controlled by the control gate 280 can fully control the channel region 220B. As a result, the thickness of the channel region 220B controlled by the control gate 280 is reduced, and thus the formation of an inversion layer can be very easily controlled, which results in the source and drain electrodes 220A of the semiconductor memory device. There is an effect of reducing the leakage current in the liver.

As described above, according to the present invention, the source and drain electrodes 220A are formed of metal silicide, thereby suppressing the occurrence of leakage current between the source and drain electrodes 220A as the semiconductor memory devices are highly integrated, thereby increasing the threshold voltage of the semiconductor memory devices. It can be prevented from changing, thereby enabling accurate data reading. In addition, since a Schottky barrier is formed between the floating gate 260A and the source and drain electrodes 220A formed of the plurality of silicon nano-points, the leakage current generated between the floating gate 260A and the source and drain electrodes 220A. Can be suppressed.

In addition, the present invention forms the floating gate 260A with a plurality of silicon nano-points, thereby ensuring sufficient charge storage space even when the floating gate 260A is formed in a smaller volume than the conventional floating gate. By greatly reducing the size of the gate 260A, the degree of integration of the semiconductor memory device may be improved.

In addition, in the present invention, even if a short circuit occurs between the floating gate 260A and the source and drain electrodes 220A due to deterioration of the tunneling insulating film 250, only a few silicon nano-points short-circuited are affected. Since the point is not affected, stable device operating characteristics can be obtained. That is, it is possible to maintain a uniform distribution of threshold voltages.

In addition, the present invention traps the charge in the potential well of the silicon nano-point having a high potential barrier, thereby preventing the occurrence of leakage current and increasing the retention time.

In addition, in the highly integrated semiconductor memory device of the present invention, the source and drain electrodes 220A are formed of metal silicide, and the floating gate 260A is formed of a plurality of silicon nano-points, thereby suppressing the occurrence of leakage current. ) Can be formed thinner than the conventional one, for example, 6 nm or less, and when directing or removing electric charges through the floating gate 260A, a direct tunneling method can be used. Lai, "Tunnel oxide and ETOX ^tm flash scaling limitation", in Tech. Dig. of Int`I Nonvolatile Memory Technology Conference (1998), pp. 6-7] When the direct tunneling method is used, the durability of the tunneling insulating layer 250 can be improved, and the operating speed and the operating voltage of the semiconductor memory device can be reduced. This is because direct tunneling is a process requiring a lower voltage, for example, in the range of 3V to 5V, compared to conventional hot electron injection or FN tunneling.

Hereinafter, an embodiment of a method for manufacturing a highly integrated semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings. In the following description of the process, a known technology is not described in the description of the semiconductor device manufacturing method or the related film formation method, which means that the technical scope of the present invention is not limited by these known technologies.

3A through 3D are cross-sectional views illustrating a method of manufacturing a semiconductor memory device in accordance with an embodiment of the present invention.

As shown in FIG. 3A, an SOI including a support substrate 200 for mechanical support, a buried oxide layer 210 formed on the support substrate 200, and a silicon substrate 220 formed on the buried oxide layer 210. Provide a substrate. In this case, a bulk silicon substrate may be used instead of the SOI substrate.

Here, the thickness of the silicon substrate 220 is preferably formed so that the electric field controlled by the control gate to be formed through a subsequent process can fully control the channel region. As a result, the thickness of the channel region controlled by the control gate can be reduced, so that the formation of the inversion layer can be controlled very easily, thereby reducing the leakage current between the source and drain electrodes of the highly integrated semiconductor memory device.

Next, after the sacrificial layer is formed on the silicon substrate 220, the sacrificial layer is selectively etched to form a sacrificial layer pattern 230 that opens an area where the source and drain electrodes are to be formed. In this case, the silicon substrate 220 covered by the sacrificial layer pattern 230 serves as a channel region through a subsequent process (see FIG. 3B).

Next, the metal film 240 is formed on the entire surface of the silicon substrate 220 including the sacrificial film pattern 230. In this case, the metal film 240 is used to form the source and drain electrodes as metal silicide. When the highly integrated memory device of the present invention uses electrons as a multicarrier, the metal film 240 may have a schottky barrier for electrons. Lower materials such as erbium (Er), ytterbium (Yb), samarium (Sm), yttrium (Y), gadolium (Gd), terbium (Tb) and cerium (Ce) In the case where the hole is used as a multiple carrier, it is formed using a material having a low Schottky barrier for the hole, for example, selected from the group consisting of platinum (Pt), lead (Pb), and iridium (Ir). can do.

As shown in FIG. 3B, heat treatment is performed to form the source and drain electrodes 220A with metal silicide. At this time, the heat treatment is to convert the silicon substrate 220 and the metal film 240 to the metal silicide by reacting with each other, rapid thermal treatment method (Rapid Thermai Annealing, RTA), furnace annealing method and laser heat treatment method ( laser annealing) can be carried out using any method selected from the group consisting of: For example, after the metal film 240 is formed of erbium (Er), and then heat-treated at a temperature ranging from 500 ° C. to 600 ° C. using a rapid heat treatment method, the source and drain electrodes 220A may be formed of erbium silicide. have.

Here, the bottom (bottom) of the source and drain electrodes 220A formed of the metal silicide may be reacted for a sufficient time so as to be in contact with the top of the buried oxide layer 210 of the SOI substrate.

Next, the unreacted metal film that is not reacted in the heat treatment process is removed. In this case, the unreacted metal film may be removed by a wet etching method or a dry etching method. Here, when using a wet etching method, a hydrochloric acid (HCl) and nitric acid (HNO ₃₎ is mixed aqua regia (aqua regia) or sulfuric acid (H ₂ SO ₄₎ and hydrogen peroxide (H ₂ O ₂₎ are mixed SPM (sulfuric peroxide mixture) can be removed using a solution, and if dry etching is used, it can be removed using an argon gas sputtering method.

Next, the sacrificial layer pattern 230 is removed.

Through the above-described process, the source and drain electrodes 220A forming the schottky junction with the channel region 220B and the channel region 220B may be formed in the silicon substrate 220.

As shown in FIG. 3C, the tunneling insulating layer 250 is formed on the silicon substrate having the channel region 220B and the source and drain electrodes 220A. In this case, the tunneling insulating film 250 may be formed using various known film forming techniques, and may be formed of a silicon oxide film using thermal oxidation to form an insulating film having excellent quality.

Here, the present invention can form the source and drain electrodes 220A by the metal silicide, and by forming a floating gate to be formed through a subsequent process to a plurality of silicon nano-points, thereby suppressing the occurrence of leakage current, thereby tunneling The thickness of the insulating layer 250 may be reduced.

Next, a floating gate 260A including a plurality of silicon nano-points is formed on the tunneling insulating film 250. In this case, the floating gate 260A may be formed by using the silicon compound as the base body 260, and the silicon compound base body 260 may be formed by any one selected from the group consisting of silicon oxide, silicon nitride, and silicon carbon. .

Hereinafter, a method of forming the floating gate 260A including the silicon compound as the base 260 and the plurality of silicon nano-points will be described in more detail. Here, silicon nitride is used as the silicon compound base 260.

Mixture gas containing argon gas, silicon source gas such as silane gas and nitrogen, such as N ₂ gas or NH ₃ gas, using plasma enhanced chemical vapor deposition (PECVD) By using the silicon nitride as a base body 260 can be grown a plurality of silicon nano-dots dispersed in the silicon nitride (see Fig. 4), the silicon nano-point having a good nano crystal structure inside the silicon nitride. In order to form, it is preferable to control slowly at the growth rate of 1.3 nm / min-1.8 nm / min, for example. To this end, a mixed gas obtained by diluting silicon source gas with argon gas in a range of 1% to 50% is injected into the reaction chamber at a lower flow rate than the gas containing nitrogen, for example, 1 sccm to 50 sccm, and containing nitrogen. The silicon nitride can be grown slowly by controlling the plasma power to 5 W or less while reducing the concentration of the radicals generated by the plasma while injecting a gas into the reaction chamber of 500 sccm or more.

The silicon nano point formed by the above-described method has a better post-treatment process such as heat treatment because the silicon nano crystal structure is superior to the silicon nano point formed by using conventional chemical vapor deposition (CVD). It is not necessary to carry out. (See FIG. 4).

As shown in FIG. 3D, a gate insulating layer 270 is formed on the floating gate 260A. In this case, the gate insulating layer 270 may be formed of a silicon oxide layer using low pressure chemical vapor deposition (LPCVD).

Meanwhile, since the silicon compound base body 260, for example, silicon oxide, silicon nitride, or silicon carbon, is an insulating material, the silicon compound base body 260 may serve as a gate insulating film, and the control gate 280 to be formed through a subsequent process using only the silicon compound base body 260 is provided. If the insulating property between the control gate 280 and the lower structure can be secured, the process of forming the gate insulating film 270 can be omitted.

Next, the control gate 280 is formed on the gate insulating film 270. In this case, the control gate 280 is formed of any one selected from the group consisting of a metal material such as polysilicon, tungsten (W) or titanium (Ti), a conductive metal nitride such as titanium nitride, and a metal silicide such as tungsten silicide or titanium silicide. can do.

Next, after the hard mask pattern is formed on the control gate 280, the control mask 280, the gate insulating layer 270, the silicon compound base 260, and the tunneling are formed using the hard mask pattern as an etch barrier. The insulating layer 250 is etched to expose the silicon substrate in the region where the source and drain electrodes 220A are formed.

Through the above-described process, a highly integrated semiconductor memory device including a source and drain electrode 220A formed of metal silicide and a floating gate 260A formed of a plurality of silicon nano-points may be formed.

As described above, according to the present invention, the silicon compound base 260 for forming the floating gate 260A composed of a plurality of silicon nano-points acts as a gate insulating film, thereby shortening the process steps, thereby providing a semiconductor memory device. The production cost can be reduced.

In addition, according to the present invention, the source and drain electrodes 220A are formed of metal silicide, and thus, between the source and drain electrodes 220A and the source and drain electrodes 220A and the floating gate 260A as the semiconductor memory device is highly integrated. By suppressing leakage current, it is possible to prevent the threshold voltage of the semiconductor memory device from changing, thereby enabling accurate data reading.

In addition, according to the present invention, by forming the floating gate 260A with a plurality of silicon nano-points, the leakage current of the floating gate 260A due to the deterioration of the tunneling insulating film 250 can be suppressed, and the size of the floating gate 260A is reduced. It is possible to improve the density by drastically reducing the. In addition, the retention time may be increased due to the large charge trapping force of the silicon nano-point.

In addition, the present invention can reduce the thickness of the tunneling insulating film 250 by suppressing the occurrence of leakage current due to the high integration of the semiconductor memory device, through which the direct tunneling of the charge when the injection or removal of the charge to the floating gate 260A There is an effect that can be done. Here, when direct tunneling is used to inject or remove charges into the floating gate 260A, the durability of the tunneling insulating layer 250 may be improved, the operating speed of the semiconductor memory device may be improved, and the operating voltage may be lowered.

FIG. 4 is a scanning electron microscopy (SEM) image showing a silicon nano dot and a silicon nitride substrate formed according to an embodiment of the present invention.

Referring to FIG. 4, it can be seen that a plurality of silicon nano-points acting as floating gates 260A are formed in the silicon nitride base body 260. The size of the silicon nano-point is 4.6 nm on average, and the density (density) is 6.0 × 10 ¹¹ / cm ² .

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

1 is a cross-sectional view showing a flash memory according to the prior art.

2 is a cross-sectional view illustrating a highly integrated semiconductor memory device according to an embodiment of the present invention.

3A to 3D are cross-sectional views illustrating a method of manufacturing a highly integrated semiconductor memory device according to an embodiment of the present invention.

Figure 4 is a scanning electron microscope image showing the silicon nano-dots and silicon nitride substrate formed in accordance with an embodiment of the present invention.

   *** Explanation of symbols for main parts of drawing ***

200: support substrate 210: buried oxide layer

220: silicon substrate 220A: source and drain electrodes

220B: channel region 230: sacrificial layer pattern

240: metal film 250: tunneling insulating film

260: silicon compound base material

260A: Floating gate composed of a plurality of silicon nano points

270 gate insulating film 280 control gate

Claims (17)

delete delete delete delete delete delete delete delete delete Forming source and drain electrodes on the substrate, the source and drain electrodes forming a schottky junction with the channel region; Forming a tunneling insulating film on the substrate; Forming a silicon compound basal body including a floating gate including a plurality of silicon nano-points on the tunneling insulating film; Forming a control gate on the silicon compound base; And Selectively etching the control gate, the floating gate, and the tunneling insulating layer to expose the source and drain electrodes; And the silicon nano point is formed using the silicon compound base. The method of claim 10, And forming a gate insulating film on the silicon compound base. The method of claim 10, The silicon nano point is a method of manufacturing a highly integrated semiconductor memory device is grown inside the silicon compound base. The method of claim 12, The silicon compound base is formed of any one selected from the group consisting of silicon oxide, silicon nitride and silicon carbon. The method of claim 10, And the channel region is formed of silicon, and the source and drain electrodes are formed of metal silicide. The method of claim 10, In the case of using electrons in the majority carrier, the source and drain electrodes are erbium (Er), ytterbium (Yb), samarium (Sm), yttrium (Y), gadolium (Gd), terbium (Tb), and cerium (Ce). A method for manufacturing a highly integrated semiconductor memory device formed using any one selected from the group consisting of The method of claim 10, In the case where holes are used as multiple carriers, the source and drain electrodes are formed using any one selected from the group consisting of platinum (Pt), lead (Pb), and iridium (Ir). The method of claim 10, The substrate may be a bulk silicon substrate or a silicon on insulator (SOI) substrate.

Images