JPH10242310A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a stable operation and sufficient charge holding characteristic even if the pattern is finer by introducing N in a silicon oxide film so that the max. concn. is within specified range in the film to form a gate insulation film with little leakage current at low temps. SOLUTION: An n-type impurity-doped polycrystalline Si film 204 is formed on the entire main surface of a p-type semiconductor substrate 201 including a first gate insulation film 203. Next a polycrystalline Si film 205 is formed on the entire main surface of the p-type semiconductor substrate 201 and the Si film 204 and immediately heat-treated in an NH3 atmosphere to introduce N in this film 205 so that the N atom concn. in the film 205 is limited to a range between approximately 2×10<20> and 2×10<21> atoms/cm<3> . This Si oxide 105 is used as a second gate insulation film 205 of nonvolatile memory elements Qe, thereby improving the charge hold characteristic.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and, more particularly, to a technology effective when applied to a semiconductor device having a nonvolatile memory element provided with an insulating film between a floating gate electrode and a control gate electrode. Things.

[0002]

2. Description of the Related Art As a semiconductor device, there is a nonvolatile semiconductor memory device called a flash memory. This flash memory has been attracting attention as a file memory for future small portable information devices because it has excellent portability and shock resistance and can be erased electrically on-board at once.

The flash memory has a memory cell array section in which a plurality of memory cells each having a nonvolatile storage element as one storage unit are arranged in a matrix. The nonvolatile memory element is configured on a main surface of a semiconductor substrate made of single crystal silicon.

The nonvolatile memory element mainly includes a semiconductor substrate, which is a channel forming region, a first gate insulating film, a floating gate electrode (also referred to as a floating gate electrode), a second gate insulating film, and a control gate electrode (control gate electrode). Electrodes), a pair of semiconductor regions (also referred to as impurity diffusion regions) which are a source region and a drain region, and the like. In this nonvolatile memory element, electrons are injected into a floating gate electrode by applying a positive voltage to a control gate electrode with respect to a semiconductor substrate, and 1
[Bit] information (“0” or “1”) is stored. Note that the first gate insulating film refers to a tunnel insulating film provided between the semiconductor substrate and the floating gate electrode. Further, the second gate insulating film refers to an interlayer insulating film provided between the floating gate electrode and the control gate electrode.

In the nonvolatile memory element, each of the floating gate electrode and the control gate electrode is formed of a polycrystalline silicon film, and each of the first gate insulating film and the second gate insulating film is formed of a silicon oxide (SiO ₂ ) film. Is formed. The silicon oxide film as the first gate insulating film is formed by subjecting a main surface of a semiconductor substrate made of single crystal silicon to a thermal oxidation treatment, and the silicon oxide film as the second gate insulating film is formed from a polycrystalline silicon film. It is formed by performing a thermal oxidation treatment on the surface of the floating gate electrode.

[0006] The silicon oxide film formed on the surface of the floating gate electrode made of the polycrystalline silicon film has a lower withstand voltage than the silicon oxide film formed on the main surface of the semiconductor substrate made of single crystal silicon, and has a lower electric charge. Due to poor retention characteristics, in a flash memory of 4 [Mbit] or later, instead of a single-layer silicon oxide film, a silicon oxide film, a silicon nitride (Si ₃ N ₄ ) film, and a silicon oxide film are sequentially stacked. Membrane, so-called ONO ( O xide / N itri
de / O xide) film to form a second gate insulating film. This is because the leak current of the ONO film is smaller than that of the silicon oxide film when the film thickness converted into the silicon oxide film is the same. This technology is described in, for example, IEE Transactions on Electron Devices, Vol. 38, 1991, pp. 386-391 (I
EEE Transaction on Electron Devices, 38 (1
991) pp 386-391).

[0007]

SUMMARY OF THE INVENTION
With the high integration of flash memory, ON is applied to the second gate insulating film.
When an O film is used, a new problem arises.
One is the process temperature due to the miniaturization of nonvolatile memory elements.
It is reduction. The ONO film is usually made of a polycrystalline silicon film.
Thermal oxidation of the surface of the floating gate electrode
Is formed on the lower silicon oxide film.
Growth (LPCVD:LowPressureChemicalVapor
Deposition) method, and then silicon nitride
The surface of the silicon film is thermally oxidized to form an upper silicon oxide film.
And is formed by However, the oxidation of this silicon nitride film
Since a high temperature of 900 ° C or more is required, the source region and drain
Forming the second gate insulating film after forming the gate region
If the LSI (LargeScaleIntegrated Circui
It becomes difficult to form a shallow junction, which is indispensable for miniaturization of t),
This is a factor that hinders high integration of flash memory.
I was

According to only the thermal oxidation method described above, 800 ° C.
It is possible to form the second gate insulating film made of a single-layer silicon oxide film even at a relatively low temperature. However, in this method, as the oxidation temperature is reduced, the thickness of the silicon oxide film becomes thinner at the upper end of the side wall of the floating gate electrode, and there is a problem that the electric field concentration in this portion becomes remarkable and the leak current increases. Was. LPCVD instead of thermal oxidation
A technique has also been proposed in which a single-layer silicon oxide film is formed at a low temperature of about 750 ° C. by a method and applied to a second gate insulating film of a nonvolatile memory element. When the LPCVD method is used, the leakage current of the silicon oxide film can be reduced as compared with the thermal oxidation method. However, the effect is not sufficient, and at present, it is difficult to apply it to a nonvolatile memory element.

Another point is that the second gate insulating film is made thinner. The voltage Vfg applied to the floating gate electrode during the rewriting operation of the nonvolatile memory element is

[0010]

Vfg = C2Vcg / (C1 + C2) (1) Here, Vcg is the applied voltage of the control gate electrode, C1 is the capacity of the first gate insulating film, and C2 is the capacity of the second gate insulating film. In order to efficiently transmit the voltage applied to the control gate electrode to the floating gate electrode and reduce the program voltage, the second gate insulating film is thinned to reduce the C2 voltage.
It is effective to increase. However, in the conventional ONO film, when the upper and lower silicon oxide films have a thickness of 5 nm or less, there is a problem that charges accumulated in the floating gate electrode leak to the control gate electrode, that is, a so-called retention defect becomes apparent. Was. Further, the upper silicon oxide film is formed to have a thickness of 5 [n].
m], it was necessary to form a silicon nitride film of about 10 [nm] or more in order to prevent oxidation of the underlying polycrystalline silicon film which is a floating gate electrode. Therefore, the thickness of the ONO film is reduced to 15 [nm] in terms of a silicon oxide film.
Today, the extent of which is limited and it is becoming difficult to reduce the thickness of the first gate insulating film, development of a new process for forming a second gate insulating film has been expected.

An object of the present invention is to form a gate insulating film having a lower leak current at a lower temperature than a conventional ONO film in a nonvolatile memory element mounted on a semiconductor device, and to achieve a stable operation even when the gate insulating film is finer. And a technique for obtaining sufficient charge retention characteristics. Another object of the present invention is to form a thin gate insulating film in a nonvolatile memory element mounted on a semiconductor device as compared with a case where a conventional ONO film is used, and to reduce a program voltage. It is to provide various technologies.

[0012]

The object of the present invention is to use a silicon oxide film or a laminated film of a silicon oxide film and a silicon nitride film as a second gate insulating film, and to provide the silicon oxide film with a maximum atomic concentration in the film. Is achieved by introducing nitrogen so that the value is approximately 2 × 10 ²⁰ [atoms / cm 3] or more. Further, the maximum nitrogen atom concentration in the silicon oxide film is approximately 2 × 10
It is more preferable that it is ²¹ [atoms / cm3] or less. In addition, the maximum hydrogen atom concentration in the silicon oxide film is set to 5 × 10 ²⁰
If it is set to [atoms / cm3] or less, further effects can be obtained.

The semiconductor device according to the present invention has a silicon oxide film between a first silicon film and a second silicon film thereabove, and nitrogen is introduced into the silicon oxide film. The nitrogen atom concentration is approximately 2 × 10 ²⁰ [atoms / cm3] or more,
Preferably, it is 2 × 10 ²¹ [atoms / cm 3] or less. When the present semiconductor device has a nonvolatile memory element, the first silicon film corresponds to a floating gate electrode, the silicon oxide film corresponds to a second gate insulating film, and the control gate electrode corresponds to a second silicon film. In this case, an n-type impurity such as phosphorus (P) is generally introduced into each of the first silicon film and the second silicon film. By using a silicon oxide film as the second gate insulating film, 15 [n] which was impossible with a conventional ONO film.
m] or less.

The silicon oxide film is formed, for example, by an LPCVD method using monosilane (SiH 4) and nitrous oxide (N ₂ O) as source gases. According to the method, 70
A silicon oxide film can be formed at a low temperature of 0 ° C. to 800 ° C. However, as described above, L
It is difficult to immediately use the silicon oxide film formed by the PCVD method as the second gate insulating film of the nonvolatile memory element. This is because the leakage current of the silicon oxide film is large,
After injecting electrons into the floating gate electrode, when the power is shut off and the device is left unattended, the electrons accumulated in the floating gate electrode leak to the control gate electrode, resulting in charge retention (retention) failure That's why. In addition, since the leakage current is large, when electrons are injected into the floating gate electrode to increase the threshold value of the nonvolatile memory element, the injected electrons escape to the control gate electrode side, and the threshold voltage is sufficiently high. There is also a problem that the value does not increase and a threshold window for writing and erasing cannot be secured. As a result of our research, it has been clarified that the leak current of the silicon oxide film is caused by a defect called an E ′ center existing in the silicon oxide film.

Therefore, in the present invention, the silicon oxide film is heat-treated in an NH3 atmosphere, and the E 'center is terminated with nitrogen atoms to reduce the leak current. The leak current of the silicon oxide film is uniquely determined by the concentration of nitrogen atoms in the silicon oxide film regardless of the process conditions. In order to reduce the leakage current, suppress the retention failure, and secure the threshold window, the maximum nitrogen atom concentration in the silicon oxide film should be approximately 2 × 10 ²⁰ [atoms / cm 3] or more, preferably 2 × 10 ²⁰ [atoms / cm 3]. 10
Must be ²¹ [atoms / cm3] or less. At this time, more nitrogen atoms are present in the upper and lower layers of the silicon oxide film than in the middle layer. In order to obtain the above-mentioned nitrogen atom concentration, annealing in an NH3 atmosphere is performed at 750 [° C.] to 9 ° C.
00 [° C], preferably from 800 [° C] to 850 [° C]
It should be done in. Therefore, it is possible to lower the temperature of the gate insulating film forming process as compared with the conventional ONO film.

Further, when the maximum hydrogen atom concentration in the silicon oxide film is set to 5 × 10 ²⁰ [atoms / cm 3] or less, the present invention is more preferable. This is because hydrogen atoms existing in the silicon oxide film form an electron trap. When hydrogen atoms are present, when rewriting is performed, electrons are accumulated in the second gate insulating film, and the electrons accumulated in the gate insulating film are discharged to the control gate electrode when left untreated, resulting in poor retention. Will happen. In order to reduce the above-mentioned hydrogen atoms, after annealing in an NH3 atmosphere, for example, about 800 [° C.] to 900 [° C.], preferably 85 ° C.
The wet oxidation may be performed at 0 ° C. for a short time.

Further, in the present invention, it is preferable to control the concentration of nitrogen atoms in the silicon oxide film so that the upper layer portion of the silicon oxide film is lower than the lower layer portion. Such a nitrogen atom distribution is achieved by performing the above-described wet oxidation.

The present invention is not limited to a semiconductor device having a nonvolatile memory element. For example, in the present invention, one of the first silicon film and the second silicon film is an active layer, the other is a gate electrode, and the silicon oxide film is a gate insulating film (between the active layer and the gate electrode). provided insulating film) to MOS (M etal O xide S emiconducto
r) The effect can be obtained even when applied to a semiconductor device having a transistor. As the MOS transistor, SRA
M and (S tatic R andom A ccess M emory) MOS transistor for load used in the memory cell of the, MOS transistor for driving which is used in liquid crystal displays.

The present invention is also applicable to a semiconductor device having a capacitance element using the first silicon film as a lower electrode, the second silicon film as an upper electrode, and the silicon oxide film as a dielectric film. The effect is obtained.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

Embodiment 1 In this embodiment, an example in which the present invention is applied to a NOR flash memory as a semiconductor device having a nonvolatile memory element will be described.

FIG. 1 is a sectional view of a principal part of a NOR type flash memory.

The flash memory of this embodiment includes a memory cell array section in which a plurality of memory cells each having the nonvolatile memory element Qe shown in FIG. 1 as one storage unit are arranged in a matrix.

The flash memory is mainly composed of, for example, a p-type semiconductor substrate 201 of plane orientation (100) made of single crystal silicon. A field insulating film 202 is formed in a non-active region on the main surface of the p-type semiconductor substrate 201, and a nonvolatile memory element is formed in an active region on the main surface of the p-type semiconductor substrate 1 whose periphery is defined by the field insulating film 202. Qe is configured.

The nonvolatile memory element Qe mainly includes a p-type semiconductor substrate 201 used as a channel formation region,
The first gate insulating film 203, the floating gate electrode 204, the second
It comprises a gate insulating film 205, a control gate electrode 207, a punch-through stopper region 208, a source region 209, and a drain region 210. Note that the first gate insulating film 203 refers to a tunnel insulating film provided between the p-type semiconductor substrate 201 and the floating gate electrode 204. Further, the second gate insulating film 205 refers to an interlayer insulating film provided between the floating gate insulating film 204 and the control gate electrode 207.

The first gate insulating film 203 is formed of a silicon oxide film formed by subjecting a main surface of a p-type semiconductor substrate 201 to a thermal oxidation process. The floating gate electrode 204
Is formed of a polycrystalline silicon film into which an n-type impurity has been introduced for the purpose of reducing the resistance value. The second gate insulating film 205 is made of LPC using SiH ₄ and N ₂ O as source gases.
It is formed of a silicon oxide film formed by using the VD method. Nitrogen is introduced into this silicon oxide film for the purpose of reducing the leak current. The control gate electrode 207
Is formed of a polycrystalline silicon film into which an n-type impurity has been introduced for the purpose of reducing the resistance value.

The punch-through stopper region 208
The p-type semiconductor substrate 201 is formed of a p-type semiconductor region made of p-type impurities introduced into the main surface. Each of the source region 209 and the drain region 210 is formed of a pair of n-type semiconductor regions made of n-type impurities introduced into the main surface of the p-type semiconductor substrate 201.

The source region 209 has an interlayer insulating film 2
The electrode 212 is electrically connected through the connection hole formed in the electrode 11. An electrode 212 is electrically connected to the drain region 210 through a connection hole formed in the interlayer insulating film 211.

Next, a method of manufacturing a memory cell using the nonvolatile memory element Qe as one storage unit will be described with reference to FIGS. 2 and 3 (cross-sectional views for explaining the manufacturing method). First, a p-type semiconductor substrate 201 of plane orientation (100) made of single-crystal silicon is prepared.
A field insulating film 202 made of a silicon oxide film is formed in a non-active region on the main surface of the first substrate by using a known selective oxidation method. The field insulating film 202 is formed to a thickness of, for example, about 500 [nm]. FIG. 2A shows the steps up to this point.

Next, a thermal oxidation treatment is applied to the active region on the main surface of the p-type semiconductor substrate 201 to form a first silicon oxide film.
A gate insulating film 203 is formed. First gate insulating film 20
3 is formed with a film thickness of, for example, about 10 [nm].

Next, an n-type impurity is deposited on the entire surface of the main surface of the p-type semiconductor substrate 201 including the first gate insulating film 203.
A polycrystalline silicon film 204 into which (for example, phosphorus) is introduced is formed. The polycrystalline silicon film 204 is formed with a thickness of, for example, about 200 [nm].

Next, the polycrystalline silicon film 204 is patterned. Patterning is performed using a photolithography technique and a dry etching technique. The steps up to this point are shown in FIG.

Next, the p including the polycrystalline silicon film 204
Silicon oxide film 205 over the entire main surface of type semiconductor substrate 201
Is formed with a film thickness of, for example, 12 [nm]. Silicon oxide film 2
05 is formed by LPC using SiH ₄ and N ₂ O as source gases.
This is performed by the VD method. The formation temperature at this time is 750 [° C.].

Next, immediately after performing the above-described steps, a heat treatment is performed in an NH 3 atmosphere to introduce nitrogen into the silicon oxide film 205. The steps up to this point are shown in FIG.

Next, on the entire surface of the silicon oxide film 205,
Polycrystalline silicon film 207 into which an n-type impurity (for example, phosphorus) is introduced
To form The polycrystalline silicon film 207 is, for example, 200 [n]
m]. The steps so far are shown in FIG.
Shown in

Next, each of the polycrystalline silicon film 207, the silicon oxide film 205, and the polycrystalline silicon film 204 is sequentially patterned to define a width in a gate length direction, and polycrystalline silicon doped with an n-type impurity is formed. A control gate electrode 207 made of a film 207, a second gate insulating film 205 made of a silicon oxide film 205 into which nitrogen is introduced, and a floating gate electrode 204 made of a polycrystalline silicon film 204 into which an n-type impurity is introduced are formed. These patterning are performed using a photolithography technique and a dry etching technique. In this step, although not shown, the control gate electrode 207
Also, a word line integrated with is formed. The steps so far are shown in FIG.

Next, a p-type impurity (for example, boron) is selectively introduced into the active region on the main surface of the p-type semiconductor substrate 201 by ion implantation to form a punch-through stopper region 208 made of an n-type semiconductor region. I do.

Next, an n-type impurity (for example, arsenic) is selectively introduced into the active region on the main surface of the p-type semiconductor substrate 201 by ion implantation to form a source region 209 comprising a pair of n-type semiconductor regions. And a drain region 210 are formed. In this step, a nonvolatile memory element Qe is formed. The steps up to this point are shown in FIG.

Next, the interlayer insulating film 21 is formed on the entire surface of the main surface of the p-type semiconductor substrate 201 including the surface of the control gate electrode 207.
Thereafter, a connection hole reaching the source region 209 and the drain region 210 is formed in the interlayer insulating film 211.

Next, the interlayer insulating film 21 including the inside of the connection hole is formed.
1, a metal film is formed on the entire surface, and then the metal film is patterned to form an electrode 212, whereby a memory cell having the nonvolatile memory element Qe shown in FIG. Complete.

Next, characteristics of the nonvolatile memory element Qe formed by the above-described manufacturing method will be described. Here, for comparison, samples were prepared in which the heat treatment temperature and time in an NH ₃ atmosphere were variously changed, and the nitrogen atom concentration in the silicon oxide film (second gate insulating film) 205, the leak current, and the non-volatile The characteristics of the storage element Qe were compared and studied.

FIGS. 4 and 5 show the current-voltage characteristics of the silicon oxide film 205. FIG. Figure 4 is a heat treatment temperature in NH3 atmosphere 850 [° C.], the result in the case of changing the time, FIG. 5 is a heat treatment time in NH ₃ atmosphere was 10 minutes, when the temperature is changed Is the result of
The film thickness was 12 [nm] in each case. 4 and 5 that the leakage current of the silicon oxide film 205 decreases as the heat treatment time and temperature in the NH ₃ atmosphere increase.

The aforementioned decrease in the leak current has a strong correlation with the nitrogen atom concentration in the silicon oxide film 205. FIG.
Control gate electrode (polycrystalline silicon film 207) / second gate insulating film (silicon oxide film 205) / floating gate electrode (polycrystalline silicon film 20) of a sample heat-treated in an NH ₃ atmosphere at 50 ° C.
The nitrogen atom distribution in section 4) was analyzed using a secondary ion mass spectrometer (S
IMS). By heat treatment in an NH3 atmosphere, 2 × 10 ²⁰ [at
oms / cm3] or more of nitrogen atoms. The nitrogen atom concentration in the silicon oxide film 205 is higher in the upper layer portion and the lower layer portion than in the middle layer portion of the silicon oxide film 205. Further, the nitrogen atom concentration increases as the heat treatment time in an NH ₃ atmosphere increases.

FIG. 7 shows the relationship between the concentration of nitrogen atoms in the silicon oxide film 205 and the leakage current when the silicon oxide film 205 is heat-treated at various temperatures and times in an NH ₃ atmosphere. . Here, as the nitrogen atom concentration in the silicon oxide film 205, a value in a lower layer portion of the silicon oxide film 205 is used. The leak current was defined as the maximum electric field of 7.5 MV / cm applied to the second gate insulating film 205 when injecting electrons into the floating gate electrode 204. From this result, it can be seen that the leakage current of the silicon oxide film 205 is uniquely determined by the nitrogen atom concentration regardless of the heat treatment conditions, and decreases as the nitrogen atom concentration increases. In order to secure a threshold window at the time of writing / erasing and maintain the retention characteristics, the leakage current of the second gate insulating film 205 must be 10 ^-4.
It is necessary to: As shown in FIG. 7, in order to achieve this current level, the nitrogen atom concentration in the silicon oxide film 205 is set to 2 ×
It must be 10 ²⁰ [atoms / cm3] or more.

In order to form a fine nonvolatile memory element Qe having a gate length of 0.5 [μm] or less, the upper limit of the process temperature must be 900 [° C.] or less. The heat treatment temperature of the silicon oxide film 205 in the NH3 atmosphere is 90
The nitrogen atom concentration in the silicon oxide film 205 was measured by the SIMS analysis described above for a sample which was set to 0 [° C.] and the heat treatment time was changed, and was found to be approximately 2 × 10 ²¹ [atoms / cm 3].
, And it was difficult to introduce any more nitrogen atoms. Therefore, the concentration of nitrogen atoms in the silicon oxide film 205 is approximately 2 × 10 ²⁰ [atoms / cm 3] or more, preferably 2 × 10 ²⁰ [atoms / cm 3].
It is limited to the range of × 10 ²¹ [atoms / cm 3] or less.

FIG. 8 shows that nitrogen atoms are introduced into the silicon oxide film 205 in an NH 3 atmosphere at 850 ° C. for 10 minutes, electrons are injected into the floating gate electrode 204 of the nonvolatile memory element Qe, and then 250 ° C. ] Shows the fluctuation of the threshold voltage when baking is performed in a nitrogen atmosphere. FIG. 11 also shows the results of the second gate insulating film 205 and the thermal silicon oxide film and the ONO film of the related art. Each film thickness is 12 [nm].

Silicon oxide film 2 heat-treated in NH ₃ atmosphere
05 indicates that the decrease in threshold voltage is smaller than that of the conventional thermal silicon oxide film or ONO film, and that the charge retention characteristics of the nonvolatile memory element Qe are improved. This is because, as described above, when the thickness of the second gate insulating film 205 is reduced to 12 [nm], the leak current of the silicon oxide 205 is reduced as compared with the thermal silicon oxide film and the ONO film. Note that the concentration of nitrogen atoms in the silicon oxide film 205 is approximately 2 × 10 ²⁰
[Atoms / cm3] or more, preferably 2 × 10 ²¹ [atoms / c
m3], the charge retention characteristics were almost the same.

According to the present embodiment, approximately 2 × 10 ²⁰ [at
oms / cm3] or more, preferably 2 × 10 ²¹ [atoms / cm3]
By using the following silicon oxide film 205 containing nitrogen atoms as the second gate insulating film 205 of the nonvolatile memory element Qe, there is an effect that charge retention characteristics can be improved.

(Embodiment 2) In this embodiment, the maximum nitrogen atom concentration in the film is approximately 2 × 10 ²⁰ [atoms / cm 3] or more.
It is preferably 2 × 10 ²¹ [atoms / cm 3] or less, and a silicon oxide film whose nitrogen distribution was optimized and whose hydrogen atom concentration was reduced was used as the second gate insulating film of the nonvolatile memory element. An example will be described.

First, a method of manufacturing a memory cell using a nonvolatile storage element as one storage unit will be described with reference to FIGS.
(A cross-sectional view for explaining the manufacturing method) will be described.

A p-type semiconductor substrate 201 of plane orientation (100) made of single crystal silicon is prepared.
A field insulating film 202 made of a silicon oxide film is formed in a non-active region of the main surface of the semiconductor device 01 using a known selective oxidation method.
The field insulating film 202 is formed to a thickness of, for example, about 500 [nm]. FIG. 9A shows the steps up to this point. Next, a thermal oxidation process is performed on the active region on the main surface of the p-type semiconductor substrate 201 to form a first gate insulating film 2 made of a silicon oxide film.
03 is formed. The first gate insulating film 203 is, for example, 10
It is formed with a thickness of about [nm].

Next, an n-type impurity is deposited on the entire surface of the main surface of the p-type semiconductor substrate 201 including the first gate insulating film 203.
A polycrystalline silicon film 204 into which (for example, phosphorus) is introduced is formed. The polycrystalline silicon film 204 is formed with a thickness of, for example, about 200 [nm].

Next, the polycrystalline silicon film 204 is patterned. Patterning is performed using a photolithography technique and a dry etching technique. FIG. 9B shows the steps up to this point.

Next, the p including the polycrystalline silicon film 204
Silicon oxide film 205 over the entire main surface of type semiconductor substrate 201
Is formed with a film thickness of, for example, 12 [nm]. Silicon oxide film 2
05 is formed by LPC using SiH ₄ and N 2 O as source gas.
This is performed by the VD method. The formation temperature at this time is 750 [° C.].

Next, immediately after performing the above-described steps, a heat treatment is performed in an NH ₃ atmosphere, so that the silicon oxide film 205 is approximately 6 ×
A nitrogen atom of 10 ²⁰ [atoms / cm 3] is introduced.

Next, 825 is applied to the silicon oxide film 205.
A wet oxidation treatment is performed in a temperature atmosphere of [° C.]. The steps up to this point are shown in FIG.

Next, on the entire surface of the silicon oxide film 205,
Polycrystalline silicon film 207 into which an n-type impurity (for example, phosphorus) is introduced
To form The polycrystalline silicon film 207 is, for example, 200 [n]
m]. The steps up to this point are shown in FIG.
It is shown in (d).

Next, each of the polycrystalline silicon film 207, the silicon oxide film 205, and the polycrystalline silicon film 204 is sequentially patterned to define a width in a gate length direction, and polycrystalline silicon doped with an n-type impurity is formed. A control gate electrode 207 made of a film 207, a second gate insulating film 205 made of a silicon oxide film 205 into which nitrogen is introduced, and a floating gate electrode 204 made of a polycrystalline silicon film 204 into which an n-type impurity is introduced are formed. These patterning are performed using a photolithography technique and a dry etching technique. In this step, although not shown, the control gate electrode 207
Also, a word line integrated with is formed. The steps so far are shown in FIG.

Next, a p-type impurity (for example, boron) is selectively introduced into the active region on the main surface of the p-type semiconductor substrate 201 by ion implantation to form a punch-through stopper region 208 made of a p-type semiconductor region. I do.

Next, an n-type impurity (for example, arsenic) is selectively introduced into the active region on the main surface of the p-type semiconductor substrate 201 by ion implantation to form a source region 209 comprising a pair of n-type semiconductor regions. And a drain region 210 are formed.
In this step, a nonvolatile memory element Qe is formed. The steps so far are shown in FIG.

Next, the interlayer insulating film 21 is formed on the entire surface of the main surface of the p-type semiconductor substrate 201 including on the control gate electrode 207.
Thereafter, a connection hole reaching the source region 209 and the drain region 210 is formed in the interlayer insulating film 211.

Next, the interlayer insulating film 21 including the inside of the connection hole is formed.
1, a metal film is formed on the entire surface, and thereafter, the metal film is patterned to form an electrode 212, so that the nonvolatile memory element Qe is stored in one storage unit as shown in FIG. Is almost completed.

The non-volatile memory element Qe of the present embodiment was able to hold charges for a longer time than in the first embodiment. To investigate the reason, the atomic concentration distribution in the silicon oxide film 205 before and after the wet oxidation was observed using a secondary ion mass spectrometer. FIG. 11 shows the state before wet oxidation.
FIG. 12 shows the nitrogen and hydrogen concentration distribution in the silicon oxide film 205 after wet oxidation. From the comparison between the two figures, it is found that the concentration of hydrogen atoms in the silicon oxide film 205 is 2 × 10 5 by wet oxidation.
²¹ from [atoms / cm3] to ^{2 × 10 20 [atoms / cm3} ] 1
It is evident that it has decreased by an order of magnitude. Further, a decrease in the nitrogen concentration in the upper layer portion of the silicon oxide film 205 (on the side of the control gate electrode 207) was also confirmed. From this analysis result, it can be seen that the silicon oxide film 20
5, the reduction of electron traps due to the reduction of hydrogen atoms and the suppression of hole current due to the reduction of the nitrogen concentration in the upper layer portion (on the side of the control gate electrode 207) of the silicon oxide film 205 improve the charge retention characteristics of the nonvolatile memory element Qe. It is thought that was realized.

In this embodiment, the nitrogen atom concentration in the silicon oxide film 205 is set to 6 × 10 ²⁰ [atoms / cm 3].
Approximately 2 × 10 20 [atoms / cm 3] or more, preferably 2 × 1
When the value is 0 ²¹ [atoms / cm 3] or less, an improvement in charge retention characteristics is observed. When the concentration of hydrogen atoms in the silicon oxide film 205 was 5 × 10 ²⁰ [atoms / cm 3] or less, the charge retention characteristics were similarly improved.

By setting the concentration of hydrogen atoms in the silicon oxide film 205 to 5 × 10 ²⁰ [atoms / cm 3] or less, it is possible to suppress a change in threshold value due to rewriting of the nonvolatile memory element Qe. is there. FIG. 20 shows the amount of threshold change due to rewriting before and after the reduction of hydrogen atoms by wet oxidation. The nitrogen atom concentration at this time is 6 × 10 ²⁰
[Atoms / cm3]. The threshold variation before wet oxidation (hydrogen atom concentration 3 × 10 ²¹ [atoms / cm 3])
While the voltage is 0.65 V, it is suppressed to about 0.15 V after wet oxidation (hydrogen atom concentration: 3 × 10 ²⁰ [atoms / cm 3]). This is because electron traps in the silicon oxide film 205 are reduced by reducing hydrogen atoms by wet oxidation.

In this embodiment, the concentration of nitrogen atoms in the silicon oxide film 205 is set to 6 × 10 ²⁰ [atoms / cm 3].
Approximately 2 × 10 ²⁰ [atoms / cm 3] or more, preferably 2 × 1
0 ²¹ [atoms / cm3] or less and the hydrogen atom concentration is 5
If it is equal to or less than × 10 ²⁰ [atoms / cm 3], it is possible to suppress the threshold value fluctuation accompanying the rewriting.

According to the present embodiment, approximately 2 × 10 ²⁰ [at
oms / cm3] or more, preferably 2 × 10 ²¹ [atoms / cm3]
The following silicon oxide film 205 containing a nitrogen atom is used as the second gate insulating film 205 of the nonvolatile memory element Qe,
Further, the upper layer portion of the silicon oxide film 205 is made higher in nitrogen atom concentration than the lower layer portion of the silicon oxide film 205.
By setting the maximum hydrogen atom concentration in the medium to 5 × 10 ²⁰ [atoms / cm 3] or less, there is an effect that the charge retention characteristics of the nonvolatile memory element Qe can be improved. In addition, there is an effect that a threshold change due to rewriting of the nonvolatile memory element Qe can be suppressed.

(Embodiment 3) In this embodiment, the maximum nitrogen atom concentration in the film is approximately 2 × 10 ²⁰ [atoms / cm 3] or more.
An example in which a silicon oxide film of preferably 2 × 10 ²¹ [atoms / cm 3] or less is used as a second gate insulating film of a nonvolatile memory element, and a silicon nitride (Si ₃ N ₄ ) film is further laminated thereon. explain.

First, a method of manufacturing a memory cell using a nonvolatile storage element as one storage unit will be described with reference to FIGS.
4 (a cross-sectional view for explaining the manufacturing method).

A p-type semiconductor substrate 201 of plane orientation (100) made of single crystal silicon is prepared.
A field insulating film 202 made of a silicon oxide film is formed in a non-active region of the main surface of the semiconductor device 01 using a known selective oxidation method.
The field insulating film 202 is formed to a thickness of, for example, about 500 [nm]. FIG. 13A shows the steps up to this point.

Next, a thermal oxidation process is performed on the active region on the main surface of the p-type semiconductor substrate 201 to form a first region made of a silicon oxide film.
A gate insulating film 203 is formed. First gate insulating film 20
3 is formed with a film thickness of, for example, about 10 [nm].

Next, an n-type impurity is deposited on the entire surface of the main surface of the p-type semiconductor substrate 201 including the first gate insulating film 203.
A polycrystalline silicon film 204 into which (for example, phosphorus) is introduced is formed. The polycrystalline silicon film 204 is formed with a thickness of, for example, about 200 [nm].

Next, the polycrystalline silicon film 204 is patterned. Patterning is performed using a photolithography technique and a dry etching technique. FIG. 13B shows the steps up to this point.

Next, the p including the surface of the polycrystalline silicon film 204 is removed.
Silicon oxide film 205 over the entire main surface of type semiconductor substrate 201
Is formed with a film thickness of, for example, 12 [nm]. Silicon oxide film 2
05 is formed by LPC using SiH4 and N2O as source gas.
This is performed by the VD method. The formation temperature at this time is 750 [° C.].

Next, immediately after performing the above-described steps, a heat treatment is performed in an NH 3 atmosphere, so that the silicon oxide film 205 is approximately 6 ×
A nitrogen atom of 10 ²⁰ [atoms / cm 3] is introduced. The steps up to this point are shown in FIG.

Next, a silicon nitride (Si ₃ N ₄ ) film 213 is formed on the entire surface of the main surface of the p-type semiconductor substrate 201 including the silicon oxide film 205 by LPCVD. FIG. 13D shows the steps up to this step.

Next, on the entire surface of the silicon oxide film 205,
Polycrystalline silicon film 207 into which an n-type impurity (for example, phosphorus) is introduced
To form The polycrystalline silicon film 207 is, for example, 200 [n]
m]. The steps so far are shown in FIG.
(e).

Next, each of the polycrystalline silicon film 207, the silicon nitride film 213, the silicon oxide film 205, and the polycrystalline silicon film 204 is sequentially patterned to define a width in a gate length direction, and an n-type impurity is introduced. Control gate electrode 207 made of doped polysilicon film 207, second gate insulating film 205 made of silicon oxide film 205 introduced with nitrogen, and floating gate electrode 204 made of polycrystalline silicon film 204 doped with n-type impurities To form These patterning are performed using a photolithography technique and a dry etching technique. In this step, although not shown, a word line integrated with the control gate electrode 207 is also formed. The steps so far are shown in FIG. Next, the p
A p-type impurity (for example, boron) is selectively introduced into the active region on the main surface of the type semiconductor substrate 201 by ion implantation to form a punch-through stopper region 208 made of an n-type semiconductor region.

Next, an n-type impurity (for example, arsenic) is selectively introduced into the active region on the main surface of the p-type semiconductor substrate 201 by ion implantation to form a source region 209 comprising a pair of n-type semiconductor regions. And a drain region 210 are formed.
In this step, a nonvolatile memory element Qe is formed. The steps up to this point are shown in FIG.

Next, the interlayer insulating film 21 is formed on the entire surface of the main surface of the p-type semiconductor substrate 201 including the region above the control gate electrode 207.
Thereafter, a connection hole reaching the source region 209 and the drain region 210 is formed in the interlayer insulating film 211.

Next, the interlayer insulating film 21 including the inside of the connection hole is formed.
14, a metal film is formed on the entire surface, and then the metal film is patterned to form an electrode 212. As a result, as shown in FIG. Is almost completed.

The nonvolatile memory element Qe has a capacity of 12 [n
m], the charge retention characteristics were improved as compared with the case where a silicon nitride film was deposited on the ONO film.

In this embodiment, the concentration of nitrogen atoms in the silicon oxide film 205 is set to 6 × 10 ²⁰ [atoms / cm 3] or more, but is generally set to 2 × 10 ²⁰ [atoms / cm 3] or more, preferably 2 × 10 ²⁰ [atoms / cm 3].
If the density is not more than × 10 ²¹ [atoms / cm 3], an improvement in charge retention characteristics is observed.

According to the present embodiment, approximately 2 × 10 ²⁰ [at
oms / cm 3] or more and 2 × 10 ²¹ [atoms / cm 3] or less.
By using it as the second gate insulating film 205 of e and further stacking the silicon nitride film 213 thereon, there is an effect that the charge retention characteristics of the nonvolatile memory element Qe can be improved.

In this embodiment, the nitrogen atoms are introduced into the silicon oxide film 205 and then the silicon nitride film 213 is formed. However, before the silicon nitride film 213 is formed, the silicon nitride film 213 is formed in the same manner as in the second embodiment. If a wet oxidation treatment is performed to reduce the concentration of hydrogen atoms in the silicon oxide film 205 to 5 × 10 ²⁰ [atoms / cm 3] or less, a further effect can be obtained.

(Embodiment 4) In this embodiment, the maximum nitrogen atom concentration in the film is approximately 2 × 10 ²⁰ [atoms / cm 3] or more.
An example in which a silicon oxide film having a density of preferably 2 × 10 ²¹ [atoms / cm 3] or less is used as a second gate insulating film of a nonvolatile memory element will be described. The nonvolatile memory element according to the present embodiment is mounted on a flash memory having an AND-type contactless array structure.

First, a method of manufacturing a memory cell using a nonvolatile memory element as one storage unit will be described with reference to FIGS.
(A cross-sectional view for explaining the manufacturing method) will be described.

A p-type semiconductor substrate 101 of plane orientation (100) made of single crystal silicon is prepared.

Next, a thermal oxidation treatment is performed to form a first gate insulating film 1 made of a silicon oxide film on the main surface of the p-type semiconductor substrate 101.
02 is formed.

Next, a polycrystalline silicon film 103 doped with an impurity (for example, phosphorus) is formed on the first gate insulating film 102, and then a silicon oxide film 104 is formed on the polycrystalline silicon film 103.
Is formed, and then the silicon nitride film 1 is formed on the silicon oxide film 104.
05 is formed. Polycrystalline silicon film 103, silicon oxide film 10
4. Each of the silicon nitride films 105 is sequentially formed by the LPCVD method.

Next, the silicon nitride film 105, the silicon oxide film 104, the polycrystalline silicon film 103, the first gate insulating film 102
Are subjected to patterning for defining the width in the gate length direction. Patterning is performed using a photolithography technique and a dry etching technique. FIG. 15A shows the steps up to this point.

Next, a silicon nitride film is formed on the entire surface of the main surface of the p-type semiconductor substrate 101 including the silicon nitride film 105 by LPC.
Thereafter, the silicon nitride film is subjected to anisotropic dry etching to form a sidewall spacer 106. The steps so far are shown in FIG.

Next, a field oxide film 107 made of a silicon oxide film is formed on the main surface of the p-type semiconductor substrate 101 by performing a wet oxidation process. The field insulating film 107 separates active regions (element forming regions) arranged along the gate length direction. The steps up to this point are shown in FIG.

Next, after performing a hot phosphoric acid treatment to remove the silicon nitride film 105 and the sidewall spacers 106, a p-type impurity (for example, boron) is ion-implanted into the active region on the main surface of the p-type semiconductor substrate 101. A punch-through stopper region 108 made of a p-type semiconductor region is selectively formed by implantation.

Next, an n-type impurity (for example, arsenic) is selectively introduced into the active region on the main surface of the p-type semiconductor substrate 101 by ion implantation to form a source region 109 comprising a pair of n-type semiconductor regions. And a drain region 110 are formed.
The steps so far are shown in FIG.

Next, a silicon oxide film 111 is formed on the entire main surface of the p-type semiconductor substrate 101 including the silicon oxide film 105 by LPCVD, and thereafter, the silicon oxide film 111 is formed.
Is anisotropically etched until the upper surface of the polycrystalline silicon film 103 is exposed. The steps so far are shown in FIG.

Next, the p including the surface of the polycrystalline silicon film 103
Impurities (for example, phosphorus) on the entire main surface of the semiconductor substrate 101
Is formed, and then the polycrystalline silicon film 112 is subjected to patterning for defining the width in the gate length direction. The steps so far are shown in FIG.

Next, the p including the upper part of the polycrystalline silicon film 112 is removed.
Silicon oxide film 113 over the entire main surface of semiconductor substrate 101
Is formed with a film thickness of, for example, 12 [nm]. Silicon oxide film 1
13 is formed by using LPC using SiH ₄ and N ₂ O as source gases.
This is performed by the VD method. The formation temperature at this time is 750 [° C.].

Next, immediately after performing the above-described steps, a heat treatment is performed in an NH ₃ atmosphere, so that the silicon oxide film 113 is approximately 6 ×
A nitrogen atom of 10 ²⁰ [atoms / cm 3] is introduced. The steps up to this point are shown in FIG.

Next, over the entire surface of the silicon oxide film 113,
Polycrystalline silicon film 115 into which an n-type impurity (for example, phosphorus) is introduced
To form

Next, the polycrystalline silicon film 115, the silicon oxide film 113, the polycrystalline silicon film 112, and the polycrystalline silicon film 103 are sequentially patterned to define the width in the gate width direction, and the n-type impurity is removed. Control gate electrode 115 made of introduced polycrystalline silicon film 115, second gate insulating film 113 made of silicon oxide film 113 introduced with nitrogen, polycrystalline silicon film 112 doped with n-type impurities, and polycrystalline silicon film 1
03 is formed. These patterning are performed using a photolithography technique and a dry etching technique. Although not shown, a word line integrated with the control gate electrode 115 is also formed in this step. The steps up to this point are shown in FIG.

Next, an interlayer insulating film 116 is formed on the entire surface of the main surface of the p-type semiconductor substrate 101 including the control gate electrodes 115 and the word lines.
By forming a data line 117 on the semiconductor substrate 16 and then performing a heat treatment in a hydrogen atmosphere, a memory cell using the nonvolatile memory element Qe as one storage unit is almost completed. The steps so far are shown in FIG.

The nonvolatile memory element Qe has a capacity of 12 [n
m], the charge retention characteristics were improved as compared with the case where the ONO film of [m] was used for the second gate insulating film. As in the first embodiment, in order to obtain good charge retention characteristics, the concentration of nitrogen atoms in the silicon oxide film 113 is set to approximately 2 × 10 ²⁰ [atoms / c].
m3] or more, preferably 2 × 10 ²¹ [atoms / cm3] or less.

FIG. 17 shows the silicon oxide film 113 described above.
3 shows a relationship between a gate length and a threshold voltage after irradiation of ultraviolet rays in a nonvolatile memory element using as a second gate insulating film. A silicon oxide film heat-treated in an NH3 atmosphere has a shorter gate length, for example, 0.3
A stable operation was possible even at [μm] or less. This is because the formation temperature of the silicon oxide film 114 is 850.
This is because the elongation of the source / drain regions was suppressed as a result of [° C.] lower than that of the ONO film.

According to the present embodiment, approximately 2 × 10 ²⁰ [at
oms / cm3] or more, preferably 2 × 10 ²¹ [atoms / cm3]
By using the following silicon oxide film 114 containing a nitrogen atom as the second gate insulating film of the nonvolatile memory element Qe,
There is an effect that charge retention characteristics can be improved.

In the nonvolatile memory element Qe in which the second gate insulating film is formed after the formation of the source / drain regions, the second gate insulating film of the nonvolatile memory element Qe
The maximum nitrogen atom concentration in the film is approximately 2 × 10 ²⁰ [atoms / cm
3], and preferably 2 × 10 ²¹ [atoms / cm 3] or less, the use of a silicon oxide film has an effect that a fine nonvolatile memory element Qe can be operated stably.

In this embodiment, the polycrystalline silicon film 115 is formed after nitrogen atoms are introduced into the silicon oxide film 114. However, before the polycrystalline silicon film 115 is formed, Similarly, a wet oxidation process is performed to reduce the hydrogen atom concentration in the silicon oxide film 114 to 5 × 10 ²⁰ [atoms / cm 2
3] When reduced below, further effects can be obtained.

As described in the third embodiment, after the formation of the silicon oxide film 114 and before the formation of the polycrystalline silicon film 115, a silicon nitride film is formed to form a second gate insulating film. The same effect can be obtained as a laminated film.

In the first to third embodiments, the NOR
In the fourth embodiment, a nonvolatile memory element mounted on a flash memory having an AND type contactless array structure has been described as an example of a nonvolatile memory element mounted on a flash memory of a NAND type. Type, D
The same effect can be obtained by applying the present invention to a nonvolatile memory element mounted on another nonvolatile semiconductor memory device such as an iNOR type or a split gate type.

Embodiment 5 In this embodiment, as a gate insulating film of a MOS transistor having a polycrystalline silicon film as an active layer, the nitrogen atom concentration in the film is approximately 2 × 10 ²⁰ [atoms].
/ Cm 3] or more, preferably 2 × 10 ²¹ [atoms / cm 3] or less, will be described. In this embodiment, the gate insulating film refers to an insulating film provided between the active layer and the gate electrode.

First, a method for manufacturing a MOS transistor will be described with reference to FIGS. 18 and 19 (cross-sectional views for explaining the manufacturing method).

An n-type semiconductor substrate 301 of plane orientation (100) made of single crystal silicon is prepared.

Next, a silicon oxide film 302 is formed on the main surface of the n-type semiconductor substrate 301 by performing a thermal oxidation process. The steps so far are shown in FIG.

Next, a polycrystalline silicon film 303 serving as an active layer of a MOS transistor is formed on the silicon oxide film 302. FIG. 18B shows the steps up to this point.

Then, a silicon oxide film 304 used as a gate insulating film is
It is formed with a thickness of [nm]. The silicon oxide film 104 is formed by an LPCVD method using SiH ₄ and N ₂ O as source gases. The formation temperature at this time is 750 [° C.].

Next, immediately after performing the above steps, 850
Heat treatment is performed in an NH ₃ atmosphere at [° C.] to introduce approximately 6 × 10 ²⁰ atoms / cm 3 of nitrogen atoms into the silicon oxide film 304. Thereafter, a wet oxidation treatment is performed in an atmosphere at a temperature of 825 ° C. to reduce the concentration of hydrogen atoms in the silicon oxide film 304 to 5 × 10 ²⁰ [atoms / cm 3] or less. The steps up to this point are shown in FIG.

Next, a polycrystalline silicon film 307 into which a p-type impurity (for example, boron) is introduced is formed on the silicon oxide film 304. The steps up to this point are shown in FIG.

Next, the polycrystalline silicon film 307 is patterned to form a gate electrode made of the polycrystalline silicon film 307. Patterning is performed using a photolithography technique and a dry etching technique. The steps up to this point are shown in FIG.

Next, using the gate electrode 307 as an impurity introduction mask, a p-type impurity (for example, boron) is introduced into the polycrystalline silicon film 303 by ion implantation to form a pair of a source region and a drain region. Is formed. In this step, a MOS transistor Q is formed.

Next, an interlayer insulating film 309 is formed on the entire surface of the main surface of the n-type semiconductor substrate 301 including on the gate electrode 307, and then a pair of p-type semiconductor regions 308 are formed on the interlayer insulating film 309. A connection hole reaching each is formed.

Next, the interlayer insulating film 30 including the inside of the connection hole is formed.
By forming a metal film on the entire surface on the substrate 9 and then patterning the metal film to form the wiring 310, the state shown in FIG.

The MOS transistor Q uses a silicon oxide film formed by a CVD method or a silicon oxide film formed by thermally oxidizing a polycrystalline silicon film 303 as a gate insulating film. The leakage current during standby was reduced. At the same time, the operating current increased. As a result,
A high on / off ratio was obtained.

In this embodiment, the nitrogen atom concentration in the silicon oxide film 304 is set to 6 × 10 ²⁰ [atoms / cm 3].
Approximately 2 × 10 20 [atoms / cm 3] or more, preferably 2 × 1
When the value was 0 ²¹ [atoms / cm 3] or less, a similarly high on / off ratio was obtained.

According to the present embodiment, as a gate insulating film of a MOS transistor Q having a polycrystalline silicon film as an active layer,
Approximately 2 × 10 ²⁰ [atoms / cm3] or more, 2 × 10 ²¹ [atom
By using a silicon oxide film containing nitrogen atoms of not more than s / cm 3], there is an effect that the on / off ratio of the MOS transistor Q can be improved.

In this embodiment, the p-channel conductivity type MOS transistor Q has been described. However, the same effect can be obtained with an n-channel conductivity type MOS transistor.

Further, in this embodiment, an MO layer having a polycrystalline silicon film as an active layer with a silicon oxide film interposed on a semiconductor substrate is used.
Although the S transistor is formed, similar effects can be obtained by forming the transistor on a glass substrate like a MOS transistor for driving a liquid crystal display.

In this embodiment, the MOS transistor in which the lower polycrystalline silicon film is used as the active layer and the upper polycrystalline silicon film is used as the gate electrode has been described. However, the lower polycrystalline silicon film is used as the gate electrode. A similar effect can be obtained in a MOS transistor using an upper polycrystalline silicon film as an active layer.

In the first to fifth embodiments, the heat treatment is performed in an NH ₃ atmosphere when introducing nitrogen atoms into the silicon oxide film. However, another nitrogen-containing gas may be used. . Further, nitrogen atoms may be introduced simultaneously with the deposition of the silicon oxide film. Other methods may be used as long as the effects of the present invention can be obtained.

Although the first to fifth embodiments have been described using a polycrystalline silicon film, similar effects can be obtained with an amorphous silicon film.

As described above, the invention made by the present inventor
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

For example, according to the present invention, a lower polycrystalline silicon film or an amorphous silicon film is used as a lower electrode, an upper polycrystalline silicon film or an amorphous silicon film is used as an upper electrode, and a silicon oxide film therebetween. May be applied to a semiconductor device having a capacitive element using as a dielectric film. In this case, the charge retention characteristics of the capacitor can be improved.

Further, the present invention may be applied to a one-chip microcomputer (semiconductor device) provided with a memory cell array having a nonvolatile storage element.

[0134]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

[0135] The charge retention characteristics of the nonvolatile memory element mounted on the semiconductor device can be improved.

Further, stable operation is possible even with a miniaturized nonvolatile memory element.

Further, the program voltage of the nonvolatile memory element can be reduced.

Further, the performance of the MOS transistor mounted on the semiconductor device can be improved.

In addition, the charge retention characteristics of the capacitor mounted on the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a flash memory according to a first embodiment of the present invention;
FIG. 4 is a sectional view of a main part of a (semiconductor device).

FIG. 2 is a cross-sectional view for explaining a method for manufacturing the flash memory.

FIG. 3 is a cross-sectional view for explaining a method for manufacturing the flash memory.

FIG. 4 is a diagram showing a relationship between a silicon oxide film electric field and a leakage current.

FIG. 5 is a diagram showing a relationship between a silicon oxide film electric field and a leak current.

FIG. 6 is a diagram showing a nitrogen atom concentration distribution in a silicon oxide film.

FIG. 7 is a graph showing a relationship between a nitrogen atom concentration in a silicon oxide film and a leakage current.

FIG. 8 is a diagram showing charge retention characteristics.

FIG. 9 is a flash memory according to a second embodiment of the present invention;
Sectional drawing for explaining the manufacturing method of the (semiconductor device).

FIG. 10 is a sectional view illustrating the method of manufacturing the flash memory.

FIG. 11 is a diagram showing a concentration distribution of nitrogen and hydrogen atoms in a silicon oxide film.

FIG. 12 is a diagram showing a concentration distribution of nitrogen and hydrogen atoms in a silicon oxide film.

FIG. 13 is a flash memory according to a third embodiment of the present invention;
Sectional drawing for explaining the manufacturing method of the (semiconductor device).

FIG. 14 is a sectional view for explaining the method for manufacturing the flash memory.

FIG. 15 is a flash memory according to a fourth embodiment of the present invention;
Sectional drawing for explaining the manufacturing method of the (semiconductor device).

FIG. 16 is a sectional view for explaining the method for manufacturing the flash memory.

FIG. 17 is a diagram showing a relationship between a gate length and a threshold voltage.

FIG. 18 is a sectional view illustrating the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention;

FIG. 19 is a sectional view illustrating the method of manufacturing the semiconductor device.

FIG. 20 is a graph showing a threshold variation due to rewriting before and after reducing hydrogen atoms by wet oxidation.

[Description of Signs] 101, 201, 301: semiconductor substrate, 102: silicon oxide film, 103: polycrystalline silicon film, 104: silicon oxide film, 1
05, 106: silicon nitride film, 107, 202: field insulating film, 108, 208: punch-through stopper region, 109, 209: source region, 111: silicon oxide film, 110, 210: drain region, 112: polycrystalline silicon Film, 113 ... a silicon oxide film into which nitrogen is introduced, 115 ...
Polycrystalline silicon film, 203: silicon oxide film, 204: polycrystalline silicon film, 205: silicon oxide film into which nitrogen is introduced, 207:
Polycrystalline silicon film, 211, 309 ... interlayer insulating film, 212,
310 ... electrode, 302 ... silicon oxide film, 303 ... polycrystalline silicon film, 304 ... silicon oxide film with nitrogen introduced, 307 ...
Polycrystalline silicon film, 308: a pair of semiconductor regions, Qe: nonvolatile memory element, Q: MOS transistor.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 27/11 H01L 29/78 613B 27/115 29/78 29/786

Claims (13)

[Claims] 1. A semiconductor device having a silicon oxide film between a first silicon film and a second silicon film overlying the first silicon film, wherein nitrogen is introduced into the silicon oxide film, and the maximum nitrogen in the silicon oxide film is A semiconductor device having an atomic concentration of about 2 × 10 ²⁰ [atoms / cm 3] or more. 2. The semiconductor device according to claim 1, wherein a maximum nitrogen atom concentration in said silicon oxide film is approximately 2 × 10 ²¹ [atoms / cm 3] or less. 3. The silicon oxide film according to claim 1, wherein a concentration of nitrogen atoms in the upper layer portion and a lower layer portion of the silicon oxide film is higher than that in a middle layer portion of the silicon oxide film. 3. The semiconductor device according to 2. 4. The silicon oxide film according to claim 1, wherein the concentration of nitrogen atoms in the upper part of the silicon oxide film is lower than that in the lower part of the silicon oxide film. The semiconductor device according to claim 1. 5. The method according to claim 1, wherein the maximum concentration of hydrogen atoms in the silicon oxide film is approximately 5 × 10 ²⁰ [atoms / cm 3] or less. 13. The semiconductor device according to claim 1. 6. The semiconductor device according to claim 1, wherein each of said first silicon film and said second silicon film contains an n-type impurity. 7. The semiconductor device according to claim 1, wherein each of said first silicon film and said second silicon film is an electrode. 8. The semiconductor device according to claim 1, wherein one of the first silicon film and the second silicon film is in a floating state. 9. A semiconductor device having a nonvolatile memory element provided with an insulating film between a floating gate electrode and a control gate electrode, wherein the floating gate electrode is the first silicon film and the insulating film 7. The semiconductor device according to claim 1, wherein is the silicon oxide film, and the control gate electrode is the second silicon film. 8. 10. A semiconductor device having a MOS transistor in which an insulating film is provided between an active layer and a gate electrode, wherein the active layer is the first silicon film or the second silicon film. 6. The semiconductor device according to claim 1, wherein is the silicon oxide film, and the gate electrode is the second silicon film or the first silicon film. 7. 11. A semiconductor device having a capacitor in which a dielectric film is provided between a lower electrode and an upper electrode, wherein the lower electrode is the first silicon film, and the dielectric film is the oxide film. 6. The semiconductor device according to claim 1, wherein the semiconductor device is a silicon film, and the upper electrode is the second silicon film. 12. A silicon nitride film having a stoichiometric ratio of approximately silicon: nitrogen = 3: 4 between said silicon oxide film and said second silicon film. Or claim 1
2. The semiconductor device according to claim 1. 13. The first silicon film and the second silicon film each include:
The semiconductor device according to claim 1, wherein the semiconductor device is made of polycrystal or amorphous.