JP2000012712A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a method for manufacturing a polycrystalline silicon interlayer insulating film, which can be applied to nonvolatile semiconductor storage devices and has few electron traps. SOLUTION: In a method for manufacturing a semiconductor device, having a nonvolatile storage element in which diffused layers which become source and drain are formed in a semiconductor substrate and a floating gate electrode is formed on the substrate through an insulating film, and then a control gate electrode is formed on the floating gate electrode through an insulating film, a silicon film 104 which becomes the floating gate electrode is formed and a silicon oxide film is formed by a reduced-pressure chemical vapor growth method using dichlorosilane as a source gas. After working the film 104 to a desired shape and heat-treated in an ammonia atmosphere immediately after the formation, a silicon film 107 which becomes the control gate electrode is formed. Therefore, the charge holding characteristic of the nonvolatile semiconductor storage device is improved after rewriting memory cells.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a nonvolatile memory element in which an insulating film is provided between a floating gate electrode and a control gate electrode. It is about effective technology.

[0002]

2. Description of the Related Art As a semiconductor device, there is a nonvolatile semiconductor memory device called a flash memory. This flash memory is excellent in portability and shock resistance, and can be electrically erased collectively on-board. Therefore, the flash memory has attracted attention as a file memory of future small portable information devices.

[0003] A memory cell of a flash memory is composed of a non-volatile storage element.
A diffusion layer serving as a source region and a drain region is formed in a semiconductor substrate made of single crystal silicon (Si). A floating gate electrode made of a polycrystalline Si film is formed on the semiconductor substrate with a gate insulating film interposed therebetween. A control gate electrode made of a polycrystalline Si film is formed on the electrode with an insulating film interposed therebetween. In a flash memory, a positive voltage is applied to a control gate electrode of a nonvolatile memory element with respect to a substrate to inject electrons into a floating gate electrode, and information “0” or “1” is obtained from a difference in threshold voltage. Is determined.

A silicon nitride film (Si ₃ N ₄ ) is usually used as an insulating film (hereinafter, referred to as a polycrystalline Si interlayer insulating film) for retaining charges accumulated in a floating gate electrode of a nonvolatile memory element.
Film sandwiched between silicon oxide films (SiO ₂ films), so-called O
An NO film is used.

[0005] However, the above-mentioned ONO film causes a problem in terms of lowering the process temperature accompanying the high integration of flash memories. The ONO film is usually formed by the following method. First, the floating gate polycrystalline Si film is thermally oxidized to form a lower SiO ₂ film. Then, low pressure chemical vapor deposition (LPCVD (L ow P ressure C hemical V apor D ep
The the Si ₃ N ₄ film was formed by osition) method), the Si ₃ N ₄
The surface of the film is thermally oxidized to form an upper SiO ₂ film. However, thermal oxidation of this Si ₃ N ₄ film usually requires a high temperature of 900 ° C. or more. Therefore, when forming a polycrystalline Si interlayer insulating film after forming a source / drain diffusion layer, LS
It becomes difficult to form a shallow junction that is indispensable for miniaturization of I, and this becomes a factor that hinders high integration of flash memories.

[0006] Further, the ONO film has a limit in thinning, which hinders a reduction in the voltage of the flash memory. This is for the following reason. The voltage _Vfg applied to the floating gate electrode during the rewriting operation of the flash memory is

[0007]

V _fg = C ₂ V _cg / (C ₁ + C ₂ ) (1) Here, V _cg is the voltage applied to the control gate electrode, C ₁ is the capacity of the gate insulating film, and C ₂ is the capacity of the polycrystalline Si interlayer insulating film. In order to efficiently transmit the voltage applied to the control gate electrode to the floating gate electrode and reduce the program voltage, the polycrystalline Si interlayer insulating film must be thinned to reduce the C voltage.
It is effective to increase ₂ . However, in the above-mentioned ONO film, when the upper and lower SiO ₂ films are 5 nm or less, there is a problem that charges accumulated in the floating gate electrode leak to the control gate electrode, so-called retention failure becomes apparent. . When an upper SiO ₂ film is to be formed by a thermal oxidation method, 10 [nm] is used to prevent oxidation of a lower polycrystalline Si film serving as a floating gate electrode.
It was necessary to form a Si ₃ N ₄ film of a degree or more. For this reason, the thinning of the ONO film is reduced to 15 [nm] in terms of SiO ₂ film.
The extent was marginal. Polycrystalline Si from the viewpoint of ensuring reliability
Now that it is becoming difficult to reduce the thickness of the interlayer insulating film, development of a new polycrystalline Si interlayer insulating film forming process has been expected.

Therefore, a new polycrystalline S which replaces the ONO film
A single-layer SiO ₂ film formed by a chemical vapor deposition (CVD) method has been proposed as an i-layer insulating film. In this method,
An SiO ₂ film is formed by LPCVD using monosilane (SiH ₄ ) as a source gas. However, a defect called an E ′ center exists in the present SiO ₂ film, and there is a problem that a leak current is large. Therefore, a heat treatment is performed in an ammonia (NH ₃ ) atmosphere to introduce nitrogen atoms, thereby terminating defects to reduce leakage current. This film can be formed at a low temperature of 850 ° C. or less, including heat treatment after film formation. Further, since it is a single-layer film, it can be easily thinned. About this technology, for example, solid
State Devices and Materials, 1997
Year, pp. 22-23 (Solid State Devices and M
aterials, (1991) pp22-23).

[0009]

However, when the above-mentioned technique is applied to the multi-value storage technique proposed to promote the increase in the capacity of the flash memory, a new problem arises. In multi-value storage, four or more threshold levels are formed in one memory cell. In order to perform the writing / erasing operation at high speed, it is necessary to narrow the interval between the threshold distributions. However, when a conventional single-layer CVD SiO ₂ film using SiH ₄ as a source gas is heat-treated in an NH ₃ atmosphere, electrons are trapped in the film as the film is rewritten, and the electrons are left as they are in the polycrystalline Si interlayer insulating film. As a result, the threshold value of the memory cell fluctuates, causing deterioration of the charge retention characteristics. Therefore, there is a problem that the interval between the threshold distributions cannot be narrowed. For this reason, SiH ₄
There has been a demand for a polycrystalline Si interlayer insulating film material having fewer electron traps than a film obtained by heat-treating a single-layer CVD SiO ₂ film using as a source gas in an NH ₃ atmosphere.

An object of the present invention is to provide a technique capable of improving the charge retention characteristics.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

[0013] The problem is that a silicon film serving as a first gate electrode (floating gate electrode) is formed, processed into a desired shape, and then subjected to a reduced pressure chemical gas using dichlorosilane (SiH ₂ Cl ₂ ) as a source gas. A silicon dioxide film (SiO ₂ film) is formed by a phase growth method (LPCVD method). Immediately thereafter, a heat treatment is performed on the silicon dioxide film in an ammonia (NH ₃ ) atmosphere, and then a second gate electrode (control gate) is formed. This is achieved by forming a silicon film to be an electrode. This is due to the following operation.

The above-mentioned electron trap is generated by N
Hydrogen (H) atoms introduced into the film when heat treatment is performed in an H ₃ atmosphere. In a CVD SiO ₂ film formed using SiH ₂ Cl ₂ as a source gas, chlorine (Cl) atoms are present in the film. Some of this Cl bonds with H atoms introduced into the film when heat treatment is performed in an NH ₃ atmosphere, resulting in H
It produces Cl and is released out of the film. For this reason, CVDS
H atoms in the iO ₂ film are reduced, and the electron trap density is reduced. Therefore, the charge retention characteristics after rewriting the memory cell can be improved.

Another object is to form an Si film serving as a first gate electrode (floating gate electrode), process the Si film into a desired shape, and then use an LPC using SiH ₂ Cl ₂ as a source gas.
A SiO ₂ film is formed by a VD method, and immediately thereafter, the Si ₂ film is formed.
The O ₂ film is subjected to a heat treatment in an NH ₃ atmosphere, and then the LPC
Forming a silicon nitride film (Si ₃ N ₄ film) by VD method,
Subsequently, Si serving as a second gate electrode (control gate electrode)
This can also be achieved by forming a film.

Another object of the present invention is to form an Si film serving as a first gate electrode (floating gate electrode), process the Si film into a desired shape, and then use an LPC using SiH ₂ Cl ₂ as a source gas.
A SiO ₂ film is formed by a VD method, and immediately thereafter, the Si ₂ film is formed.
The O ₂ film is subjected to a heat treatment in an NH ₃ atmosphere, and then the LPC
A Si ₃ N ₄ film is formed by a VD method, and then a SiO ₂ film is formed, and then a second gate electrode (control gate electrode)
This is also achieved by forming a Si film that becomes

Another object of the present invention is to form a Si film serving as a first gate electrode (floating gate electrode), process the Si film into a desired shape, and then use an LPC using SiH ₂ Cl ₂ as a source gas.
A SiO ₂ film is formed by a VD method, and immediately thereafter, the Si ₂ film is formed.
The O ₂ film is subjected to a heat treatment in an NH ₃ atmosphere, and then the LPC
A Si ₃ N ₄ film is formed by a VD method, then a SiO ₂ film is formed, and then a Si ₃ N ₄ film is formed by an LPCVD method, and subsequently, a Si film serving as a second gate electrode (control gate electrode) is formed. This can also be achieved by forming a film.

Another object of the present invention is to form an Si film serving as a first gate electrode (floating gate electrode), process the Si film into a desired shape, and then use an LPC using SiH ₂ Cl ₂ as a source gas.
A SiO ₂ film is formed by a VD method, and immediately thereafter, the Si ₂ film is formed.
The O ₂ film is subjected to a heat treatment in an NH ₃ atmosphere, and then the LPC
A Si ₃ N ₄ film is formed by a VD method, and thereafter, a SiH ₂ Cl ₂ film is formed.
The a SiO ₂ film was formed by the LPCVD method as a raw material gas, the said SiO ₂ film by heat treatment in a NH ₃ atmosphere immediately, followed by a second gate electrode (control gate electrode) and a Si film formed It is also achieved by doing

Another object of the present invention is to form a Si film serving as a first gate electrode (floating gate electrode), process the Si film into a desired shape, and then use an LPC using SiH ₂ Cl ₂ as a source gas.
A SiO ₂ film is formed by a VD method, and immediately thereafter, the Si ₂ film is formed.
The O ₂ film is subjected to a heat treatment in an NH ₃ atmosphere, and then the LPC
A Si ₃ N ₄ film is formed by a VD method, and then a SiH ₂ C
An SiO ₂ film is formed by an LPCVD method using l ₂ as a source gas. Immediately thereafter, the SiO ₂ film is subjected to a heat treatment in an NH ₃ atmosphere, and thereafter, a Si ₃ N ₄ film is formed by an LPCVD method. This is also achieved by forming a Si film to be a second gate electrode (control gate electrode).

Another object is to form a Si film to be a first gate electrode (floating gate electrode), process it into a desired shape, form a SiO ₂ film, and then form an LPC.
A Si ₃ N ₄ film is formed by a VD method, and then a SiH ₂ C
An SiO ₂ film is formed by an LPCVD method using l ₂ as a source gas. Immediately thereafter, the SiO ₂ film is subjected to a heat treatment in an NH ₃ atmosphere, and then a second gate electrode (control gate electrode)
This is also achieved by forming a Si film that becomes

Another object is to form a Si film serving as a first gate electrode (floating gate electrode), process it into a desired shape, form a SiO ₂ film, and then form an LPC
A Si ₃ N ₄ film is formed by a VD method, and then a SiH ₂ C
An SiO ₂ film is formed by an LPCVD method using l ₂ as a source gas. Immediately thereafter, the SiO ₂ film is subjected to a heat treatment in an NH ₃ atmosphere, and thereafter, a Si ₃ N ₄ film is formed by an LPCVD method. This is also achieved by forming a Si film to be a second gate electrode (control gate electrode).

The source gases used when forming the SiO ₂ film by the LPCVD method using SiH ₂ Cl ₂ include nitrous oxide (N ₂ O), nitric oxide (NO), and nitrogen dioxide. And nitrogen (NO ₂ ).

Further, further effects can be obtained by performing wet oxidation after the heat treatment in the NH ₃ atmosphere.

The present invention is not limited to a polycrystalline silicon interlayer insulating film between a floating gate electrode and a control gate electrode of a nonvolatile memory element as a memory cell. For example, in a nonvolatile memory element having an erase gate electrode, the effect can be obtained even when used for an insulating film between the floating gate electrode and the erase gate electrode.

The present invention is not limited to a semiconductor device having a nonvolatile memory element. For example, the present invention may be applied to a semiconductor device having a field-effect transistor in which a diffusion layer serving as a source and a drain is formed in a semiconductor substrate and a gate electrode is formed on the semiconductor substrate via an SiO ₂ film. effective. The field-effect transistor, MOSFET constituting a peripheral circuit of the nonvolatile semiconductor memory device (M etal O xide S emiconductor F ie
ld E ffect T ransistor), and the like.

The present invention is also effective when applied to a semiconductor device having a field effect transistor having a polycrystalline Si film as an active layer and an insulating film provided between the active layer and a gate electrode. As a field effect transistor, SRA
M and (S tatic R andom A ccess M emory) MOSFET for loads used in the memory cell, MOSFET for driving used in liquid crystal displays and the like.

Further, according to the present invention, the lower electrode is formed of a polycrystalline Si film or an amorphous Si film, the upper electrode is formed of a polycrystalline Si film or an amorphous Si film, and a dielectric film is interposed therebetween. The present invention is also effective when applied to a semiconductor device having a capacitive element provided with.

Further, according to the present invention, there are provided two layers of Si films on the main surface of a semiconductor substrate,
_The present invention is applicable to all semiconductor devices having _two films.

[0029]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) In this embodiment, a polycrystalline Si interlayer insulating film of a NOR type flash memory is formed of SiH ₂ C
Si formed by LPCVD using l ₂ as a source gas
An example in which an O ₂ film is applied and the film is subjected to a heat treatment in an NH ₃ atmosphere to improve the charge retention characteristics of the memory and further suppress a threshold change due to rewriting will be described.

FIGS. 1 and 2 show a procedure for forming a memory cell (nonvolatile storage element). Each figure is a cross-sectional view of a memory cell perpendicular to a word line.

First, a Si substrate 101 having a (100) plane orientation is used.
To form a p-type well.
Thereafter, an element isolation insulating film 102 was formed to a thickness of about 400 [nm] by a known technique (FIG. 1A).

Next, after a gate oxide film 103 having a thickness of about 8.5 [nm] is formed by a thermal oxidation method, a phosphorus-doped polycrystalline Si film 104 serving as a floating gate electrode is formed.
Was formed with a thickness of about 100 [nm], and this was processed by known lithography and dry etching techniques (FIG. 1B).

Next, by a LPCVD method using SiH ₂ Cl ₂ and N ₂ O as source gases, S
An iO ₂ film 105 was formed. The temperature at the time of formation is 750 ° C. (FIG. 1C).

Thereafter, the film was heat-treated in an NH ₃ atmosphere at 850 ° C. (105 shown in FIG. 1C becomes 106 shown in FIG. 1D).

Next, a polycrystalline Si film 107 doped with phosphorus, serving as a control gate electrode, was formed with a thickness of about 150 [nm] (FIG. 2E).

Next, the polycrystalline Si film 107 and the SiO ₂ film 10 are formed by known lithography and dry etching techniques.
6. The polycrystalline Si film 104 was sequentially processed to form a floating gate electrode and a control gate electrode (FIG. 2 (f)).

Next, after boron difluoride (BF ²⁺ ) ions are implanted into the Si substrate 101 to form a punch-through stopper region 108, arsenic (As ⁺ ) ions are implanted into the Si substrate 101 to form a drain region. 109 and a source region 110 were formed (FIG. 2G).

Thereafter, an SiO ₂ film 111 containing boron and phosphorus was formed, and this was heat-treated in a nitrogen atmosphere at 850 ° C. to be reflowed. After that, a contact hole reaching the source region 109 and the drain region 110 was formed in the SiO ₂ film 111.

Next, a metal film 112 is formed by a sputtering method, processed into electrodes and wirings, and finally heat-treated in a hydrogen atmosphere to complete a memory cell (FIG. 2).
(h)).

[0041] Figure 3, in the memory cell formed by the method described above, after 10 ⁶ times write / erase, shows the change in the threshold when it was allowed to stand at 250 ° C.. In the figure, for comparison, CVD was performed by forming SiH ₄ as a source gas and heat-treating the same in an NH ₃ atmosphere.
The results for the SiO ₂ film are also shown. A CVD SiO ₂ film formed by using SiH ₂ Cl ₂ as a source gas and heat-treating the same in an NH ₃ atmosphere is formed by using SiH ₄ as a source gas,
Compared with a CVD SiO ₂ film heat-treated in an NH ₃ atmosphere, the change in threshold value was suppressed, and the charge retention characteristics were improved.

To investigate the reason, the polycrystalline Si film 10
4 / polycrystalline Si interlayer insulating film 106 / polycrystalline Si film 107
A constant current stress was applied to the polycrystalline Si interlayer insulating film of the capacitor made of and a trap charge amount in the film was measured. The result is shown in FIG. For comparison, the figure also shows the result of a CVD SiO ₂ film formed by using SiH ₄ as a source gas and heat-treating the same in an NH ₃ atmosphere. SiH ₂ C
The CVD SiO ₂ film formed by using l ₂ as a source gas and heat-treated in an NH ₃ atmosphere is a CVD Si ₂ film formed by using SiH ₄ as a source gas and heat-treated in an NH ₃ atmosphere.
The amount of trapped charge stored is smaller than that of the O ₂ film.
This is because SiH ₂ Cl ₂ is formed as a raw material gas, and chlorine atoms in a CVD SiO ₂ film which is heat-treated in an NH ₃ atmosphere are combined with hydrogen atoms in the film and released outside the film.
It is considered that traps in the film decrease.

According to this embodiment, a single-layer SiO ₂ film formed by LPCVD using SiH ₂ Cl ₂ as a source gas is N
By performing a heat treatment in an H ₃ atmosphere and using this as a polycrystalline Si interlayer insulating film of a flash memory, there is an effect that the charge retention characteristics after rewriting can be improved.

(Embodiment 2) In this embodiment, a polycrystalline Si interlayer insulating film of a NOR type flash memory is made of SiH ₂
S formed by LPCVD using Cl ₂ as a source gas
An example in which an iO ₂ film is applied, heat-treated in an NH ₃ atmosphere, and then wet-oxidized to further improve the charge retention characteristics of the flash memory after rewriting will be described.

FIGS. 5, 6 and 7 show a procedure for forming a memory cell (nonvolatile storage element). Each figure is a cross-sectional view of a memory cell perpendicular to a word line.

First, a Si substrate 101 having a plane orientation of (100)
To form a p-type well.
Thereafter, an insulating film 102 for element isolation was formed to a thickness of about 400 [nm] by a known technique (FIG. 5A).

Next, after a gate oxide film 103 having a thickness of about 8.5 nm is formed by a thermal oxidation method, a phosphorus-doped polycrystalline Si film 104 serving as a floating gate electrode is formed.
Was formed with a thickness of about 100 [nm], and this was processed by known lithography and dry etching techniques (FIG. 5B).

Next, by LPCVD using SiH ₂ Cl ₂ and N ₂ O as source gases, an S
An iO ₂ film 105 was formed. The temperature at the time of formation is 750 ° C. (FIG. 5C).

Thereafter, the film was heat-treated in an NH ₃ atmosphere at 850 ° C. (105 shown in FIG. 5C becomes 106 shown in FIG. 5D). Thereafter, the film was wet-oxidized at 850 ° C. (106 shown in FIG. 5D is replaced by 113 shown in FIG. 6E).
Becomes).

Next, a polycrystalline Si film 107 doped with phosphorus, serving as a control gate electrode, was formed with a thickness of about 150 [nm] (FIG. 6F).

Next, the polycrystalline Si film 108 and the SiO ₂ film 11 are formed by known lithography and dry etching techniques.
3. The polycrystalline Si film 104 was sequentially processed to form a floating gate electrode and a control gate electrode (FIG. 6 (g)).

Next, after boron difluoride (BF ²⁺ ) ions are implanted into the Si substrate 101 to form a punch-through stopper region 108, arsenic (As ⁺ ) ions are implanted into the Si substrate 101 to form a drain region. 109 and a source region 110 were formed (FIG. 6H).

Thereafter, an SiO ₂ film 111 containing boron and phosphorus was formed, and this was heat-treated at 850 ° C. in a nitrogen atmosphere to be reflowed. After that, a contact hole reaching the source region 109 and the drain region 110 was formed in the SiO ₂ film 111.

Next, a metal film 112 is formed by a sputtering method, and is processed into electrodes and wirings. Finally, heat treatment is performed in a hydrogen atmosphere to complete a memory cell (FIG. 7).
(i)).

The flash memory prepared by the above-mentioned method has further improved rewriting charge retention characteristics as compared with the first embodiment. This is because the wet oxidation reduces the number of hydrogen atoms in the polycrystalline Si interlayer insulating film, and further reduces the electron trap density in the film.

According to this embodiment, after a single-layer SiO ₂ film formed by LPCVD using SiH ₂ Cl ₂ as a source gas is heat-treated in an NH ₃ atmosphere, wet oxidation is further performed, and this is performed in a flash memory. By using the polycrystalline Si interlayer insulating film described above, there is an effect that the charge retention characteristics after memory rewriting can be further improved.

(Embodiment 3) In this embodiment, SiH ₂
S formed by LPCVD using Cl ₂ as a source gas
After heat-treating the iO ₂ film in an NH ₃ atmosphere, a silicon nitride film (Si ₃ N ₄ ) formed by LPCVD is laminated,
An example in which this is used for a polycrystalline Si interlayer insulating film of a NOR flash memory will be described.

FIG. 8, FIG. 9, and FIG. 10 show a procedure for forming a memory cell (non-volatile memory element). Each figure is a cross-sectional view of a memory cell perpendicular to a word line.

First, a Si substrate 101 having a plane orientation of (100)
To form a p-type well.
Thereafter, an element isolation insulating film 102 was formed to a thickness of about 400 [nm] by a known technique (FIG. 8A).

Next, after a gate oxide film 103 having a thickness of about 8.5 [nm] is formed by thermal oxidation, a phosphorus-doped polycrystalline Si film 104 serving as a floating gate electrode is formed.
Was formed with a thickness of about 100 [nm], and this was processed by known lithography and dry etching techniques (FIG. 8B).

Next, by the LPCVD method using SiH ₂ Cl ₂ and N ₂ O as source gases, the S
An iO ₂ film 105 was formed. The temperature at the time of formation is 750 ° C. (FIG. 8C). Thereafter, the film was heat-treated in an NH ₃ atmosphere at 850 ° C. (105 shown in FIG. 8C becomes 106 shown in FIG. 8D).

Next, the Si ₃ N ₄ film 11 is formed by the LPCVD method.
4 was formed (FIG. 9E).

Next, a polycrystalline Si film 107 doped with phosphorus, serving as a control gate electrode, was formed with a thickness of about 150 [nm] (FIG. 9F).

Next, the polycrystalline Si film 107 and the Si ₃ N ₄ film 11 are formed by known lithography and dry etching techniques.
4. The SiO ₂ film 106 and the polycrystalline Si film 104 were sequentially processed to form a floating gate electrode and a control gate electrode (FIG. 9G).

Next, after boron difluoride (BF ²⁺ ) ions are implanted into the Si substrate 101 to form a punch-through stopper region 108, arsenic (As ⁺ ) ions are implanted into the Si substrate 101 to form a drain region. 109 and the source region 110 were formed (FIG. 9H).

Thereafter, an SiO ₂ film 111 containing boron and phosphorus was formed, and this was heat-treated in a nitrogen atmosphere at 850 ° C. to be reflowed. After that, a contact hole reaching the source region 109 and the drain region 110 was formed in the SiO ₂ film 111.

Next, a metal film 112 is formed by a sputtering method, processed to form electrodes and wirings, and finally heat-treated in a hydrogen atmosphere to complete a memory cell (FIG. 10).
(i)).

The flash memory formed by the above method is a CVD SiO ₂ formed by using SiH ₄ as a source gas.
The film was heat-treated in an NH ₃ atmosphere, and the charge retention characteristics after rewriting were improved as compared with the case where a polycrystalline Si interlayer insulating film composed of a laminated film having a Si ₃ N ₄ film formed on the film was used.

[0069] According to this embodiment, the SiO ₂ film formed by LPCVD method using SiH ₂ Cl ₂ as source gases N
After heat treatment in an H ₃ atmosphere, Si ₃
By forming an N ₄ film and using this laminated film as a polycrystalline Si interlayer insulating film of a flash memory, there is an effect that charge retention characteristics can be improved as compared with the prior art.

In the present embodiment, a CVD SiO ₂ film serving as a polycrystalline Si interlayer insulating film is formed, heat-treated in an NH ₃ atmosphere, and then wet-oxidized by the method described in the second embodiment. further improved charge retention characteristics to form a ₃ N ₄ film.

(Embodiment 4) In this embodiment, an SiO ₂ film / Si ₃ N ₄ film / SiO ₂ film (ONO film) is used as a polycrystalline Si interlayer insulating film of a NOR type flash memory.
The SiO ₂ film of the NO film is made of L using SiH ₂ Cl ₂ as a source gas.
An example in which a threshold voltage change due to a memory rewrite is suppressed by forming by a PCVD method and thereafter performing a heat treatment in an NH ₃ atmosphere will be described.

FIGS. 11, 12 and 13 show a procedure for forming a memory cell (nonvolatile storage element). Each figure is
FIG. 3 is a sectional view of a memory cell perpendicular to a word line.

First, a Si substrate 101 having a plane orientation of (100)
To form a p-type well.
Thereafter, an element isolation insulating film 102 was formed to a thickness of about 400 [nm] by a known technique (FIG. 11A).

Next, after a gate oxide film 103 having a thickness of about 8.5 [nm] is formed by a thermal oxidation method, a phosphorus-doped polycrystalline Si film 104 serving as a floating gate electrode is formed.
Was formed in a thickness of about 100 [nm], and this was processed by known lithography and dry etching techniques (FIG. 11B).

Next, a SiO 2 film having a thickness of about 5 nm is formed by LPCVD using SiH ₂ Cl ₂ and N ₂ O as source gases.
_Two films 105 were formed. The temperature at the time of formation is 750 ° C. (FIG. 11C). Thereafter, the film was heat-treated in an NH ₃ atmosphere at 850 ° C. (105 shown in FIG.
(It becomes 106 shown to (d)).

Next, the Si ₃ N ₄ film 11 is formed by the LPCVD method.
4 was formed with a film thickness of about 8 [nm] (FIG. 12E).

Next, the SiO ₂ film 115 is formed to a thickness of 5 [nm] by LPCVD using SiH ₂ Cl ₂ and N ₂ O as source gases.
It was formed with a film thickness of about. The temperature at the time of formation is 750 ° C. (FIG. 12F). Thereafter, the film was heat-treated in an NH ₃ atmosphere at 850 ° C. (115 shown in FIG.
(It becomes 116 shown in (g)).

Next, a polycrystalline Si film 107 doped with phosphorus, serving as a control gate electrode, was formed with a thickness of about 150 [nm] (FIG. 12 (h)).

Next, the polycrystalline Si film 107 and the SiO ₂ film 11 are formed by known lithography and dry etching techniques.
6, Si ₃ N ₄ film 114, SiO ₂ film 106, polycrystalline Si
Each of the films 104 was sequentially processed to form a floating gate electrode and a control gate electrode (FIG. 13 (i)).

Next, after boron difluoride (BF ²⁺ ) ions are implanted into the Si substrate 101 to form a punch-through stopper region 108, arsenic (As ⁺ ) ions are implanted into the Si substrate 101 to form a drain region. 109 and a source region 110 were formed (FIG. 13 (j)).

Thereafter, an SiO ₂ film 111 containing boron and phosphorus was formed, and this was heat-treated in a nitrogen atmosphere at 850 ° C. to be reflowed. After that, a contact hole reaching the source region 109 and the drain region 110 was formed in the SiO ₂ film 111.

Next, a metal film 112 is formed by a sputtering method, processed into electrodes and wirings, and finally heat-treated in a hydrogen atmosphere to complete a memory cell (FIG. 13).
(k)).

The flash memory formed by the above-described method has improved charge retention characteristics after rewriting as compared with the case where the ONO film according to the prior art is used for the polycrystalline Si interlayer insulating film.

According to the present embodiment, an SiO ₂ film is formed by LPCVD using SiH ₂ Cl ₂ as a source gas, and immediately after that, a film heat-treated in an NH ₃ atmosphere is replaced with a polycrystalline Si interlayer insulating film of a flash memory. ONO film SiO ₂
By using the film, there is an effect that the charge retention characteristics after rewriting the memory cell can be improved as compared with the related art.

In this embodiment, both upper and lower SiO ₂ films constituting the ONO film are formed by LPCVD using SiH ₂ Cl ₂ as a source gas, and heat treatment is performed in an NH ₃ atmosphere. Upper and lower SiO constituting ONO film
L using SiH ₂ Cl ₂ as a source gas for one of the _two films
The same effect can be obtained by forming by the PCVD method and performing heat treatment in an NH ₃ atmosphere.

In this embodiment, before forming the polycrystalline Si film 107 to be the control gate electrode, the Si ₃ N ₄
Similar effects can be obtained by forming a film.

In the present embodiment, at least one SiO ₂ film constituting the ONO film is formed by LPCVD using SiH ₂ Cl ₂ as a source gas, and heat-treated in an NH ₃ atmosphere. When wet oxidation is performed by the method described above, the charge retention characteristics after rewriting the memory cell can be further improved.

(Embodiment 5) In this embodiment, SiH ₂
A SiO ₂ film is formed using Cl ₂ as a source gas,
_{An example} in which a film heat-treated in _three atmospheres is used as a polycrystalline Si interlayer insulating film of a contactless array type flash memory will be described.

FIG. 14, FIG. 15, and FIG. 16 show a procedure for forming a memory cell (nonvolatile storage element). Each figure is a cross-sectional view of a memory cell parallel to a word line.

First, a Si substrate 201 having a plane orientation of (100)
To form a p-type well.

Next, a gate oxide film 202 having a thickness of about 8.5 [nm] is formed by a thermal oxidation method, and a polycrystalline Si film 203 doped with phosphorus is subsequently formed to a thickness of about 100 [nm]. Formed. After that, 50 days by LPCVD method.
SiO ₂ film 204 having a thickness of about [nm], 80 [nm]
A Si ₃ N ₄ film 205 having a film thickness of about a degree was sequentially formed. Then, the four-layer film was processed by known lithography and dry etching techniques (FIG. 14A).

Next, 120 [nm] is formed by the LPCVD method.
A Si ₃ N ₄ film 206 having a film thickness of about the same thickness was formed, and this was subjected to anisotropic dry etching to leave only on the side walls of the pattern formed in FIG. 14A (FIG. 14B).

Next, S was obtained by pyrogenic oxidation.
A thermal oxide film 207 having a thickness of about 300 [nm] was formed in a portion not covered with the i ₃ N ₄ film, and separation between memory cells was performed (FIG. 14C).

Next, the Si ₃ N ₄ film 2 was heated with a hot phosphoric acid aqueous solution.
05 and 206, the boron difluoride (BF
²⁺ ) ions are implanted into the Si substrate 201 to form a punch-through stopper region 208. Subsequently, arsenic (As ⁺ ) ions are implanted into the Si substrate 201 to form a source region 209.
Then, a drain region 210 was formed (FIG. 14D).

Next, the SiO ₂ film 21 is formed by the LPCVD method.
1 and anisotropically etched until the surface of the polycrystalline Si film 203 was exposed (FIG. 15E).

Next, a polycrystalline Si film 212 doped with phosphorus was formed to a thickness of about 40 [nm], which was processed by known lithography and dry etching techniques. In this memory cell, a floating gate electrode is formed by two layers of the polycrystalline Si films 203 and 212 (FIG. 15F).

Next, an SiO ₂ film 213 serving as a polycrystalline Si interlayer insulating film was formed to a thickness of about 10 nm by LPCVD using SiH ₂ Cl ₂ and N ₂ O as source gases. The temperature at the time of formation is 750 ° C. (FIG. 15 (g)).

Thereafter, a heat treatment at 850 ° C. was performed for 10 minutes in an NH ₃ atmosphere to introduce nitrogen atoms into the SiO ₂ film 213 (213 shown in FIG. 15 (g) corresponds to 2 shown in FIG. 15 (h)).
14).

Next, a polycrystalline Si film 215 doped with phosphorus is formed to a thickness of about 150 [nm], and is processed by a known technique to form a control gate (FIG. 16).
(i)).

Next, an SiO ₂ film 2 containing boron and phosphorus
No. 16 was formed and heat-treated in a nitrogen atmosphere at 850 ° C. to cause reflow. Thereafter, a contact hole reaching the source region 209 and the drain region 210 was formed in the SiO ₂ film 216 (not shown).

Next, a metal film 217 is formed by a sputtering method, which is processed into electrodes and wirings, and finally heat-treated in a hydrogen atmosphere to complete a memory cell (FIG. 16).
(j)).

[0102] SiH ₂ and Cl ₂ and SiO ₂ film was formed as the material gas, the contact-less array-type flash memory is used for the film polycrystalline Si interlayer insulating film where the heat treatment it in NH ₃ atmosphere, the SiH ₄ The charge retention characteristics after rewriting were improved as compared with the case where a SiO ₂ film was formed as a source gas and this was heat-treated in an NH ₃ atmosphere.

According to the present embodiment, a SiO ₂ film is formed using SiH ₂ Cl ₂ as a source gas, and a film heat-treated in an NH ₃ atmosphere is used as a polycrystalline Si interlayer insulating film of a contactless array type flash memory. By using such a structure, there is an effect that the charge retention characteristics after rewriting can be improved as compared with the related art.

[0104] Further, in the present embodiment, as in Embodiment 3, the polycrystalline Si interlayer insulating film, SiH ₂ Cl ₂ SiO ₂ film is formed as a raw material gas, film and Si ₃ heat-treated in a NH ₃ atmosphere Even when a stacked film of N ₄ films is used, the charge retention characteristics can be improved.

Further, regardless of the presence or absence of the Si ₃ N ₄ film, NH 3
The same effect can be obtained by performing wet oxidation after heat treatment in _three atmospheres.

As in the fourth embodiment, a SiO ₂ film / Si ₃ N ₄ film / SiO ₂ film (ONO)
Film), and any one of these SiO ₂ films is
The same effect can be obtained by forming H ₂ Cl ₂ as a source gas and performing heat treatment in an NH ₃ atmosphere. The same effect can be obtained by forming an Si ₃ N ₄ film after forming the ONO film and before forming the polycrystalline Si film 107 serving as a control gate. Further, one of the SiO ₂ films of the ONO film is
If a wet oxidation is performed after the heat treatment in the NH ₃ atmosphere after the formation using iH ₂ Cl ₂ , an even greater effect can be obtained on the improvement of the charge retention characteristics.

Note that the effects of the present invention are described in the first to fourth embodiments.
In the fifth embodiment, the description has been made using the memory cell of the contactless array type nonvolatile semiconductor memory device in the fifth embodiment. However, the same effect can be obtained with a NAND type, DiNOR type, or split gate type memory cell. .

In the first to fifth embodiments, the effect of the present invention has been described with the first gate electrode as the floating gate electrode and the second gate electrode as the control gate electrode. It is not limited to this. As shown in FIG. 17, for example, a similar effect can be obtained even if the first gate electrode is a floating gate electrode and the second gate electrode is a memory cell having an erase gate electrode. In this memory cell, in addition to the floating gate electrode 104 and the control gate electrode 107,
An erase gate electrode 118 is provided between adjacent control gates. FIG. 17 is a cross-sectional view perpendicular to the word lines, and a channel exists in a direction perpendicular to the paper surface (not shown). In this memory cell, writing is performed from the substrate 101 to the gate oxide film 10.
3, electrons are injected into the floating gate electrode 104. For erasing, electrons are emitted from the floating gate electrode 104 to the erase gate electrode 118 through the polycrystalline Si interlayer insulating film 116. In a conventional polycrystalline Si interlayer insulating film, a large number of electron traps exist in the film, and therefore, there is a problem that the number of rewrites increases, the tunnel current decreases, and the erase time increases. SiH as shown in Embodiments 1 to 5
_An SiO ₂ film is formed using ₂ Cl ₂ as a source gas,
A film heat-treated in an H ₃ atmosphere is converted to a polycrystalline Si interlayer insulating film 1
When used for 16, the number of electron traps in the film is reduced. As a result, an increase in the erasing time due to the rewriting can be suppressed.

In the first to fifth embodiments, the description has been made using the polycrystalline Si film as the two-layer Si film.
Similar effects can be obtained even with an amorphous Si film.

(Embodiment 6) In this embodiment, a MOSFET (field-effect transistor) in which a diffusion layer serving as a source and a drain is formed in a semiconductor substrate and a gate electrode is formed on the semiconductor substrate via a gate insulating film. 3), an example in which a SiO ₂ film is formed on the gate insulating film using SiH ₂ Cl ₂ as a source gas and the SiO ₂ film is heat-treated in an NH ₃ atmosphere will be described.

FIG. 18 shows a method of manufacturing a MOSFET.
This will be described with reference to FIG.

N of plane orientation (100) made of single crystal Si
A mold semiconductor substrate 301 is prepared, and thereafter, an oxide film 302 for element isolation is formed by a known selective oxidation method.
(a)).

Next, an SiO ₂ film 303 is formed by LPCVD using SiH ₂ Cl ₂ and N ₂ O as source gases.
(FIG. 18 (b)).

Next, immediately after performing the above steps, at 850 ° C.
NH ₃ heat-treated in an atmosphere of, the SiO ₂ film 303
A nitrogen atom is introduced therein (303 shown in FIG. 18B becomes 304 shown in FIG. 18C).

Next, a polycrystalline Si film 305 into which a p-type impurity (for example, boron) is introduced is formed on the SiO ₂ 304 by a film of about 150 [nm]. And CVDS by low pressure chemical vapor deposition.
The iO ₂ film 306 is formed with a thickness of about 150 [nm]. (FIG. 18D).

Next, the CVD SiO ₂ film 306 and the polycrystalline Si film 305 are processed by a known lithography technique and a dry etching technique to form a gate electrode (FIG. 18E).

Next, using the gate electrode as a mask for introducing impurities, a p-type impurity (for example, boron) is introduced by ion implantation to form a source region 307 and a drain region 308 (FIG. 19F).

Next, a CVD SiO ₂ film 309 was formed on the gate electrode by low pressure chemical vapor deposition to a thickness of 150 [n].
m]. Subsequently, the CVD SiO ₂ film 309 is etched by an anisotropic dry etching technique to form a sidewall insulating film 310 on a side wall of the gate electrode.
(FIG. 19 (g)).

Next, the entire surface of the main surface of the n-type semiconductor substrate 301 including the surface of the gate electrode is doped with sulfur containing boron and phosphorus.
iO to form a ₂ layer 311, then the SiO ₂ film 311
Then, a contact hole reaching the source region 307 and the drain region 308 is formed.

Next, a metal film 312 was formed by a sputtering method, and was processed into electrodes and wirings (FIG. 19H).

The MOSFET employs a case where a thermal oxide film is used as a gate insulating film, or a film obtained by forming an SiO ₂ film using SiH ₄ and N ₂ O as source gases and heat-treating the SiO ₂ film in an NH ₃ atmosphere. Hot carrier resistance was improved compared to the case where

According to this embodiment, a diffusion layer serving as a source and a drain is formed in a semiconductor substrate, and a gate electrode is formed on the semiconductor substrate via a gate insulating film.
In the OSFET, SiH ₂ C is formed on the gate insulating film.
SiO ₂ film is formed to l ₂ as a source gas, NH ₃ it
Use of a film that has been heat-treated in an atmosphere has the effect of improving hot carrier resistance.

(Embodiment 7) In this embodiment, the polycrystalline S
A SiO ₂ film is formed on a gate insulating film of a MOSFET (field effect transistor) having an i film as an active layer by LPCVD using SiH ₂ Cl ₂ as a source gas, and a film heat-treated in an NH ₃ atmosphere is used. An example will be described. In addition,
In this embodiment, a gate insulating film refers to an insulating film provided between an active layer and a gate electrode.

FIG. 20 and FIG.
It is shown in FIG.

First, the plane orientation (10
0), an n-type semiconductor substrate 401 is prepared.
An iO ₂ film 402 is formed (FIG. 20A).

Next, a MOSF is formed on the SiO ₂ film 402.
A polycrystalline Si film 403 serving as an active layer of ET is formed (FIG. 20B).

Next, an SiO ₂ film 404 to be used as a gate insulating film is formed on the SiO ₂ film 403 by, for example, 8 [n].
m]. The SiO ₂ film 404 is formed by LPCVD using SiH ₂ Cl ₂ and N ₂ O as source gases.
Method so that chlorine atoms are present in the film. (FIG. 20 (c)).

Next, immediately after performing the above steps, at 850 ° C.
Is performed in an NH ₃ atmosphere to introduce nitrogen atoms into the SiO ₂ film 404 (404 shown in FIG.
0 (d) becomes 405).

Next, on the SiO ₂ film 405, a polycrystalline Si film 406 into which a p-type impurity (for example, boron) is introduced.
Is formed (FIG. 21E).

Next, the polycrystalline Si film 406 is processed by known lithography and dry etching techniques.
A gate electrode is formed (FIG. 21F).

Next, using the gate electrode 406 as an impurity introduction mask, a p-type impurity (for example, boron) is introduced into the polycrystalline Si film 403 by ion implantation to form a source region 407 and a drain region 408. . In this step, a MOSFET is formed (FIG. 21).
(g)).

Next, an SiO ₂ film 409 containing boron and phosphorus is formed on the entire surface of the main surface of the n-type semiconductor substrate 401 including the surface of the gate electrode 406, and then a source region is formed on the SiO ₂ film 409. 407, a contact hole reaching the drain region 408 is formed.

Next, a metal film 410 was formed by a sputtering method, and this was processed into electrodes and wirings (FIG. 21H).

The MOSFET employs a case where a thermal oxide film is used as a gate insulating film, or a film obtained by forming an SiO ₂ film using SiH ₄ and N ₂ O as a source gas and heat-treating the SiO ₂ film in an NH ₃ atmosphere. Leakage current during standby was reduced as compared with the case where At the same time, the operating current increased. As a result, a high on / off ratio was obtained.

According to this embodiment, SiH _{2 is used} as a gate insulating film of a MOSFET having a polycrystalline Si film as an active layer.
A SiO ₂ film is formed using Cl ₂ as a source gas,
By using a film heat-treated in ₃ atmospheres, MO
There is an effect that the on / off ratio of the SFET can be improved.

In this embodiment, the MOSFET using the polycrystalline Si film as the active layer is formed on the semiconductor substrate with the SiO ₂ film interposed therebetween. The same effect can be obtained even if it is formed above.

In this embodiment, the lower polycrystalline Si
The MOSFET using the film as an active layer and the upper polycrystalline Si film as a gate electrode has been described.
Similar effects can be obtained in a MOSFET in which the film is used as a gate electrode and the upper polycrystalline Si film is used as an active layer.

Further, in Embodiments 6 and 7, when a SiO ₂ film is formed using SiH ₂ Cl ₂ as a source gas, this is heat-treated in an NH ₃ atmosphere, and then wet oxidation is performed, a further higher effect is obtained. can get.

In the sixth and seventh embodiments, the p-channel conductive type MOSFET has been described. However, the same effect can be obtained in the n-channel conductive type MOSFET.

In the sixth and seventh embodiments, a polycrystalline Si film has been described as a gate electrode. However, similar effects can be obtained with an amorphous Si film.

In the first to seventh embodiments, Si
In forming the O ₂ film, SiH ₂ Cl ₂ and N ₂ O were used as source gases, but the same effect can be obtained by using NO or NO ₂ instead of N ₂ O. Further, other gases may be used as long as the effects of the present invention can be obtained.

As described above, the invention made by the present inventors is described below.
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

For example, according to the present invention, a lower polycrystalline Si film or an amorphous Si film is used as a lower electrode, an upper polycrystalline Si film or an amorphous Si film is used as an upper electrode, and SiO ₂ between them is used.
May be applied to a semiconductor device having a capacitive element using as a dielectric film. In this case, the charge retention characteristics of the capacitor can be improved.

The present invention may be applied to a one-chip microcomputer (semiconductor device) provided with a memory cell array having a flash memory.

[0145]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

The charge retention characteristics of the flash memory can be improved.

In addition, the performance of a field effect transistor mounted on a semiconductor device can be improved.

In addition, the charge retention characteristics of a capacitor mounted on a semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a method for manufacturing a flash memory according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a method of manufacturing the flash memory.

FIG. 3 is a diagram showing a decrease in threshold voltage.

FIG. 4 is a diagram showing a trap charge amount of an interlayer insulating film.

FIG. 5 is a view for explaining a method for manufacturing a flash memory according to the second embodiment of the present invention;

FIG. 6 is a diagram for explaining a method of manufacturing the flash memory.

FIG. 7 is a view illustrating a method for manufacturing the flash memory.

FIG. 8 is a view illustrating a method of manufacturing a flash memory according to Embodiment 3 of the present invention;

FIG. 9 is a view illustrating a method of manufacturing the flash memory.

FIG. 10 is a view illustrating a method for manufacturing the flash memory.

FIG. 11 is a view illustrating a method of manufacturing a flash memory according to Embodiment 4 of the present invention;

FIG. 12 is a view illustrating a method for manufacturing the flash memory.

FIG. 13 is a view illustrating a method of manufacturing the flash memory.

FIG. 14 is a view illustrating a method of manufacturing the flash memory according to the fifth embodiment of the present invention.

FIG. 15 is a view illustrating a method of manufacturing the flash memory.

FIG. 16 is a view illustrating a method for manufacturing the flash memory.

FIG. 17 is a diagram showing a flash memory having an erase gate electrode.

FIG. 18 is a view illustrating a method for manufacturing the MOSFET according to the sixth embodiment of the present invention.

FIG. 19 is a view illustrating a method of manufacturing the MOSFET.

FIG. 20 is a view illustrating a method for manufacturing the MOSFET according to the seventh embodiment of the present invention.

FIG. 21 is a diagram illustrating a method for manufacturing the MOSFET.

[Explanation of symbols]

101: p-type substrate, 102: oxide film for element isolation, 103
... Gate oxide film, 104, 107, 118 ... Polycrystalline Si film doped with phosphorus, 105, 115 ... CVDSi
O ₂ film, 106, 116... CVD SiO after NH ₃ heat treatment
₂ film, 108: punch-through stopper region, 109: source region, 110: drain region, 111: SiO ₂ film containing boron and phosphorus, 112: metal film, 113: N
CVD SiO ₂ film after H ₃ heat treatment and wet oxidation, 11
4 ... Si ₃ N ₄ film 115 ... floating gate electrode - polycrystalline S between the control gate electrode
i interlayer insulating film 116: polycrystalline S between floating gate electrode and control gate electrode
i interlayer insulating film 117: SiO ₂ film for preventing channel inversion, 201: p-type substrate, 202: gate insulating film, 203, 212, 215
... A polycrystalline Si film doped with phosphorus, 207 an oxide film for element isolation, 208 a punch-through stopper region, 20
9: source region, 210: drain region, 211: CV
DSiO2 film, 213 ... CVD SiO2 film, 214 ... N
H ₃ after heat treatment of the CVD SiO ₂ film, 216 ... SiO ₂ film containing boron and phosphorus, 217 ... metal film 301 ... n-type substrate, 302 ... isolation oxide film 303 ... CVD SiO2 film, 304 ... NH ₃ after heat treatment CVD SiO ₂ film, 305: polycrystalline Si film, 306, 3
09, 310: CVD SiO ₂ film, 307: source region, 308: drain region, 311: SiO ₂ film containing boron and phosphorus, 312: metal film 401: n-type substrate, 402: SiO 2 film, 403, 40
6 ... polycrystalline Si film, 404 ... CVD SiO2 film, 405
... CVD SiO ₂ film after NH ₃ heat treatment, 407 source region, 408 drain region, 409 SiO ₂ film containing boron and phosphorus, 410 metal film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/786 21/336 // H01L 21/318 (72) Inventor Takashi Kobayashi 1-chome Higashi Koigakubo, Kokubunji-shi, Tokyo 280 Hitachi Central Research Laboratory Co., Ltd. (72) Toshiyuki Mine 1-chome Higashi Koikekubo, Kokubunji-shi, Tokyo 280 Hitachi Central Co., Ltd. (72) Inventor Toshio Uemura 5--22 Kamimizuhoncho, Kodaira-shi, Tokyo No. 1 F-term in Hitachi Ultra-LII Systems Inc. (reference) 5F001 AA01 AA41 AA43 AA63 AB07 AB08 AD15 AD18 AD23 AF06 AF07 AG10 AG12 AG21 AG29 AG30 AG31 AG32 AH04 5F040 DA18 DA19 DB09 EA08 EC07 ED03 EJ04 EK02 FA12 5F058 BA11 BA20 BB04 BC02 BC11 BD02 BD03 BD09 BF04 BH02 BH11 5F083 AD11 BS29 EP02 EP23 EP64 ER22 GA21 GA30 JA32 JA33 PR03 PR0 5 PR12 PR21 PR33 PR36

Claims (26)

[Claims] 1. A method for manufacturing a semiconductor device, comprising: a two-layered silicon film on a main surface of a semiconductor substrate; and a silicon oxide film between the two-layered silicon film. Forming a silicon oxide film by a reduced pressure chemical vapor deposition method using dichlorosilane as a source gas, and immediately thereafter, performing a heat treatment on the silicon oxide film in an ammonia atmosphere, and subsequently forming an upper silicon film. A method for manufacturing a semiconductor device. 2. A method for manufacturing a semiconductor device, comprising: a two-layer silicon film on a main surface of a semiconductor substrate; and a silicon oxide film between the two-layer silicon film. And forming a silicon oxide film by a reduced pressure chemical vapor deposition method using dichlorosilane as a source gas. Immediately thereafter, the silicon oxide film is subjected to a heat treatment in an ammonia atmosphere. A method for manufacturing a semiconductor device, comprising: forming a film, and subsequently forming an upper silicon film. 3. The method according to claim 1, wherein a wet oxidation is performed after the silicon oxide film is subjected to a heat treatment in an ammonia atmosphere. 4. The device according to claim 1, wherein one of the two silicon layers is a floating gate electrode of the nonvolatile memory element and the other is a control gate electrode. Of manufacturing a semiconductor device. 5. The semiconductor device according to claim 1, wherein one of the two silicon films is a floating gate electrode of the nonvolatile memory element, and the other is an erase gate electrode. Of manufacturing a semiconductor device. 6. A diffusion layer serving as a source and a drain is formed in a semiconductor substrate, a first gate electrode is formed on the semiconductor substrate via an insulating film, and an insulating film is formed on the first gate electrode. A method for manufacturing a semiconductor device having a non-volatile memory element having a second gate electrode formed therethrough, comprising: forming a silicon film to be a first gate electrode; processing the silicon film into a desired shape; A silicon oxide film by low pressure chemical vapor deposition using
Immediately thereafter, a heat treatment is performed on the silicon oxide film in an ammonia atmosphere, and subsequently, a silicon film serving as a second gate electrode is formed. 7. A diffusion layer serving as a source and a drain is formed in a semiconductor substrate, a first gate electrode is formed on the semiconductor substrate via an insulating film, and an insulating film is formed on the first gate electrode. A method of manufacturing a semiconductor device having a non-volatile memory element having a second gate electrode formed therethrough, comprising: forming a silicon film to be a first gate electrode; processing the silicon film into a desired shape; A silicon oxide film by low pressure chemical vapor deposition using
Immediately thereafter, the silicon oxide film is subjected to a heat treatment in an ammonia atmosphere, and thereafter, a silicon nitride film is formed by a low pressure chemical vapor deposition method, and subsequently, a silicon film to be a second gate electrode is formed. Semiconductor device manufacturing method. 8. The method according to claim 6, wherein a wet oxidation is performed after the silicon oxide film is subjected to a heat treatment in an ammonia atmosphere. 9. A diffusion layer serving as a source and a drain is formed in a semiconductor substrate, a first gate electrode is formed on the semiconductor substrate via an insulating film, and an insulating film is formed on the first gate electrode. A method of manufacturing a semiconductor device having a non-volatile memory element having a second gate electrode formed therethrough, comprising: forming a silicon film to be a first gate electrode; processing the silicon film into a desired shape; A silicon oxide film by low pressure chemical vapor deposition using
Immediately thereafter, the silicon oxide film is subjected to a heat treatment in an ammonia atmosphere, and thereafter, a silicon nitride film is formed by a low pressure chemical vapor deposition method, and thereafter, a silicon oxide film is formed, and then a second gate electrode is formed. A method for manufacturing a semiconductor device, comprising forming a silicon film. 10. A diffusion layer serving as a source and a drain is formed in a semiconductor substrate, a first gate electrode is formed on the semiconductor substrate via an insulating film, and an insulating film is formed on the first gate electrode. A method of manufacturing a semiconductor device having a non-volatile memory element having a second gate electrode formed therethrough, comprising: forming a silicon film to be a first gate electrode; processing the silicon film into a desired shape; A silicon oxide film by low pressure chemical vapor deposition using
Immediately thereafter, the silicon oxide film is subjected to a heat treatment in an ammonia atmosphere, and thereafter, a silicon nitride film is formed by a reduced pressure chemical vapor deposition method, and then, a silicon oxide film is formed, and then, a low pressure chemical vapor deposition method is used. A method for manufacturing a semiconductor device, comprising: forming a silicon nitride film; and subsequently forming a silicon film to be a second gate electrode. 11. A diffusion layer serving as a source and a drain is formed in a semiconductor substrate, a first gate electrode is formed on the semiconductor substrate via an insulating film, and an insulating film is formed on the first gate electrode. A method of manufacturing a semiconductor device having a non-volatile memory element having a second gate electrode formed therethrough, comprising: forming a silicon film to be a first gate electrode; processing the silicon film into a desired shape; A silicon oxide film by low pressure chemical vapor deposition using
Immediately thereafter, the silicon oxide film is subjected to a heat treatment in an ammonia atmosphere, and thereafter, a silicon nitride film is formed by a reduced pressure chemical vapor deposition method, and then the silicon oxide film is formed by a reduced pressure chemical vapor deposition method using dichlorosilane as a source gas. And immediately after that, a heat treatment is performed on the silicon oxide film in an ammonia atmosphere, and subsequently, a silicon film to be a second gate electrode is formed. 12. A diffusion layer serving as a source and a drain is formed in a semiconductor substrate, a first gate electrode is formed on the semiconductor substrate via an insulating film, and an insulating film is formed on the first gate electrode. A method for manufacturing a semiconductor device having a non-volatile memory element having a second gate electrode formed therethrough, comprising: forming a silicon film to be a first gate electrode; processing the silicon film into a desired shape; A silicon oxide film by low pressure chemical vapor deposition using
Immediately thereafter, the silicon oxide film is subjected to a heat treatment in an ammonia atmosphere, and thereafter, a silicon nitride film is formed by a reduced pressure chemical vapor deposition method, and then the silicon oxide film is formed by a reduced pressure chemical vapor deposition method using dichlorosilane as a source gas. Immediately thereafter, the silicon oxide film is subjected to a heat treatment in an ammonia atmosphere, and thereafter, a silicon nitride film is formed by a low pressure chemical vapor deposition method, and then a silicon film to be a second gate electrode is formed. A method for manufacturing a semiconductor device, comprising: 13. A diffusion layer serving as a source and a drain is formed in a semiconductor substrate, a first gate electrode is formed on the semiconductor substrate via an insulating film, and an insulating film is formed on the first gate electrode. A method of manufacturing a semiconductor device having a non-volatile memory element having a second gate electrode formed therethrough, comprising: forming a silicon film to be a first gate electrode; processing the silicon film into a desired shape; A silicon film is formed, then a silicon nitride film is formed by a low pressure chemical vapor deposition method, and then a silicon oxide film is formed by a low pressure chemical vapor deposition method using dichlorosilane as a source gas. A method for manufacturing a semiconductor device, comprising: subjecting a film to a heat treatment in an ammonia atmosphere, and subsequently forming a silicon film to be a second gate electrode. 14. A diffusion layer serving as a source and a drain is formed in a semiconductor substrate, a first gate electrode is formed on the semiconductor substrate via an insulating film, and an insulating film is formed on the first gate electrode. A method of manufacturing a semiconductor device having a non-volatile memory element having a second gate electrode formed therethrough, comprising: forming a silicon film to be a first gate electrode; processing the silicon film into a desired shape; A silicon film is formed, then a silicon nitride film is formed by a low pressure chemical vapor deposition method, and then a silicon oxide film is formed by a low pressure chemical vapor deposition method using dichlorosilane as a source gas. The film is subjected to a heat treatment in an ammonia atmosphere, and thereafter, a silicon nitride film is formed by a low pressure chemical vapor deposition method, and subsequently, a silicon film to be a second gate electrode is formed. The method of manufacturing a semiconductor device according to. 15. The method according to claim 9, wherein wet oxidation is performed after the heat treatment in the ammonia atmosphere. 16. The semiconductor according to claim 6, wherein the first gate electrode is a floating gate electrode, and the second gate electrode is a control gate electrode. Device manufacturing method. 17. The semiconductor according to claim 6, wherein the first gate electrode is a floating gate electrode, and the second gate electrode is an erase gate electrode. Device manufacturing method. 18. A method for manufacturing a semiconductor device having a field-effect transistor in which a diffusion layer serving as a source and a drain is formed in a semiconductor substrate and a gate electrode is formed on the semiconductor substrate via a silicon oxide film. A method for manufacturing a semiconductor device, comprising: forming the silicon oxide film by a reduced pressure chemical vapor deposition method using digluolsilane as a source gas, and thereafter performing a heat treatment in an ammonia atmosphere. 19. The method according to claim 18, wherein wet oxidation is performed after the heat treatment in the ammonia atmosphere. 20. A method of manufacturing a semiconductor device having a field-effect transistor in which a silicon oxide film is provided between an active layer made of a silicon film and a gate electrode, wherein the silicon oxide film is made of dichlorosilane as a source gas. A method for manufacturing a semiconductor device, comprising: forming a substrate by a low pressure chemical vapor deposition method; and thereafter performing a heat treatment in an ammonia atmosphere. 21. The method according to claim 20, wherein wet oxidation is performed after the heat treatment is performed in the ammonia atmosphere. 22. A method of manufacturing a semiconductor device having a capacitor in which a dielectric film made of a silicon oxide film is provided between a lower electrode and an upper electrode, wherein the silicon oxide film is made of dichlorosilane as a source gas. A method for manufacturing a semiconductor device, comprising: forming a substrate by a low pressure chemical vapor deposition method; and thereafter performing a heat treatment in an ammonia atmosphere. 23. The method according to claim 22, wherein wet oxidation is performed after the heat treatment in the ammonia atmosphere. 24. When forming a silicon oxide film by a reduced pressure chemical vapor deposition method using dichlorosilane as a source gas, at least one of nitrous oxide, nitric oxide and nitrogen dioxide is combined as a source gas. The method of manufacturing a semiconductor device according to claim 1, wherein the method is used. 25. A semiconductor device having a capacitor in which a dielectric film is provided between a lower electrode and an upper electrode, wherein each of the lower electrode and the upper electrode is a polycrystalline silicon film or an amorphous silicon film. Wherein the dielectric film is formed of a silicon oxide film in which chlorine atoms and nitrogen atoms are present at the same time. 26. A semiconductor device in which a two-layered silicon film exists on a main surface of a semiconductor substrate, and a silicon oxide film exists between the two-layered silicon film, wherein one of the two-layered silicon film is provided. Is a floating gate electrode of a nonvolatile memory element, and the other is an erase gate electrode, wherein chlorine atoms and nitrogen atoms are simultaneously present in the silicon oxide film.