JP4224000B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device having a MIS type structure. Furthermore, the present invention particularly relates to a nonvolatile semiconductor memory device and a manufacturing method thereof.

  The nonvolatile semiconductor memory device is usually configured as a semiconductor integrated circuit device. A typical example is a flash memory device that can be electrically written and erased. This flash memory device is disclosed in, for example, Japanese Patent Laid-Open No. 62-276878 (Patent Document 1), Japanese Patent Laid-Open No. 3-219496 (Patent Document 2) or IEDM, 1992 92-991 to 92-993. In the paper “A1.28 μm 2 Contactless Memory Cell Technology for a 3V-Only 64 Mbit EEPROM” (Non-patent Document 1).

  FIG. 10 shows a cross-sectional structure of the main part of an example of such a flash memory device. A so-called stack structure is widely used as the main part of the memory. The stack structure is a general name of a general form in which a capacitor provided for storage is mounted on an electrical switch circuit, for example. In FIG. 10, 601 is a single crystal Si substrate, 602 is an element isolation oxide film, 603 is a gate oxide film (tunnel insulating film), 606 is a floating gate electrode, 607 is an interlayer insulating film, 608 is a control gate electrode, and 610 is a source. 611, drain, 609, 612, 613, insulating film, 614, source wiring, and 615, drain wiring.

The configuration of the main part of the memory will be described in detail below. As the gate oxide film 603, a silicon oxide film having a thickness of 7.5 nm to 10 nm is used. This silicon oxide film is usually formed by thermally oxidizing a Si substrate. The floating gate electrode 606 is a polycrystalline Si film containing phosphorus at a high concentration, and the film thickness is about 50 nm to 200 nm. As the interlayer insulating film 607, a laminated film 607 of SiO ₂ film / Si ₃ N ₄ film / SiO ₂ film formed by low pressure chemical vapor deposition (hereinafter referred to as LP-CVD) is used. This laminated film 607 is called a so-called ONO film (hereinafter, this film is abbreviated as ONO film).

  The first state of the information in the flash memory, for example, writing is performed by the following method. The drain 611 is set to a positive bias (for example, + 4V), the control gate electrode 608 is set to a negative bias (for example, −10V), the source 610 is opened, while the Si substrate 601 is set to 0V. In this state, electrons accumulated in the floating gate electrode 606 are extracted to the drain 611 side, and information is written. Each of the above voltages is applied using a pulse having a width of about 100 microseconds. According to this method, electrons in the floating gate electrode 606 are extracted to the drain 611 side by a Fowler-Nordheim tunnel current (hereinafter abbreviated as FN current).

  The second state of information, for example, erasure is performed by the following method. The control gate electrode 608 is set to a positive bias (for example, +10 V), the Si substrate 601 is set to a negative bias (for example, −4 V), and the source 610 and the drain 611 are set to an open state. In this state, electrons are injected from the Si substrate 601 to the floating gate electrode 606 to erase information. Each voltage is applied using a pulse having a width of about 100 microseconds.

  As the information holding state, the first and second states are referred to as writing and erasing, respectively. However, the same charge state may be called in reverse. This depends on the operating method. However, the problem is similar. Hereinafter, for convenience, the above names are used for the state of charge. This is to facilitate understanding of the contents of the specification. It is needless to say that the operation method of the reverse designation is also included in the present invention as the charge state in this specification is read as the charge state.

JP-A-62-276878 Japanese Patent Application Laid-Open No. 3-219396 IEDM, 1992, KUME “A1.28μm2 Contactless Memory Cell Technology for a 3V-Only 64Mbit EEPROM” (92-991 to 92-993) IEE Electron Device Letters Vol.12 No.11 1991 (IEEE ELECTRON DEVICE LETTERS, Vol.12, No.11, November 1991) (p587)

  Information rewriting in the flash memory is performed by injecting and extracting electrons from the floating gate electrode through the gate insulating film. This rewriting time depends on the amount of FN current flowing in the gate insulating film. Since this FN current amount greatly depends on the film thickness of the gate insulating film, the thinner the gate insulating film, the shorter the rewriting time. However, the thinning of the gate insulating film induces the following problems. The outline of the problem will be described below with reference to the drawings.

  FIG. 15 is a diagram showing the electric field-current characteristics of the MOS capacitor before and after applying a constant current (FN current) stress. The stress application means a method for acceleratingly testing a state in which stress is applied in a mounted actual state. That is, this method injects a predetermined amount of charge into a memory cell and compares the memory characteristics before and after the charge injection. In this case, charge injection is referred to as stress application.

In FIG. 15, the solid line indicates the characteristic before the stress is applied, and the dotted line indicates the characteristic after the stress is applied. In this example, the injection current density is 0.1 A / cm ² and the injection charge amount is 1 C / cm ² . As is apparent from FIG. 15, after applying stress, the leakage current increases in a low electric field region (for example, ± 8 MV / cm or less). This is because when FN current injection is performed on the gate insulating film for applying stress, holes or the like injected into the gate insulating film form new levels in the gate insulating film. This is because the leakage current through this level increases.

  This leakage current in the low electric field region is a main cause of deterioration of charge retention characteristics of the rush memory. That is, the specific cause of the deterioration of the charge retention characteristic is generally called a retention failure of the flash memory (a charge leaks from the floating gate to the substrate side) or a disturbance failure (a charge leaks from the substrate side to the floating gate side). Is.

  FIG. 16 is a diagram showing the relationship between the thickness of the gate insulating film and the current density in the flash memory cell. The black dot characteristic represents the relationship between the gate insulating film thickness and the FN current, and the white dot characteristic represents the relationship between the gate insulating film thickness and the leakage current in a low electric field. As understood from FIG. 16, the leakage current in the low electric field can be suppressed by increasing the thickness of the gate insulating film. However, the leakage current and the FN current in a low electric field have a trade-off relationship with the film thickness of the gate insulating film. Therefore, when the gate insulating film is thickened, the FN current decreases, and a new problem of increasing the rewriting time occurs.

  As one means for solving this problem, a method of suppressing a leakage current in a low electric field by using an oxynitride film in which a small amount of nitrogen is introduced into a conventional thermal oxide film has been proposed. For example, IEE Electron Device Letters, Vol. 12, No. 11, 1991 (IEEE ELECTRON DEVICE LETTERS, Vol. 12, No. 11, p587, November 1991) (Non-Patent Document 2). However, even if this method is used, a sufficient level for guaranteeing the charge retention characteristic has not yet been reached.

  An object of the present invention is to provide a nonvolatile semiconductor device in which a FN current is increased while suppressing a leakage current in a low electric field of a gate insulating film due to a rewrite operation. Furthermore, the object of the present invention is to provide a manufacturing method thereof. Therefore, the present invention can provide a highly reliable and high-speed rewritable nonvolatile semiconductor device.

  The outline of a representative example of the invention disclosed in this specification will be described as follows.

  One form of the semiconductor device of the present invention has the following characteristics. That is, the floating gate electrode is formed through a non-single crystal silicon film having an average film thickness of 10 nm or less, more preferably 8 nm or less, and at least a part of which is laminated on the floating gate electrode. This is an electrically rewritable nonvolatile semiconductor device having at least a control gate electrode provided through an interlayer insulating film. The effect of the present invention is recognized when the average film thickness is 10 nm or less. The effect appears remarkably when the average film thickness is 8 nm or less.

  Another embodiment of the semiconductor device of the present invention has the following characteristics. That is, it includes a floating gate electrode made of an amorphous silicon film provided via a gate insulating film, and a control gate electrode provided via an interlayer insulating film in such a manner that at least a part of the floating gate electrode is laminated on the floating gate electrode And an electrically rewritable nonvolatile semiconductor device.

  The non-single-crystal silicon refers to polycrystalline silicon, amorphous silicon, or a mixed form of both. Polycrystalline silicon is the easiest to use based on the manufacturing process and manufacturing method in the field of semiconductor devices.

  Still another embodiment of the semiconductor device of the present invention is as follows. That is, it is provided via the interlayer insulating film in a form in which at least a part is stacked on the floating gate electrode provided via the gate insulating film and composed of a plurality of conductors or semiconductor films. The nonvolatile semiconductor device has at least a control gate electrode and is electrically rewritable. Of the layers constituting the floating gate electrode, a non-single-crystal silicon film having an average film thickness of 10 nm or less, more preferably an average film thickness of 8 nm or less is in contact with the gate insulating film. The effect of the present invention is recognized when the average film thickness is 10 nm or less. The effect appears remarkably when the average film thickness is 8 nm or less.

  Still another embodiment of the semiconductor device of the present invention is as follows. That is, it is provided via the interlayer insulating film in a form in which at least a part is stacked on the floating gate electrode provided via the gate insulating film and composed of a plurality of conductors or semiconductor films. The nonvolatile semiconductor device has at least a control gate electrode and is electrically rewritable. Of the layers constituting the floating gate electrode, the layer in contact with the gate insulating film is an amorphous silicon film.

  Note that non-single-crystal silicon refers to polycrystalline silicon, amorphous silicon, or a mixed form of both. Polycrystalline silicon is the easiest to use based on the manufacturing process and manufacturing method in the field of semiconductor devices.

  Of the two or more conductors or semiconductor materials constituting the floating gate electrode, the layers other than the layer in contact with the gate insulating film may be materials used as a material for the floating gate in a typical semiconductor memory device. For example, silicon can be used as the semiconductor material, and polycrystalline silicon, tungsten, or titanium nitride containing impurities at a high concentration can be used as the conductor.

  In the floating gate electrode, a polycrystalline silicon film containing phosphorus (P) or arsenic (As) is frequently used as the silicon film above the layer in contact with the gate insulating film.

  The thickness of the layer in contact with the gate insulating film of the floating gate electrode is preferably 8 nm or less in the case of polycrystalline silicon. The average grain size of polycrystalline silicon is more preferably 20 nm or less. On the other hand, in the case of amorphous silicon, the range of 8 nm or less is preferable. The total thickness of the floating gate electrode is sufficient as a typical thickness in a nonvolatile semiconductor memory device.

  According to another aspect of the semiconductor device of the present invention, the floating gate electrode provided via the gate insulating film, and the control provided via the interlayer insulating film in a form where at least a part of the floating gate electrode is laminated. At least a gate electrode, wherein the floating gate electrode is composed of two or more layers of conductors or semiconductor films processed using the same mask, and the thin film of the layer in contact with the gate insulating film has an average film thickness of 10 nm or less, More preferably, the electrically rewritable nonvolatile semiconductor device is a silicon film having an average film thickness of 8 nm or less.

  In this case, the thickness of the layer in contact with the gate insulating film of the floating gate electrode is extremely preferably in the range of 8 nm or less in the case of polycrystalline silicon. The average grain size of this polycrystalline silicon is more preferably 20 nm or less. On the other hand, in the case of amorphous silicon, the thickness of the layer in contact with the gate insulating film of the floating gate electrode is extremely preferably in the range of 8 nm or less.

  The thickness of the entire floating gate electrode is sufficient as a usual thickness. In the floating gate electrode, a polycrystalline silicon film containing phosphorus (P) or arsenic (As) is frequently used as the silicon film above the layer in contact with the gate insulating film.

The present invention has been made based on the following knowledge about the gate insulating film.
(1) The relationship between the FN current of the MOS capacitor and the thickness of the polycrystalline Si film serving as the gate electrode was examined. As a result, it has been found that when the thickness of the polycrystalline Si film is thinner than about 8 nm, the FN current is remarkably increased.
(2) The inventors have obtained knowledge that the same effect as the above (1) can be obtained even when the gate electrode in contact with the gate insulating film is an amorphous Si film.

  The reason for this phenomenon is considered as follows. That is, for example, when an insulator such as oxygen or nitrogen on the surface of the polycrystalline silicon film is subjected to a high-temperature heat treatment, the interface of the silicon grains diffuses and the back surface of the polycrystalline silicon film (that is, the gate insulating film side). Reach the surface). At this time, it reacts with the silicon film on the back surface to form a new insulator film. This phenomenon tends to occur along the grain boundary. For this reason, the back surface of the polycrystalline silicon has fine irregularities. As a result, it is considered that when an electric field is applied, electric field concentration occurs in the fine protrusions, and the F-N current increases remarkably.

  Further, in the above-described embodiment of the present invention, when an amorphous silicon film and another gate material are used, a thin film made of an amorphous silicon film and another gate material in contact with the gate insulator layer, that is, a conductor film or a semiconductor. A thin layer of insulator exists at the interface with the film. This thin layer of insulator is often a silicon oxide film, a silicon nitride film, or a composite film thereof. And the thickness of the thin layer of this insulator is 0.3 nm or more and 1 nm or less. Of these insulators, the thermal oxide layer is most useful.

In general, it is recognized that crystallization of an amorphous Si film proceeds at a temperature of 600 to 650 ° C. or higher. However, we have found that when an insulating film is present on the film surface, a very thin amorphous silicon film having a film thickness of about 8 nm or less has a high crystallization temperature. Specifically, an amorphous silicon film having a thickness of about 8 nm or less formed at a temperature of about 480 ° C. or less by a low pressure chemical vapor deposition method using disilane (Si ₂ H ₆ ) has a temperature of about 800 ° C. or less. The knowledge that it does not crystallize at the heat treatment temperature was obtained. However, this phenomenon is limited to the case where an insulating film of about 0.3 nm or more exists on the surface of the amorphous silicon film. If a field effect transistor is manufactured by a process of 800 ° C. or less utilizing the above phenomenon, a gate electrode made of an amorphous silicon film can be formed.

  The effects obtained by typical inventions among those disclosed in the present application will be described as follows.

  The rewrite current (F-N current) can be greatly increased without increasing the low electric field leakage current of a flash memory typified by a nonvolatile semiconductor device. An increase in the rewriting current (F-N current) brings about an improvement in the rewriting time.

  In addition, the breakdown life of the gate insulating film is greatly improved.

  As a result, a highly reliable nonvolatile semiconductor memory device in which the rewriting time is significantly improved as compared with the conventional method can be provided.

  First, a comparative experiment using a capacitor as the basis of the present invention will be described.

  Three types of planar capacitor structures were prepared in order to compare characteristics such as current-voltage characteristics (IV characteristics) of MOS capacitors. These sectional views are shown in FIGS. FIG. 1 shows a structure corresponding to the present invention. In the figure, the reference number 100 indicates the case where the lower gate Si film is a polycrystalline Si film, and the reference number 200 indicates the case where the lower gate silicon film is an amorphous Si film. Both geometric shapes are the same. FIG. 2 is a cross-sectional view showing a conventional capacitor structure. FIG. 3 shows the sample conditions for comparing the differences in the processes.

  First, element isolation oxide films 102, 202, and 302 of 500 nm are formed on each of P-type single crystal Si substrates 101, 201, and 301 by a well-known LOCOS method. Next, a gate insulating film having a thickness of 7.7 nm is formed by a pyrogenic oxidation method at 850 ° C. In FIGS. 1 and 2, the gate oxide films are indicated as 103, 203, and 303, respectively. Each sample of this comparative experiment is shown in FIG.

  Next, no. 1 and No. Sample 6 is a conventional gate electrode.

The gate electrode of these samples is a 200 nm phosphorus-doped amorphous Si film 306. The phosphorus-doped amorphous Si film 306 is formed by a low pressure chemical vapor deposition method (hereinafter referred to as LP-CVD method) using Si ₂ H ₆ and phosphine (PH ₃ ). Phosphorus was contained at a concentration of 3 × 10 ²⁰ / cm ³ (FIG. 2).

On the other hand, no. 2-No. 5 and no. Each sample 7 has a laminated structure of a non-doped amorphous Si film, a SiO ₂ film, and a phosphorus-doped amorphous Si film.

The specific thickness of each layer is as follows. The film thickness of the non-doped amorphous Si films 104 and 204 is _{2 to} 8 nm, the film thickness of the SiO ₂ films 105 and 204 is 0.5 nm, and the film thickness of the phosphorus-doped amorphous Si films 106 and 206 is 200 nm. These layers were successively formed in the same apparatus. The details will be described below.

First, non-doped amorphous Si films 104 and 205 were deposited on the gate oxide films 103 and 203 by LP-CVD using Si ₂ H ₆ . A vertical LP-CVD apparatus having a load lock mechanism was used as the deposition apparatus. The deposition temperature was 420 ° C., the deposition pressure was 70 Pa, and the flow rate of Si ₂ H ₆ was 150 cc / min. It was formed by simultaneously flowing nitrogen as a carrier gas. The flow rate of this nitrogen is 2000 cc / min.

The film thicknesses of the amorphous Si films 104 and 204 were controlled by the time for introducing Si ₂ H ₆ gas. The amorphous Si film in each sample is as follows. Sample No. 2 is 2 nm. 3 is 4 nm. 4 is 6 nm, and no. 5 is 8 nm (see FIG. 3). Subsequently, the Si 2 H 6 gas was shut off and the inside of the reaction furnace was evacuated, and then oxygen gas was flowed into the furnace to form SiO ₂ films 105 and 205 on the surfaces of the amorphous Si films 104 and 204 in a reduced-pressure oxygen atmosphere. The film thicknesses of the SiO ₂ films 105 and 205 can be controlled by the oxygen partial pressure and time. In this embodiment, the thickness of the SiO ₂ films 105 and 205 is 0.5 nm. Subsequently, the temperature inside the furnace was raised to 525 ° C. in reduced-pressure nitrogen, and amorphous Si films 106 and 206 containing 3 × 10 ²⁰ / cm ^{3 of} phosphorus were deposited to a thickness of 200 nm. Also in this sample, Si ₂ H ₆ and PH ₃ were used for forming the phosphorus-doped amorphous Si films 106 and 206, and deposition was performed under the same conditions as the phosphorus-doped amorphous film 306 described above.

  As a result of examining the formation method of the non-doped amorphous Si films 104 and 204 in this experiment, when the deposition is performed at a temperature of about 480 ° C. or higher, the unevenness of the thin film surface becomes large, and a flat continuous film is obtained. I found it impossible. Further, since the deposition rate is increased, it is very difficult to control the film thickness. Therefore, the non-doped amorphous Si films 104 and 204 are desirably formed at a temperature of 480 ° C. or lower.

  Next, the phosphorus-doped amorphous Si films 106, 206, and 306 of all the samples were converted into phosphorus-doped polycrystalline Si films 106, 206, and 306. This conversion is possible by heat-treating each sample in a nitrogen atmosphere at 750 ° C. for 40 minutes. At this heat treatment temperature, only the phosphorus-doped Si films 106, 206, and 306 having a thickness of 200 nm are crystallized. On the other hand, during this process, the non-doped amorphous Si films 104 and 204 in contact with the gate insulating films 103 and 203 maintain an amorphous state. This is because the polycrystallization of silicon is promoted by phosphorus. Crystallization of amorphous Si occurs when the radius of the Si cluster reaches a certain size. The radius of this cluster is generally called the critical radius. Since the thickness of the Si film in the present invention is equal to or greater than the critical radius, crystallization does not usually occur unless a heat treatment at a higher temperature than the heat treatment for crystallizing amorphous Si is performed.

  Next, sample No. 1-No. 5, nitrogen annealing at 900 ° C. for 120 minutes was added to convert the non-doped amorphous Si film 104 corresponding to the lower electrode 104 into the polycrystalline Si film 104.

  Subsequently, the phosphorus-doped polycrystalline Si films 106, 206, 306 and the lower Si films 104, 204 are processed into a predetermined shape by a known lithography and dry etching method to form the gate electrodes 104, 106, 204, 206, 306. Form. Thus, the MOS capacitor shown in FIGS. 1 and 2 is produced.

  First, the crystallinity of the Si films 106, 206, 204, 206, and 306, which are gate electrodes, and the grain size thereof were observed with a transmission electron microscope. The crystal grain size of the upper electrodes 106, 206, and 306 of the sample (No. 1 to No. 5) to which heat treatment at 900 ° C. for 120 minutes was added was about 0.5 μm to 1.5 μm regardless of the sample. On the other hand, it was confirmed that the ultrathin Si film 104 in the lower layer shown in FIG. 1 is a polycrystalline Si film 104 having a very small particle size. Specifically, their average particle size was about 2 to 2.5 times the deposited film thickness. The average particle size of the sample (No. 5) in which the lower Si film 104 was deposited by 8 nm was about 20 nm.

On the other hand, the crystal grain sizes of the phosphorus-doped polycrystalline Si films 206 and 306 of the samples to which the high-temperature heat treatment is not added (No. 6, No. 7), that is, the samples subjected to only the heat treatment at 750 ° C. are both about 0. It was about 3 μm to 1.0 μm. Sample No. 7 is an amorphous Si film 204 that retains crystallinity immediately after deposition, and a thin SiO ₂ film 205 (film thickness of about 0.5 nm) on the Si film exists without change. Confirmed that.

  The current-electric field characteristics before and after the constant current stress application were compared for each of the above samples. FIG. 4 shows the relationship between the thickness of the lower ultrathin Si films 104 and 204 deposited on the gate oxide film 103 and the low electric field leakage current (at −6 MV / cm). FIG. 5 shows the relationship between the film thickness of the lower ultrathin Si films 104 and 204 deposited on the gate oxide film 103 and the FN current (−11 MV / cm) for the same sample as FIG. In this figure, the point of the lower Si film of 0 nm corresponds to the conventional single layer gate electrode 306.

  As can be seen from these figures, it can be seen that in the present invention, the FN current can be significantly increased while maintaining the low electric field leakage current after stress application at least equivalent to the conventional method. That is, the increase in the FN current increased from the region where the thickness of the lower layer Si film 104 was thinner than 8 nm as the thickness of the lower layer Si film 104 was reduced. In particular, in the sample with the lower Si film 104 having a thickness of 2 nm, the FN current could be increased by about an order of magnitude compared with the sample having the conventional structure.

  FIG. 6 shows a comparison of the fracture life distribution due to constant current stress of the sample added with heat treatment at 900 ° C. for 60 minutes. The vertical axis in FIG. 5 represents the cumulative defect rate, and the horizontal axis represents the injected charge amount.

  According to the present invention, it can be seen that the breakdown life against a constant current stress is improved as compared with the conventional method, and it is improved as the lower layer Si film 104 becomes thinner.

  On the other hand, even if the lower amorphous Si film 104 was previously heat-treated and converted to the polycrystalline Si film 104 before the upper electrode 106 was deposited, the same result as described above was obtained.

  7 is a diagram comparing the fracture life distributions due to constant current stress of samples (No. 6, No. 7) subjected to only heat treatment at 750 ° C. for 40 minutes. In the present invention, the fracture life was improved by about twice that of the conventional method.

  In the present embodiment, only the sample having a thickness of 4 nm is described for the lower amorphous Si film 204, but the same result as the above sample is obtained until the lower amorphous Si film thickness is about 8 nm. Obtained.

  As a result of examining the relationship between the heat treatment temperature after forming the non-doped amorphous Si film and the crystallinity of the film, the crystallization temperature of the amorphous Si film decreases when the film thickness is greater than about 8 nm. I understood. Therefore, in order to maintain the amorphous state up to about 800 ° C., the thickness of the amorphous Si film is preferably about 8 nm or less.

In this embodiment, the SiO ₂ films 103 and 203 obtained by oxidizing the Si substrate in water vapor are used for the gate insulating films 103 and 203. However, the same thing can be said even if an oxynitride film formed in the following atmosphere is used. The effect was obtained. These atmospheres are (1) ammonia (NH ₃ ) atmosphere, (2) nitrous oxide (N ₂ O) atmosphere, or (3) nitrogen monoxide (NO) atmosphere. Here, the In-Situ amorphous Si films 106 and 206 were deposited as the upper layer electrodes 106 and 206, but the same effect was obtained even when the In-Situ polycrystalline Si film was deposited.

In the present invention, another important point is the thickness of the insulating films 105 and 205 existing at the interface between the lower ultrathin Si films 104 and 204 and the upper electrodes 106 and 206. In this embodiment, after the lower ultra-thin Si films 104 and 204 are deposited, the lower ultra-thin Si films 104 and 204 are oxidized in the same CVD apparatus to form SiO ₂ films 105 and 205 of about 0.5 nm. Yes. When the film thicknesses of the SiO ₂ films 105 and 205 formed on the surfaces of the ultrathin Si films 104 and 204 are examined, when the upper electrodes 106 and 206 are crystallized when the thickness is less than about 0.3 nm, the lower electrode It was found that the thin Si films 104 and 204 were crystallized simultaneously with the crystallinity of the upper layer and almost the same as the single layer film.

On the other hand, when the thickness of the SiO ₂ films 105 and 205 is greater than about 1 nm, the insulating films 105 and 205 become resistors and a gate voltage drop occurs. That is, in the present invention, it is important that the thicknesses of the insulating films 105 and 205 existing at the electrode interface are about 0.3 nm to 1 nm. With respect to the insulating film at the interface, similar results were obtained for nitride films and oxynitride films formed in an atmosphere containing nitrogen atoms.

Example 1
Next, a first embodiment of the present invention will be described with reference to the drawings.

  In this example, the memory cells shown in FIGS. 8 to 10 were fabricated in order to evaluate the write / erase time. In the samples of FIGS. 8 and 9, the film thickness of the extremely thin (referred to as ultrathin) Si films 404 and 504 was used as a parameter as described above. 8 is a sample obtained by converting a non-doped ultrathin Si film 404 in contact with the gate oxide film 403 into a polycrystalline Si film 404 by heat treatment at 900 ° C. The sample of FIG. 9 is a sample whose maximum heat treatment temperature is 750 ° C. Hereinafter, detailed description will be given with reference to FIGS.

First, element isolation oxide films 402, 502, and 602 are formed on a P-type single crystal Si substrate 401, 501, and 601 by a well-known LOCOS method. Gate insulating films 403, 503, and 603 having a thickness of 8 nm were formed in the region surrounded by the element isolation oxide film. The gate insulating films 403, 503, and 603 were formed by a pyrogenic oxidation method at 850 ° C. Next, as a standard sample (FIG. 11) as a standard sample, a polycrystalline Si film 606 containing 3 × 10 ²⁰ / cm ^{3 of} phosphorus was deposited to 100 nm by LP-CVD. In the sample of the present invention, amorphous non-doped ultrathin Si films 404 and 504 were deposited by the method shown in Example 1 to 2 nm, 4 nm, 6 nm, 8 nm, and 10 nm, respectively, and then a 0.5 nm SiO ₂ film 405 was deposited. , 505 and 100 nm In-situ phosphorus-doped polycrystalline Si films 406 and 506 were formed. In this example, monosilane (SiH ₄ ) and phosphine (PH ₃ ) were used to form the In-situ phosphorus-doped polycrystalline Si films 306 and 406, and deposition was performed at a temperature of 630 ° C.

  Subsequently, after performing a heat treatment for 30 minutes in a nitrogen atmosphere at 750 ° C., the phosphorus-doped polycrystalline Si films 406, 506, 606 to be the floating gate electrodes 404, 406, 504, 506, 606, and the ultrathin layer underneath. One side surface of the Si films 404 and 504 (in the direction parallel to the drawing sheet) was processed into a predetermined shape. This processing was performed by known lithography and dry etching methods.

Next, interlayer insulating films 407, 507, and 607 composed of a SiO ₂ / Si ₃ N ₄ / SiO ₂ laminated film were formed by LP-CVD. The thickness of the SiO ₂ film as the upper and lower layers of Si ₃ N ₄ is 4 nm. For the formation, Si ₃ N ₄ and nitrous oxide (N ₂ O) are used, and the manufacturing temperature is 700 ° C. The film thickness of Si ₃ N ₄ is 8 nm. Dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ) are used for the production, and the production temperature is 700 ° C. Subsequently, 100 nm phosphorus-doped polycrystalline Si films 408, 508, and 608 to be control gate electrodes 408, 508, and 608 and 100 nm SiO ₂ films 409, 509, and 609 were deposited by LP-CVD. Furthermore, these were heat-treated in a nitrogen atmosphere at 750 ° C. for 20 minutes. Subsequently, the SiO ₂ films 409, 509, and 609, the phosphorus-doped polycrystalline Si films 408, 508, and 608 to be the control gate electrodes 408, 508, and 608, the interlayer insulating films 407, 507, and 607, and the floating gate electrodes 404 and 406 , 504, 506, 606 are processed into a predetermined shape on the other side surface (perpendicular to the paper surface of the drawing), and control gate electrodes 408, 508, 608 and floating gate electrodes 404, 406, 504, 506, 606 did. Processing was performed by known lithography and dry etching methods.

Next, after depositing a 10 nm SiO ₂ film by LP-CVD, phosphorus is ion-implanted into the regions to be the sources 410, 510, 610 and the drains 411, 511, 611. Thereafter, the sample shown in FIG. 8 and the conventional sample shown in FIG. 10 are subjected to nitrogen annealing at 900 ° C. for 60 minutes, and the sample shown in FIG. 9 is subjected to nitrogen annealing at 750 ° C. for 300 minutes. 410, 510, 610 and drains 411, 511, 611 were formed.

Next, after depositing 100 nm SiO ₂ films 412, 512, 612 by LP-CVD, the entire surfaces of the SiO ₂ films 412, 512, 612 are etched by anisotropic dry etching, and floating gate electrodes 404, Side wall insulating films 412, 512, and 612 were formed on the side walls of 406, 504, 506, 606, ONO films 407, 507, 607, and control gate electrodes 408, 508, 608. Subsequently, after depositing 300 nm of SiO ₂ films (PSG films) 413, 513, 613 containing 4 mol% of phosphorus by atmospheric pressure-CVD, the surfaces of the sources 410, 510, 610, and the drains 411, 511, 611 are exposed. A contact hole was formed.

  Finally, aluminum (Al) 414, 415, 514, 515, 614, 615 is deposited by reactive sputtering to a thickness of 500 nm, then processed into a predetermined shape, and source wirings 414, 514, 614, drain wirings 415, 515 are formed. , 615, and the memory cells shown in FIGS.

  In the sample shown in FIG. 8, the maximum heat treatment temperature was set to 900 ° C., so that the ultrathin Si film 405 immediately above the gate oxide film was a polycrystalline Si film 405. On the other hand, in the sample shown in FIG. 9, the maximum heat treatment temperature is 750 ° C., so the state of the amorphous Si film 504 is maintained.

  The rewrite characteristics were evaluated using the nonvolatile semiconductor memory device having this structure. The erasing operation is performed by injecting electric charges with the FN current through the entire surface of the gate insulating films 403, 503, and 603 to the floating gate electrodes 404, 406, 504, 506, and 506, and the writing operation is performed. , 504, 506, 606 to drains 411, 511, 611, the charge is extracted by the FN current of the gate insulating films 403, 503, 603. When erasing is performed, a pulse is applied to the control gate electrodes 408, 508, and 608 with + 10V, the sources 410, 510, and 610, the drains 411, 511, and 611 open, and the Si substrates 401, 501, and 601 set to -4V. Then, erasing was performed while checking the threshold voltage. At the time of writing, a pulse in which the control gate electrodes 408, 508 and 608 are set to −10V, the drains 411, 511 and 611 are set to + 4V, the sources 410, 510 and 610 are opened, and the Si substrates 401, 501 and 601 are set to OV. The voltage was applied and writing was performed while checking the threshold voltage.

  FIG. 11 shows the relationship between the film thickness of the lower ultrathin Si film 404 of the memory cell and the write and erase times. FIG. 11 is a comparison of samples subjected to heat treatment at 900 ° C. for 60 minutes. Although there was almost no significant difference in the erase time compared with the memory cell formed by the conventional method, the write time was significantly reduced as the lower ultrathin Si film 404 was made thinner.

  FIG. 12 is a comparison of samples with a maximum heat treatment temperature of 750 ° C. The writing time of this sample was also significantly shorter than the conventional method. The characteristic of this sample is that the writing time hardly changes until the film thickness of the lower ultrathin Si film 504 is about 6 nm, but the writing time tends to be longer after about 8 nm. This corresponds to the progress of crystallization from about 8 nm as described in Example 1. As a result of observation with a transmission electron microscope, the lower ultrathin Si film 504 of about 8 nm was locally crystallized, and that of about 10 nm was almost a polycrystalline Si film.

  In this embodiment, the floating gate electrode has a two-layer structure of phosphorus-doped polycrystalline Si / ultra-thin Si. However, a phosphorus-doped polycrystalline Si / non-doped polycrystalline Si / ultra-thin Si structure or titanium nitride (TiN) / non-doped polycrystalline Similar effects were obtained even with a three-layer structure such as Si / ultra-thin Si structure. That is, the increase in the FN current depends on the thickness or grain size of the lowermost Si film in contact with the gate insulating film, and does not depend on the floating gate electrode material formed on the upper layer.

Example 2
Next, a second embodiment of the present invention will be described. Up to now, a floating gate structure having a two-layer or three-layer structure including an ultrathin Si film in the lowermost layer has been described. Here, an example in which the floating gate electrode is an ultrathin Si single layer film will be described.

  FIG. 13 is a cross-sectional view of the nonvolatile semiconductor memory device manufactured in the third embodiment of the present invention. This structure and process flow are almost the same as the conventional structure shown in FIG. The difference is the film thickness of the floating gate electrode 704 and the method of forming it. As shown in FIG. 10, the conventional floating gate electrode 606 is a polycrystalline Si film 606 containing phosphorus, and has a thickness as thick as 50 nm or more. The floating gate electrode 704 according to the present invention is a non-doped Si film 704 formed by the same method as the lower ultrathin Si film 504 of Example 2, and is characterized by a very thin film thickness of about 8 nm or less.

  FIG. 14 shows the rewrite characteristics when the thickness of the floating gate electrode 704 is 2 nm to 10 nm. The evaluation method for erasing / writing was the same as in Example 2.

  The erase time is almost the same as that of the conventional method, but the write time is remarkably shortened when the floating gate Si film 704 is thinned, particularly when the thickness is less than about 8 nm.

  In this embodiment, since the maximum heat treatment temperature is as high as 900 ° C., the floating gate electrode is a polycrystalline Si film, but when formed at a temperature of 750 ° C. or less as shown in Embodiment 2, that is, the floating gate electrode Even when a non-doped amorphous Si film was used, the writing time was significantly reduced as compared with the conventional method.

Example 3
A specific example in which the present invention is applied to a semiconductor integrated circuit device having a nonvolatile memory element will be described below.

  In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted.

  A schematic configuration of a semiconductor integrated circuit device according to an embodiment of the present invention is shown in FIG.

  As shown in FIG. 17, the semiconductor integrated circuit device mounts a memory cell array in which a plurality of memory blocks 17 are arranged in a matrix. In the memory cell array, a plurality of word lines WL extending in the X direction are arranged, and a plurality of data lines DL extending in the Y direction are arranged.

  The memory block 17 is provided with a nonvolatile memory element Q that performs a write operation and an erase operation by the tunnel effect. A plurality of nonvolatile memory elements Q are arranged in the extending direction of the word lines WL, and a plurality of nonvolatile memory elements Q are arranged in the extending direction of the data lines DL. That is, the nonvolatile memory element Q is disposed in a region where the word line WL and the data line DL intersect.

  The direct object of the present invention described in detail in the present specification relates to the structure of the nonvolatile memory element Q.

  A drain region of each of the plurality of nonvolatile memory elements Q arranged along the extending direction is electrically connected to the one data line DL via the selection transistor St1 and the local data line LDL. Is done. Further, a selection transistor St2 is electrically connected to each source region of the plurality of nonvolatile memory elements Q arranged along the extending direction of one data line DL via a local source line LSL. The The local source line LSL is electrically connected to the source line SL via the selection transistor St2. In addition, each word line WL is electrically connected to each control gate electrode of a plurality of nonvolatile memory elements Q arranged along the extending direction. In the memory cell array configured as described above, the erasing operation of the nonvolatile memory element Q can be performed for each word line WL or for each memory block 17 and also for the entire memory cell array. Note that the word line WL and the control gate electrode of the nonvolatile memory element Q are generally formed integrally as will be described later.

  Next, the specific structure of the non-volatile memory element Q mounted on the semiconductor integrated circuit device is cut at the position of FIG. 18 (main part plan view) and FIG. 19 (AA cutting line shown in FIG. 18). A cross-sectional view taken along the line BB in FIG. 2 will be described. In FIG. 18, an interlayer insulating film 30 and a data line DL, which will be described later, are not shown for easy viewing.

  As shown in FIG. 18 (main part plan view), a plurality of the nonvolatile memory elements Q are arranged in the extending direction of the word lines WL extending in the gate length direction (X direction), and in the gate width direction ( A plurality of data lines (not shown) extending in the Y direction are arranged in the extending direction.

  The nonvolatile memory element Q is formed on the surface of the active region of the p-type semiconductor substrate 1 made of single crystal silicon, as shown in FIG. The nonvolatile memory element Q mainly includes a p-type semiconductor substrate 1 serving as a channel formation region, a first gate insulating film 3, a floating gate electrode (also referred to as a floating gate or a charge storage gate electrode) G1, and a second gate insulating film. 13, a control gate electrode (control gate electrode) G2, an n-type semiconductor region 6A as a source region, an n-type semiconductor region 6B as a drain region, a pair of n + -type semiconductor regions 9 as a source region and a drain region, a threshold value The p-type semiconductor region 15 is a voltage control region. That is, the nonvolatile memory element Q is composed of an n-channel conductivity type field effect transistor.

  The first gate insulating film 3 is formed of a silicon oxide film set to a thickness of about 8 [nm], for example. For example, the second gate insulating film 13 is formed in a multilayer structure in which a first silicon oxide film, a silicon nitride film, and a second silicon oxide film are sequentially laminated. The first silicon oxide film is set to a thickness of about 5 [nm], the silicon nitride film is set to a thickness of about 10 [nm], and the second silicon oxide film is a film of about 4 [nm], for example. Set to thickness.

  The floating gate electrode G1 according to the present invention includes a first gate material (8, 20) and a second gate material 11 laminated on the surface of the first gate material (8, 20). In this embodiment, the first gate material is composed of the non-single-crystal silicon film 20 and the polycrystalline silicon film 8 described so far. The lower layer 20 of the first gate material is specifically a multi-single crystal silicon film 20 which is crystallized by heat treatment after depositing an amorphous silicon film, and the average thickness is 8 nm or less. Hereinafter, both layers are referred to as a first gate material.

The second gate material 11 is formed of a polycrystalline silicon film into which an impurity (for example, phosphorus) for reducing the resistance value is introduced. This polycrystalline silicon film is set to a thickness of about 100 [nm], for example, and is set to an impurity concentration of about 3.5 × 10 ²⁰ [atoms / cm ³ ]. Impurities introduced into the polycrystalline silicon film are introduced during or after the deposition of the polycrystalline silicon film. The first gate material (8, 20) is initially formed of a polycrystalline silicon film that does not contain impurities, and is set to a thickness of, for example, about 50 [nm]. Thereafter, the impurity concentration is set to about 2.5 × 10 ²⁰ [atoms / cm ³ ]. The impurities introduced into the first gate material (8, 20) are introduced from the polycrystalline silicon film of the gate material 11 by thermal diffusion (drive-in diffusion).

  The width of the first gate material (8, 20) in the gate length direction defines the gate length of the charge storage gate electrode G1. The width in the gate length direction of the first gate material (8, 20) is set to about 0.5 [μm], for example. That is, the gate length of the charge storage gate electrode G1 is set to 0.5 [μm].

  Sidewall spacers 16 are formed on the respective side wall surfaces in the gate length direction of the first gate material (8, 20). The sidewall spacer 16 is formed of a silicon oxide film deposited by, for example, a CVD method.

The control gate electrode G2 is formed of, for example, a polycrystalline silicon film into which an impurity (for example, phosphorus) for reducing a resistance value is introduced. This polycrystalline silicon film is set to a thickness of about 200 [nm], for example, and an impurity concentration of about 3.5 × 10 ²⁰ [atoms / cm ³ ].

The n-type semiconductor region 6A as the source region is formed on the surface of the active region of the p-type semiconductor substrate 1 between the thermal oxide insulating film (field insulating film) 2 and the first gate material (8, 20). For example, the impurity concentration is set to about 5 × 10 ¹⁹ [atoms / cm ³ ]. The n-type semiconductor region 6B, which is the drain region, is formed on the surface of the active region of the p-type semiconductor substrate 1 between the thermal oxide insulating film 2 and the first gate material (8, 20), for example, 5 × 10 ^20. The impurity concentration is set to about [atoms / cm ³ ]. Each of the pair of n + -type semiconductor regions 9 as the source region and the drain region is formed on the surface of each of the n-type semiconductor region 6A and the n-type semiconductor region 6B, for example, about 7 × 10 ²⁰ [atoms / cm ³ ]. Impurity concentration is set. That is, each of the pair of n-type semiconductor regions 9 is set to a higher impurity concentration than each of the n-type semiconductor region 6A and the n-type semiconductor region 6B, and the nonvolatile memory element Q is one of the drain region on the channel formation region side. The part region is configured by an LDD (Lightly Doped Drain) structure in which the impurity concentration is set lower than the impurity concentration of the other regions.

The p-type semiconductor region 15 serving as the threshold voltage control region is formed on the surface of the active region of the p-type semiconductor substrate 1 under the n-type semiconductor region 6A serving as the source region, and is, for example, 5 × 10 ¹⁷ [atoms / cm. ³ ] is set to an impurity concentration of about. The p-type semiconductor region 15 is a step of forming the n-type semiconductor region 6A as the source region and the n-type semiconductor region 6B as the drain region after the step of forming the first gate material (8, 20). Prior to this, p-type impurities are selectively introduced into the surface of the p-type semiconductor substrate 1 by, for example, ion implantation.

  The width of the active region of the p-type semiconductor substrate 1 in the gate length direction is defined by a pair of thermally oxidized insulating films (field insulating films) 2 formed on the surface of the inactive region of the p-type semiconductor substrate 1. Each of the pair of thermal oxide insulating films 2 is formed of a silicon oxide film formed by a well-known selective oxidation method, and has a thickness of, for example, about 500 [nm]. Each of the pair of thermal silicon oxide films 2 extends in the gate width direction, and electrically isolates the nonvolatile memory elements Q arranged in the direction in which the word lines WL extend. That is, the thermal oxidation insulating film 2 is used as an insulating film for element isolation.

A p-type semiconductor region 12 which is a channel stopper region is formed under the thermal oxide insulating film 2. The p-type semiconductor region 12 is set to an impurity concentration of about 4 × 10 ¹⁷ [atoms / cm ³ ], for example.

  The n-type semiconductor region 6A that is the source region and the n-type semiconductor region 6B that is the drain region are respectively the n-type semiconductor region 6A and the n-type semiconductor region 6B of the plurality of nonvolatile storage elements Q arranged in the gate width direction. Are formed continuously in the direction of the gate width. Each of the pair of n-type semiconductor regions 9 that are the source region and the drain region is the source region of the plurality of nonvolatile memory elements Q arranged in the gate width direction, and the pair of n-type semiconductor regions 9 that are the drain regions. It is formed continuously in the gate width direction so as to be formed integrally with each other. That is, each of the source region and the drain region of the nonvolatile memory element Q is electrically connected to each of the source region and the drain region of another nonvolatile memory element Q arranged in the gate width direction.

  The n-type semiconductor region 6A, which is the source region, and one n + -type semiconductor region 9, which is the source region, are used as local source lines (LSL). The n-type semiconductor region 6B as the drain region and the other n + -type semiconductor region 9 as the drain region are used as local data lines (LDL). That is, the semiconductor integrated circuit device of the present embodiment is configured with a structure in which a local data line (LDL) is embedded in the p-type semiconductor substrate 1 and is configured with an AND type flash memory.

  A pair of thermally oxidized insulating films 10 are formed on the respective surfaces of the p-type semiconductor substrate 1 between the thermally oxidized insulating film 2 and the first gate material (8, 20). Each of the pair of thermal oxide insulating films 10 is formed on the surface of each of the n-type semiconductor region 6A, the n-type semiconductor region 6B, and the pair of n-type semiconductor regions 9. Each of the pair of thermal oxide insulating films 10 extends in the gate width direction. Each of the pair of thermally oxidized insulating films 10 is formed by a thermal oxidation method, and is set to a film thickness of, for example, about 150 [nm].

  The second gate material 11 of the floating gate electrode G1 is formed on the surface of the first gate material (8, 20) and the surface of the oxide insulating film 10. That is, the width of the second gate material 11 in the gate length direction is wider than the width of the first gate material (8, 20) that defines the gate length of the charge storage gate electrode G1. . In this way, the width of the second gate material 11 in the gate length direction is made wider than the width of the first gate material (8, 20) in the gate length direction, thereby making it possible to measure the gate length of the charge storage gate electrode G1. Since the area of the charge storage gate electrode G1 can be increased without increasing the operating speed, the operating speed of the nonvolatile memory element Q can be increased and the amount of charge stored in the nonvolatile memory element Q can be increased. can do.

  A control gate electrode (also referred to as a control gate electrode) G2 of the nonvolatile memory element Q is formed integrally with a word line WL extending in the gate length direction, and is arranged in another nonvolatile memory element Q arranged in the gate length direction. Are electrically connected to the control gate electrode G2. The control gate electrode G2 and the word line WL are formed of, for example, a polycrystalline silicon film. Impurities that reduce the resistance value are introduced into the polycrystalline silicon film during or after the deposition.

  An interlayer insulating film 30 is formed on the entire surface of the nonvolatile memory element Q on the p-type semiconductor substrate 1 including the control gate electrode G2 and the word line WL. A data line DL extends on the interlayer insulating film 30. The interlayer insulating film 30 is formed of a silicon oxide film, for example, and the data line DL is formed of a metal film such as an aluminum film or an aluminum alloy film.

  In addition, on the surface of the p-type semiconductor substrate 1 between the non-volatile memory element Q and the non-volatile memory element Q arranged in the gate width direction, as shown in FIG. 14 is formed.

  Next, a method for manufacturing a semiconductor integrated circuit device having the nonvolatile memory element Q will be described with reference to FIGS. 21 to 23 (cross-sectional views for explaining a manufacturing method) and FIGS. 24 to 27 (a manufacturing method). For this purpose will be described.

  First, a p-type semiconductor substrate 1 made of single crystal silicon is prepared.

  Next, as shown in FIGS. 21 and 23, a pair of thermally oxidized insulating films (field insulating films) 2 are formed on the surface of the inactive region of the p-type semiconductor substrate 1. Each of the pair of thermally oxidized insulating films 2 is formed of, for example, a thermally oxidized silicon film formed by a well-known selective oxidation method, and extends in the gate width direction (Y direction). Each of the pair of thermal oxide insulating films 2 defines the width in the gate length direction (X direction) of the active region of the p-type semiconductor substrate 1.

  Next, a first gate insulating film 3 is formed on the surface of the active region of the p-type semiconductor substrate 1 defined by the pair of thermal oxide insulating films 2. The first gate insulating film 3 is formed of a silicon oxide film formed by a thermal oxidation method.

  Next, on the entire surface of the substrate including the surfaces of the thermal oxide insulating film 2 and the first gate insulating film 3, the amorphous silicon film 20, the thermal oxide insulating film, Then, a polycrystalline silicon film 8 is sequentially formed. The amorphous silicon film 20 and the polycrystalline silicon film 8 are silicon films containing no impurities. The amorphous silicon film 20 is an amorphous silicon film having a thickness of 4 nm, and the thermally oxidized insulating film on the surface thereof is obtained by thermally oxidizing the amorphous silicon film 20 in a low-temperature reduced-pressure oxygen atmosphere. This is a 0.5 nm thermal silicon oxide film.

  Next, on the surface of a part of the laminated film composed of the amorphous silicon film 20, the thermal silicon oxide film, and the polycrystalline silicon film 8 on the first gate insulating film 3, it extends in the gate width direction. An oxidation resistant mask 5 is formed.

  Next, the oxidation resistant mask 5 and the laminated film are patterned, and an amorphous silicon film 20, a thermal silicon oxide film, and a polycrystalline silicon film are formed on a part of the surface of the first gate insulating film 3. 8 and the upper surface thereof are covered with an oxidation-resistant mask 5, and a first gate material (8, 20) having a defined width in the gate length direction is formed.

Next, the surface of one p-type semiconductor substrate 1 between the thermal oxide insulating film 2 and the oxidation resistant mask 5 is self-aligned with respect to the thermal oxide insulating film 2 and the oxidation resistant mask 5. A p-type semiconductor region 15 which is a threshold voltage control region is formed by selectively introducing a type impurity (for example, boron). The p-type impurity is introduced from an acceleration energy of 100 keV, an implantation amount of 1 × 10 ¹⁴ [atoms / cm ² ], and a direction that forms an angle of 60 degrees with the surface of the p-type semiconductor substrate 1.

  Next, n is formed on the surface of one p-type semiconductor substrate 1 between the thermal oxide insulating film 2 and the oxidation resistant mask 5 in a self-aligned manner with respect to the thermal oxide insulating film 2 and the oxidation resistant mask 5. A type impurity (for example, arsenic) is selectively introduced to form an n-type semiconductor region 6A as a source region.

  Next, n is formed on the surface of the other p-type semiconductor substrate 1 between the thermal oxidation insulating film 2 and the oxidation resistant mask 5 in a self-aligned manner with respect to the thermal oxidation insulating film 2 and the oxidation resistant mask 5. A type impurity (for example, arsenic) is selectively introduced to form an n-type semiconductor region 6B as a drain region.

  Next, as shown in FIGS. 22 and 25, side wall spacers 16 are formed on the side walls in the gate length direction of the oxidation-resistant mask 5 and the first gate material (8, 20). The sidewall spacer 16 is formed of, for example, a silicon oxide film. The sidewall spacer 16 is formed by forming a silicon oxide film on the entire surface of the p-type semiconductor substrate 1 including the surface of the oxidation resistant mask 5 by, for example, a CVD (Chemical Vapor Deposition) method, and then anisotropically forming the silicon oxide film. It is formed by etching.

  Next, the surface of the p-type semiconductor substrate 1 between the thermal oxide insulating film 2 and the side wall spacer 16 is n-type impurity (for example, phosphorus) self-aligned with the thermal oxide insulating film 2 and the side wall spacer 16. Then, a pair of n-type semiconductor regions 9 which are a source region and a drain region are formed on the surfaces of the n-type semiconductor region 6A and the n-type semiconductor region 6B. Each of the pair of n-type semiconductor regions 9 is set to a higher impurity concentration than the n-type semiconductor regions 6A and 6B.

  Next, a thermal oxidation process is performed to form a pair of thermal oxide insulating films 10 on the surface of the p-type semiconductor substrate 1 between the thermal oxide insulating film 2 and the sidewall spacers 16. The thickness of each of the pair of thermal oxide insulating films 10 is set to be thinner than the thermal oxide insulating film 2 and thicker than the first gate insulating film 3. The thermal oxidation treatment is performed in water vapor in an oxidation temperature region where the surface reaction tends to regulate the oxidation amount of the p-type semiconductor substrate 1.

  In the oxidation treatment, the amorphous silicon film having a thickness of 4 nm in contact with the first gate insulating film 3 becomes the polycrystalline silicon film 20. At this time, the silicon oxide film formed on the surface of the amorphous silicon film disappears.

  On the other hand, the first gate material (8, 20) is grown between the first gate material (8, 20) and the p-type semiconductor substrate 1 from the side wall surface side in the gate length direction toward the center by the oxidation. The gate bird's beak (thermal oxide insulating film) is formed, but the variation of the gate bird's beak (thermal oxide insulating film) becomes very small. The reason why the variation in the gate bird's beak is small is that there is no speed increasing action because the impurity concentration is small.

  Further, since the thickness of the thermal oxide insulating film 10 is set to be thinner than that of the thermal oxide insulating film 2 formed by the selective oxidation method, the heat treatment time for forming the thermal oxide insulating film 10 forms the thermal oxide insulating film 2. Shorter than the heat treatment time.

  Next, the mask 5 is removed. At this time, a part of the sidewall spacer 16 is also removed.

  Next, a polycrystalline silicon film is formed on the entire surface of the p-type semiconductor substrate 1 including the surfaces of the oxide insulating film 10 and the first gate material (8, 20) by, eg, CVD. Impurities (for example, phosphorus) that reduce the resistance value are introduced into the polycrystalline silicon film during its deposition.

  Next, a mask 20 having a defined width in the gate length direction is formed on a part of the surface of the polycrystalline silicon film on the oxide insulating film 10 and the first gate material (8, 20). The mask 20 is formed of a photoresist film, for example, and extends in the gate width direction.

  Next, the polycrystalline silicon film is patterned, and impurities are introduced onto the surfaces of the oxide insulating film 10 and the first gate material (8, 20) as shown in FIGS. A second gate material 11 made of the polycrystalline silicon film and having a defined width in the gate length direction is formed.

  Next, a p-type impurity is introduced into the surface of the p-type semiconductor substrate 1 below the thermal oxide insulating film 2 in a self-aligned manner with respect to the mask 20 by, for example, ion implantation, to form a p-type semiconductor region 12 which is a channel stopper region. Form. Next, the mask 20 is removed.

  Next, a thermal diffusion process is performed to diffuse the impurities introduced into the second gate material 11 into the first gate material (8, 20). The thermal diffusion treatment is performed for about 10 [minutes] in an atmosphere of about 850 [° C.], for example. By this step, the resistance value of the first gate material is reduced by the impurities introduced from the second gate material 11 by diffusion.

  Next, a second gate insulating film 13 is formed on the surface of the second gate material 11. The second gate insulating film 13 is formed of a multilayer film in which a first silicon oxide film, a silicon nitride film, and a second silicon oxide film are sequentially stacked by, for example, a CVD method.

  Next, a third gate material is formed on the surface of the second gate insulating film 13. The third gate material is formed of, for example, a polycrystalline silicon film into which an impurity for reducing the resistance value is introduced.

  Next, as shown in FIG. 27, the third gate material is patterned to define the width in the gate width direction, and each of the second gate material 11 and the first gate material (8, 20) is arranged in the gate width direction. The patterning for defining the width is sequentially performed to form the control gate electrode G2 and the word line (WL) with the third gate material, and the second gate material 11 and the first gate material (8, 20) respectively. A floating gate electrode G1 is formed. By this step, the nonvolatile memory element Q is almost completed.

  Next, on the surface of the p-type semiconductor substrate 1 between the nonvolatile memory element Q and another nonvolatile memory element Q arranged in the gate width direction, the p-type is self-aligned with the control gate electrode 13. Impurities are introduced to form a p-type semiconductor region 14 which is a channel stopper region. Through this step, the channel formation regions of the plurality of nonvolatile memory elements Q arranged in the gate width direction are separated from each other by the p-type semiconductor region 14.

  Next, an interlayer insulating film 30 is formed on the entire surface of the p-type semiconductor substrate 1 including the word line (WL) and the control gate electrode G2, and then data is formed on the entire surface of the p-type semiconductor substrate 1 including the interlayer insulating film 30. Line DL is formed. The data line DL is formed of a metal film made of, for example, an aluminum film or an aluminum alloy film.

  In addition, after the step of forming a polycrystalline silicon film by, for example, the CVD method on the entire surface of the p-type semiconductor substrate 1 including the surfaces of the thermal oxide insulating film 10 and the first gate material (8, 20). Before the step of forming the mask 20, a step of introducing an impurity (for example, phosphorus) into the polycrystalline silicon film may be provided.

  The nonvolatile memory element Q configured as described above has a first gate material (8, 20) between the first gate material (8, 20) and the p-type semiconductor substrate 1 from the side wall surface side in the gate length direction. The variation of the gate bird's beak that grows toward the center can be reduced to 5 [nm] or less. This reduction in gate bird's beak variation can suppress variation in threshold voltage after writing.

  Note that the effective channel length of the nonvolatile memory element Q is 0.3 [nm], the threshold voltage measured from the control gate electrode G2 is 1.5 [V], and the punch-through breakdown voltage is 8 [V]. ].

  In the data erasing operation to the nonvolatile memory element Q, a reference potential of −4 [V] is applied to the p-type semiconductor substrate 1, a pulse width of 0.5 [ms] and a voltage of 12 are applied to the control gate electrode G2. The operation potential (write voltage pulse) of [V] is applied and tunnel current injection from the entire channel region to the charge storage gate electrode G1 is performed. The threshold voltage after erasing rises to 6 [V]. On the other hand, in the data erasing operation, an operating potential of −9 [V] is applied to the control gate electrode G2, and an operating potential (erasing voltage pulse) having a pulse width of 0.5 [ms] and a voltage of 5 [V] is applied to the drain region. Is applied, and a tunnel current is discharged from the charge storage gate electrode G1 to the drain region. The threshold voltage after erasing decreases to 1 [V]. As a result of performing the test of the write operation and the erase operation with the semiconductor integrated circuit device having a capacity of 1 [Mbit], the variation of the write-erase voltage for obtaining a certain threshold voltage shift is 0.02 [V]. It was able to be suppressed to the extent.

  According to the semiconductor integrated circuit device having the nonvolatile memory device of this example, it was possible to increase the FN current by using a predetermined amorphous silicon film as the first gate material.

  In addition, according to the present embodiment, the impurity concentration of the gate electrode material in contact with the gate insulating film is reduced, the variation in the area of the overlap region due to the gate bird beak is reduced, and the FN current is made uniform. I can do it.

In addition, according to the present embodiment, the following various effects can be obtained.
(1) The dimensional accuracy of the width of the first gate material (8, 20) in the gate length direction can be increased, and the gate length of the floating gate electrode G1 defined by the width of the first gate material in the gate length direction can be increased. The dimensional accuracy can be increased. As a result, it is possible to reduce the variation in the area of the overlap region where the floating gate electrode G1 and the drain region overlap, and to reduce the variation in the area of the overlap region where the floating gate electrode and the source region overlap. Therefore, the write characteristics and erase characteristics of the nonvolatile memory element Q can be made uniform.

  Further, in the nonvolatile memory element Q that performs the writing operation and the erasing operation by the tunnel effect, the variation in threshold voltage after writing can be reduced. As a result, the operation margin of the nonvolatile memory element Q with respect to fluctuations in the power supply potential can be increased.

In addition, since the nonvolatile memory element Q having uniform characteristics can be manufactured across the semiconductor chips and between the semiconductor wafers, a highly reliable large-capacity semiconductor integrated circuit device can be stably manufactured.
(2) The diffusion length in which impurities introduced in a self-aligned manner with respect to the oxidation resistant mask 5 are diffused to the channel forming region side under the first gate material (8, 20) can be shortened. As a result, the effective channel length between the source region and the drain region can be ensured, so that the punch-through breakdown voltage of the nonvolatile memory element Q can be increased.
(3) The dimensional accuracy of the width in the gate length direction of the first gate material (8, 20) can be further increased. As a result, the variation in the area of the overlap region where the charge storage gate electrode G1 and the drain region overlap can be further reduced, so that the write characteristics and the erase characteristics of the nonvolatile memory element Q can be further uniformed. .

In the step before forming the second gate material 11, the first gate material (8) is an amorphous silicon film (amorphous silicon film) whose impurity concentration is set to 1 × 10 ¹⁹ [atoms / cm ³ ] or less. [A-Si]). In this case, the same effect as that obtained when the first gate material (8) is formed of a polycrystalline silicon film whose impurity concentration is set to 1 × 10 ¹⁹ [atoms / cm ³ ] or less can be obtained.

  Of course, a modification for increasing the capacity of the nonvolatile memory element can also be implemented. A schematic configuration of a semiconductor integrated circuit device according to this modification is shown in FIG.

  As shown in FIG. 28, the semiconductor integrated circuit device includes a nonvolatile memory element Q that performs a write operation and an erase operation by a tunnel effect. The nonvolatile memory element Q is mainly a p-type semiconductor substrate 1, a first gate insulating film 3, a floating gate electrode G1, a second gate insulating film 13, a control gate electrode G2, and a source region, which are channel forming regions. An n-type semiconductor region 6A, an n-type semiconductor region 6B as a drain region, a pair of n + -type semiconductor regions 9 as a source region and a drain region, and a p-type semiconductor region 15 as a threshold voltage control region.

  The floating gate electrode G1 is composed of the first gate material (8, 20) and the second gate material 11 stacked on the surface of the first gate material (8, 20), as in the above example. . The second gate material 11 is formed of a polycrystalline silicon film into which phosphorus is introduced as an impurity for reducing the resistance value.

The surface of the second gate material 11 is formed in an uneven shape. The uneven shape of the second gate material 11 is formed by immersing the p-type semiconductor substrate 1 in a phosphoric acid solution before the step of forming the second gate insulating film 13. The step of immersing the p-type semiconductor substrate 1 in a phosphoric acid solution is performed under the condition of immersing in a phosphoric acid solution (H ₃ PO ₄ ) of about 140 to 160 ° C. for about 60 minutes.

  As described above, the second gate material 11 is formed of a polycrystalline silicon film into which phosphorus is introduced, and the second gate insulating film 13 is formed after the step of forming the second gate material 11. By providing the step of immersing the semiconductor substrate 1 in a phosphoric acid solution before the step, the surface of the second gate material 11 can be made uneven, so that the surface area of the second gate material 11 is increased. can do. As a result, since the surface area of the charge storage gate electrode G1 can be increased, the charge storage amount of the nonvolatile memory element Q can be increased.

  The uneven shape on the surface of the second gate material 11 can also be formed by depositing hemispherical particles (hemispherical grains: HSG) by the CVD method.

It is sectional drawing of the planar capacitor used in order to demonstrate the basic effect of this invention. It is sectional drawing of the conventional planar capacitor used for the comparison with this invention. It is a figure which shows the conditions of each sample used in order to demonstrate the basic effect of this invention. It is a figure which compares the current density of the leakage current in the low electric field after constant current stress application. It is a figure which compares the rewriting (FN) electric current after a constant current stress application. It is a figure which compares the breakdown lifetime distribution by constant current stress (comparison with the capacitor which heat-processed at 900 degreeC). It is a figure which compares the breakdown lifetime distribution by constant current stress (comparison with the capacitor which heat-processed at 750 degreeC). 1 is a cross-sectional view of a first memory cell used in a first embodiment of the present invention. It is sectional drawing of the 2nd memory cell used for the 1st Example of the present invention. It is sectional drawing of the conventional memory cell used for the comparison in the 2nd Example. It is a figure which shows the comparison (900 degreeC heat processing) of the write / erase time of a memory cell. It is a figure which shows the comparison (750 degreeC heat processing) of the programming / erasing time of a memory cell. It is sectional drawing of the memory cell used for the 2nd Example of this invention. FIG. 6 shows a comparison of memory cell write / erase times (heat treatment at 900 ° C.). FIG. It is a figure which shows the comparative example of the electric current-electric field characteristic before and behind a fixed current stress. It is a figure which shows the general relationship between the film thickness of a gate insulating film, and current density. It is an equivalent circuit diagram of the principal part of the memory array mounted in the semiconductor integrated circuit device that is Embodiment 3 of the present invention. FIG. 18 is a plan view of a main part of the semiconductor integrated circuit device of FIG. 17. It is principal part sectional drawing cut | disconnected by the AA cutting line shown in FIG. It is principal part sectional drawing cut | disconnected by the BB cutting line shown in FIG. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is principal part sectional drawing for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is a principal part top view for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is a principal part top view for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is a principal part top view for demonstrating the manufacturing method of the said semiconductor integrated circuit device. It is a principal part top view for demonstrating the manufacturing method of the said semiconductor integrated circuit device. 10 is a cross-sectional view of a main part showing a modification of the memory cell shown in Embodiment 3. FIG.

Explanation of symbols

1 ... p-type semiconductor substrate 1, 2 ... field insulating film, 3 ... first gate insulating film, 4 ... polycrystalline silicon film, 5 ... oxidation resistant mask, 6. ... n-type semiconductor region, 7... oxidation-resistant mask, 8... first gate material, 9... n-type semiconductor region, 10. , 12 ... p-type semiconductor region, 13 ... second gate insulating film, 14 ... p-type semiconductor region, 15 ... p-type semiconductor region, 16 ... side wall spacer, 17 ... Memory block, G1 ... charge storage gate electrode, G2 ... control gate electrode, Q ... nonvolatile memory element, ST ... selection transistor, WL ... word line, DL ... data line , LSL ... Local source line, LDL ... Local data line. 101, 201, 301, 401, 501, 601, 701 ... single crystal silicon substrate, 102, 202, 302, 402, 502, 602, 702 ... element isolation oxide film, 103, 203, 303, 403, 503, 603, 703 ... gate insulating film (tunnel insulating film), 104, 204, 404, 504, 704 ... Si film, 105, 205, 405, 505 ... SiO ₂ film, 104, 106, 204, 206, 306 ... gate electrode, 404, 406, 504, 506, 606, 704 ... floating gate electrode, 407, 507, 607, 707 ... ONO interlayer film, 408, 508, 608, 708 ... Control gate electrode, 409, 413, 509, 513, 609, 613, 709, 713 ... Insulating film, 412, 512, 612, 712 ... Side wall insulating film, 410, 51 , 610, 710 ... the source region, 411,511,611,711 ... drain region, 414,514,614,714 ... source wiring, 415,515,615,715 ... drain wiring.

Claims (14)

In a method for manufacturing a nonvolatile semiconductor memory device formed on a semiconductor substrate,
(A) forming a first insulating film to be a gate insulating film on the semiconductor substrate;
(B) forming a first silicon film to be an amorphous floating gate electrode having an average film thickness of 10 nm or less on the first insulating film;
(C) forming a second insulating film having a thickness of 0.3 to 1 nm on the amorphous first silicon film;
(D) forming a first conductor film serving as a floating gate electrode on the second insulating film;
(E) forming a third insulating film serving as an interlayer insulating film on the first conductor film;
(F) forming a second conductive film to be a control gate electrode on the third insulating film;
(G) having a heat treatment step after the step (b),
In the non-volatile semiconductor memory device manufacturing method, the amorphous first silicon film maintains an amorphous state in the heat treatment step after the step (b). The method of manufacturing a nonvolatile semiconductor memory device according to claim 1.
The first conductive film includes an amorphous second silicon film, and the amorphous second silicon film is converted into a polycrystalline silicon film in the heat treatment step . Manufacturing method of semiconductor memory device . In a method for manufacturing a nonvolatile semiconductor memory device formed on a semiconductor substrate,
(A) forming a first insulating film to be a gate insulating film on the semiconductor substrate;
(B) forming a first silicon film to be an amorphous floating gate electrode having an average film thickness of 10 nm or less on the first insulating film;
(C) forming a second insulating film having a thickness of 0.3 to 1 nm on the amorphous first silicon film;
(D) forming a first conductor film serving as a floating gate electrode having an amorphous second silicon film on the second insulating film;
(H) forming a third insulating film serving as an interlayer insulating film on the second silicon film;
(I) forming a second conductive film to be a control gate electrode on the third insulating film;
(J) A method for manufacturing a nonvolatile semiconductor memory device , comprising the step of selectively polycrystallizing the second silicon film after the step (d). The method of manufacturing a nonvolatile semiconductor memory device according to claim 3.
The method of manufacturing a nonvolatile semiconductor memory device , wherein the step of selectively polycrystallizing the second silicon film is a step of heat treatment. In the manufacturing method of the non-volatile semiconductor memory device according to any one of claims 1 to 4 .
A method for manufacturing a nonvolatile semiconductor memory device , wherein the first silicon film has an average film thickness of 8 nm or less . The method of manufacturing a nonvolatile semiconductor memory device according to claim 5 .
The heat treatment step is a heat treatment step of 800 ° C. or lower, or the step of selectively polycrystallizing the second silicon film is a heat treatment step of 800 ° C. or lower. Manufacturing method. In a method for manufacturing a nonvolatile semiconductor memory device formed on a semiconductor substrate ,
(A) forming a first insulating film to be a gate insulating film on the semiconductor substrate;
(B) forming a first silicon film to be an amorphous floating gate electrode having an average film thickness of 10 nm or less on the first insulating film;
(C) forming a second insulating film having a thickness of 0.3 to 1 nm on the amorphous silicon film;
(D) forming a first conductor film serving as a floating gate electrode having an amorphous second silicon film on the second insulating film;
(E) forming a third insulating film serving as an interlayer insulating film on the first conductor film;
(F) forming a second conductive film to be a control gate electrode on the third insulating film;
(G) after the step (b), a step of polycrystallizing the first silicon film;
(H) after the step (d), the step of polycrystallizing the second silicon film,
A method for manufacturing a nonvolatile semiconductor memory device , wherein the crystal grain size of the first silicon film is smaller than the crystal grain size of the second silicon film . In a method for manufacturing a nonvolatile semiconductor memory device formed on a semiconductor substrate,
(A) forming a first insulating film to be a gate insulating film on the semiconductor substrate;
(B) forming a first silicon film to be an amorphous floating gate electrode having an average film thickness of 10 nm or less on the first insulating film;
(C) forming a second insulating film having a thickness of 0.3 to 1 nm on the amorphous first silicon film;
(D) forming a first conductor film serving as a floating gate electrode having a polycrystalline second silicon film on the second insulating film;
(E) forming a third insulating film serving as an interlayer insulating film on the first conductor film;
(F) forming a second conductive film to be a control gate electrode on the third insulating film;
(G) after the step (b), the step of polycrystallizing the second silicon film,
A method of manufacturing a nonvolatile semiconductor memory device , wherein the crystal grain size of the first silicon film is smaller than the crystal grain size of the second silicon film . The method for manufacturing a nonvolatile semiconductor memory device according to claim 7 or 8,
A method for manufacturing a nonvolatile semiconductor memory device , wherein the crystal grain size of the first silicon film is 20 nm or less . In the manufacturing method of the non-volatile semiconductor memory device according to any one of claims 7 to 9,
A method for manufacturing a nonvolatile semiconductor memory device , wherein the first silicon film has an average film thickness of 8 nm or less . In the manufacturing method of the non-volatile semiconductor memory device according to any one of claims 7 to 10,
The method for manufacturing a nonvolatile semiconductor memory device , wherein the polycrystallization step is a heat treatment step . The method of manufacturing a nonvolatile semiconductor memory device according to claim 11.
The method for manufacturing a nonvolatile semiconductor memory device, wherein the second insulating film disappears in the heat treatment step . In the manufacturing method of the non-volatile semiconductor memory device according to any one of claims 1 to 12,
The method of manufacturing a nonvolatile semiconductor memory device , wherein the first conductor film is a laminated film of a silicon film . In the manufacturing method of the non-volatile semiconductor memory device according to any one of claims 1 to 13,
The method of manufacturing a nonvolatile semiconductor memory device , wherein the first silicon film is formed at 480 ° C. or lower .

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