JP2009010166A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable characteristic variation of a floating gate electrode or a control gate electrode to be controlled as much as possible, a tunnel insulating film reliability to be prevented from being degraded, and stress-induced leak current to be controlled. <P>SOLUTION: The semiconductor device has a substrate 1 having a primary conductive semiconductor layer, a pair of secondary conductive source/drain regions 12 prepared so as to face the semiconductor layer, a primary insulating film 14 prepared on the semiconductor layer between the source/drain regions, a floating gate 16 prepared on the primary insulating film that includes a single crystal semiconductor in which a sub-grain boundary 17 is formed in a direction where the source/drain regions face, and a memory cell having a secondary insulating film 18 prepared on the floating gate electrode and a control gate electrode 20 prepared on the secondary insulating film. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  2. Description of the Related Art In recent years, miniaturization of elements has been advanced rapidly in semiconductor memory elements represented by nonvolatile semiconductor memory (EEPROM) that can be electrically written and erased.

  In the case of a conventional floating gate type nonvolatile semiconductor memory, polycrystalline silicon has been used as a floating gate electrode for accumulating charges. In other words, by applying an electric field to the element, electrons are injected from the silicon substrate to the floating gate electrode through the tunnel insulating film, and the threshold value of the cell is changed in the positive direction (writing operation), or a reverse electric field is applied. Thus, by extracting electrons accumulated in the floating gate electrode to the substrate side, the threshold value is changed in the negative direction (erase operation), thereby producing a memory effect. At this time, the floating gate electrode made of polycrystalline silicon is processed by using a lithography technique and an etching technique so that a polycrystalline silicon film is formed on the tunnel insulating film formed on the substrate and has a desired size. Further, the processed floating gate electrode is formed by oxidation (post-oxidation process) for the purpose of recovering damage during processing.

  However, in this case, since polycrystalline silicon is used as the floating gate electrode, various crystal plane orientations are exposed at the end face. And, it is known that the oxidation rate is dependent on the plane orientation, so if oxidation (post-oxidation process) is performed in this state, the oxide film thickness of the exposed polycrystalline silicon surface will be different for each crystal grain As a result, the oxidation proceeds non-uniformly. As a result, the surface (side surface) shape of the floating gate electrode becomes uneven, and the variation in the area of the floating gate electrode between cells increases. Particularly in the case of a flash memory device having a next-generation fine cell structure, this variation in area becomes one of the causes of serious variation in device characteristics. The same can be said for the control gate as well as the floating gate electrode.

  On the other hand, a technique of using the floating gate electrode as single crystal silicon has been proposed (see, for example, Patent Document 1, Patent Document 2, and Patent Document 3). These conventional techniques form an exposed portion where the surface of the semiconductor substrate is exposed at a position adjacent to or away from the element portion in order to monocrystalize the floating gate electrode, and this exposed portion is used as a seed. An amorphous silicon film is grown on a solid phase. However, this method has a problem that it is disadvantageous for miniaturization of elements because a lithography process for forming a seed is added or a region for forming a seed is required.

  On the other hand, in the operation of the nonvolatile semiconductor memory, in both the NOR type and the NAND type, electrons are taken into and out of the floating gate electrode through the tunnel insulating film as described above. A large stress is applied. As a result, defects called traps are generated in the tunnel insulating film, and the leakage current (stress-induced leakage current) increases, which hinders data retention and the like. In particular, it is known that the deterioration tendency is remarkable in recent years when miniaturization advances.

  The traps and defects in the tunnel insulating film, which cause this leakage current, are caused by the fact that electrons in silicon tunnel to the conduction band of the tunnel insulating film due to voltage application and have large energy when they escape to the cathode side. ing. That is, when electrons having energy depending on the applied voltage escape to the cathode side, high-energy holes are generated by impact ionization on the cathode side, and hydrogen present at the silicon interface is generated by these holes. The bond is broken. As a result, it is considered that a weak portion in the tunnel insulating film is destroyed and a defect is generated, resulting in leakage current and dielectric breakdown.

  Such weak portions in the insulating film that cause defects and traps in the tunnel insulating film are concentrated particularly on the end of the tunnel insulating film. This is a position corresponding to a portion where the tunnel insulating film is increased in the oxidation step after forming the tunnel insulating film, that is, a so-called bird's beak portion. At the end of the tunnel insulating film sandwiched between the semiconductor substrate and the floating gate electrode in the word line direction, the tunnel insulating film is increased particularly on the floating gate electrode side. Defects such as electron traps are generated at the end of the increased tunnel insulating film by applying a high electric field stress during writing / erasing. Furthermore, since the central part of the film with a small amount of film increase is thinner than the end part, the electric field concentrates on this part, which promotes the generation of traps and defects. As a result, data retention characteristics and disturb characteristics are significantly deteriorated.

The reason why the bird's beak portion is weak is that the insulating film to be increased is an oxide film formed by oxidation of the floating gate electrode made of polycrystalline silicon. A floating gate electrode used in a conventional nonvolatile memory is a polycrystalline silicon film, and a bird's beak portion is formed by oxidation of the polycrystalline silicon film. That is, the oxide film has various crystal orientations. Further, the proportion of the bird's beak in the cell area increases due to the miniaturization of the element.
Japanese Patent Laid-Open No. 07-273229 JP 2000-260889 A JP-A-10-107165

As described above, the tunnel insulating film of the nonvolatile semiconductor memory such as the EEPROM has the following three problems in the post-oxidation process after forming the tunnel insulating film and the floating gate electrode.
1) Large irregularities are formed on the processed end face of the floating gate electrode made of a polycrystalline silicon film, and the variation in element characteristics increases.
2) During oxidation, a bird's beak made of an oxide film is formed at the interface between the tunnel insulating film and the floating gate electrode, and the bird's beak is formed by oxidation of polycrystalline silicon. It is formed at the end.
3) Since a bird's beak is formed at the end portion, the central portion of the tunnel insulating film becomes thinner than the end portion, causing electric field concentration, and traps and defects are present in the tunnel insulating film when high voltage stress is applied during writing / erasing. As a result, the tunnel leakage current increases.

  For this reason, in the future generations in which miniaturization will progress and the variation in cell area will affect the variation in memory characteristics of the cell, the unevenness of the end face of the floating gate electrode will be minimized, and the tunnel insulating film and floating There is a demand for a floating gate material capable of realizing a tunnel insulating film that can suppress defects in the bird's beak formed at the gate interface and stress-induced leakage current caused thereby.

  However, it has been extremely difficult to satisfy such a requirement with the prior art and the conventional gate structure. As described above, it has been proposed to change the floating gate electrode from polycrystalline silicon to single crystal silicon, but it has been difficult to realize it because it is disadvantageous for an increase in lithography process and miniaturization.

  The present invention has been made in view of the above circumstances, and its purpose is to suppress variations in characteristics of the floating gate electrode or the control gate electrode as much as possible, and to prevent a decrease in the reliability of the tunnel insulating film. Another object of the present invention is to provide a semiconductor device capable of suppressing stress-induced leakage current and a method for manufacturing the same.

  A semiconductor device according to a first aspect of the present invention includes a substrate having a first conductivity type semiconductor layer, a pair of second conductivity type source / drain regions provided facing the semiconductor layer, and the source / drain regions. A first insulating film provided on the semiconductor layer between the drain regions, and a single insulating layer provided on the first insulating film, in which subgrain boundaries are formed along the direction in which the source / drain regions face each other. A memory cell having a floating gate electrode including a crystalline semiconductor, a second insulating film provided on the floating gate electrode, and a control gate electrode provided on the second insulating film. It is characterized by that.

  According to a second aspect of the present invention, there is provided a semiconductor device comprising: a substrate having a first conductivity type semiconductor layer; a pair of second conductivity type source / drain regions provided opposite to the semiconductor layer; A first insulating film provided on the semiconductor layer between the source / drain regions, a charge storage film provided on the first insulating film, and a second insulation provided on the charge storage film And a control gate electrode including a single crystal semiconductor provided on the second insulating film and having a sub-grain boundary formed in a direction orthogonal to a direction in which the impurity regions are opposed to each other. And.

  The method of manufacturing a semiconductor device according to the third aspect of the present invention includes a step of forming a first insulating film on a semiconductor substrate, and forming a first amorphous semiconductor film on the first insulating film. A step of forming a first mask insulating film on the first amorphous semiconductor film, and at least until the surface of the semiconductor substrate is exposed, the first mask insulating film, A step of patterning a laminated film composed of one amorphous semiconductor film and the first insulating film, a step of forming a second amorphous semiconductor film so as to cover the patterned laminated film, By performing heat treatment, the second amorphous semiconductor film is monocrystallized by solid phase epitaxial growth to form a first single crystal film, and the first amorphous semiconductor film is monocrystallized by solid phase epitaxial growth. The second single crystal film Wherein the step, removing the first TanAkiramaku by etching, further comprising: a.

  According to a fourth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a first insulating film on a semiconductor substrate; and forming a first amorphous semiconductor film on the first insulating film. A step of forming a first mask insulating film on the first amorphous semiconductor film, and at least until the surface of the semiconductor substrate is exposed, the first mask insulating film, A step of patterning the first amorphous semiconductor film and the first laminated film made of the first insulating film, and a second amorphous semiconductor film so as to cover the patterned first laminated film And forming the first amorphous semiconductor film into a first single crystal film by solid-phase epitaxial growth to form a first single crystal film by heat treatment. Single crystallized by phase epitaxial growth and second A step of forming a crystal film; a step of removing the first single crystal film by etching and removing a part of the semiconductor substrate; and depositing an element isolation insulating film on the entire surface. Planarizing the first mask insulating film, exposing the upper surface of the first mask insulating film, removing the first mask insulating film and exposing the upper surface of the second single crystal film, Forming a second insulating film so as to cover an upper surface of the second single crystal film; forming a third amorphous semiconductor film on the second insulating film; and Forming a second mask insulating film on the amorphous semiconductor film; and until the surface of the semiconductor substrate is exposed, the second mask insulating film, the third amorphous semiconductor film, From the second insulating film, the second single crystal film, and the first insulating film Patterning the second laminated film into a gate shape, forming a fourth amorphous semiconductor film so as to cover the patterned second laminated film, and heat-treating the fourth laminated film. The amorphous semiconductor film is single crystallized by solid phase epitaxial growth to form a third single crystal film, and the third amorphous semiconductor film is single crystallized by solid phase epitaxial growth to obtain a fourth single crystal film. And a step of removing the third single crystal film by etching.

  According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: forming a first insulating film on a semiconductor substrate; forming a charge storage film on the first insulating film; and etching. And patterning the first laminated film comprising the charge storage film and the first insulating film and removing a part of the semiconductor substrate, and depositing an element isolation insulating film on the entire surface, The step of exposing the upper surface of the charge storage by planarizing the film, the step of forming a second insulating film so as to cover the upper surface of the charge storage film, and the first on the second insulating film Forming the amorphous semiconductor film, forming the mask insulating film on the first amorphous semiconductor film, and until the surface of the semiconductor substrate is exposed, the mask insulating film, A first amorphous semiconductor film; A step of patterning a second laminated film comprising an edge film, the charge storage film, and the first insulating film into a gate shape; and a second amorphous film so as to cover the patterned second laminated film A step of forming a semiconductor film and a heat treatment make the second amorphous semiconductor film a single crystal by solid phase epitaxial growth to form a first single crystal film, and the first amorphous semiconductor film And a step of removing the first single crystal film by etching, and a step of removing the first single crystal film by etching.

  According to the present invention, a semiconductor device capable of suppressing variations in characteristics of a floating gate electrode or a control gate electrode as much as possible, preventing a decrease in reliability of a tunnel insulating film, and suppressing stress-induced leakage current. And a method for manufacturing the same.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
A nonvolatile semiconductor memory device according to a first embodiment of the present invention will be described. The nonvolatile semiconductor memory device of this embodiment is a NAND type. That is, the nonvolatile semiconductor memory device of this embodiment has a NAND cell in which a plurality of memory cells are connected in series. A cross section of the nonvolatile semiconductor memory device of this embodiment is shown in FIGS. 1 is a cross-sectional view of the NAND cell in a direction parallel to the bit line, and FIG. 2 is a cross-sectional view taken along the cutting line AA shown in FIG. 1, that is, a cross-sectional view in the direction parallel to the word line. .

  As shown in FIG. 1, each memory cell 10 includes an n-type source / drain region 12 provided on a p-type silicon substrate 1 having a plane orientation of (100) and a source region and a drain region. A tunnel insulating film 14 provided on a region serving as a channel between the silicon substrate 1, a single-crystal silicon floating gate electrode 16 provided on the tunnel insulating film 14, and an electrode provided on the floating gate electrode 16 An inter-layer insulating film 18 and a control gate electrode 20 provided on the inter-electrode insulating film 18 and having a laminated structure of a polycrystalline silicon film 20a and a tungsten silicide film 20b are provided. Adjacent memory cells 10 in the NAND cell are connected so as to share a source region or a drain region. The interelectrode insulating film 18 has an ONO film structure that is a laminated structure of a silicon oxide film, a CVD silicon nitride film, and a CVD silicon oxide film. In addition, each memory cell 10 includes an insulating layer made of, for example, a silicon oxide film on the upper and side surfaces of the control gate electrode, the side surface of the interelectrode insulating film 18, the side surface of the floating gate electrode 16, and the side surface of the tunnel gate insulating film 14. A film 24 is formed.

  As shown in FIG. 2, the memory cell 10 in the direction parallel to the word line is insulated by the element isolation region 3 formed on the silicon substrate 1. The interelectrode insulating film 18 and the control gate electrode 20 of the memory cell 10 in the word line direction are common.

  Further, in the present embodiment, the floating gate electrode 16 made of single crystal silicon has a central portion along the direction parallel to the bit line, that is, the direction in which the source region and the drain region face each other, as shown in FIG. A grain boundary (sub-grain boundary) 17 is formed. This sub-grain boundary 17 is a kind of grain boundary formed by lattice mismatch formed at a portion where the solid-phase growth surface comes into contact and solid-phase growth stops. The difference from the normal crystal grain boundary is that the plane orientations of both solid phase growth films with the subgrain boundary 17 in between are the same.

  In the present embodiment, the floating gate electrode 16 is single-crystallized. For this reason, in the post-oxidation process described later in the manufacturing method, the side surface of the floating gate electrode 16 is uniformly oxidized, and the unevenness of the side surface of the floating gate electrode 16 can be suppressed. The variation in the area can be reduced. Further, in the post-oxidation step after the formation of the tunnel insulating film 14 and the floating gate electrode 16, a bird's beak 15 is generated between the tunnel insulating film 14 and the floating gate electrode 16 as shown in FIG. Since this bird's beak 15 is an oxide film grown by oxidation of a single crystal silicon film, unlike the conventional case where the floating gate electrode is made of polycrystalline silicon, a homogeneous tunnel insulating film can be formed.

  On the other hand, as shown in FIG. 4, when the floating gate electrode is made of polycrystalline silicon as in the prior art, the side surface is exposed to various crystal plane orientations. The oxide film thickness on the exposed surface of the polycrystalline silicon is different for each crystal grain, and thus the oxidation proceeds non-uniformly. As a result, the side surface shape of the floating gate electrode becomes uneven, and the variation in the area of the floating gate electrode between memory cells increases. FIG. 4 is a cross-sectional view in a direction parallel to the substrate surface after the post-oxidation process of the floating gate electrode when the floating gate electrode is made of polycrystalline silicon.

  In the present embodiment, the floating gate electrode 16 made of single crystal silicon has the same plane orientation (100) as that of the silicon substrate 1 as will be described later in the manufacturing method. For this reason, the bird's beak formed by oxidizing the single crystal silicon in the post-oxidation process becomes a highly reliable oxide film, and it becomes possible to suppress traps and defect generation against high electric field stress during writing / erasing. , Stress-induced leakage current can be reduced. The reason for this will be described with reference to FIGS.

5 and 6, the silicon oxide film formed on the surface of different silicon substrate of plane orientation, show the results of a comparison stress induced leakage current (SILC) and dielectric breakdown lifetime (50% Q _BD). Here, the stress-induced leakage current (SILC) means the amount of current increase before and after stress application, and the gate current density is 10 ⁻¹⁰ A / cm ^{2 in} the current-voltage characteristic before stress application as shown in FIG. The evaluation voltage Vgs is defined as a voltage, and in the current-voltage characteristics after the stress is applied, the increase in current at the evaluation voltage Vgs is defined as SILC. Further, the Q _BD, it is meant the total amount of electrons injected into the tunnel insulating film up to the dielectric breakdown, to monitor the gate current during the stress application test, integrated over time until breakdown occurs Defined as a value. Moreover, _{50% Q BD} value in measurement results of the _{Q BD,} is defined as _{Q BD} value corresponding to the cumulative failure rate of 50%. According to this, the silicon oxide film formed on the (100) plane has the highest reliability, and both the SILC and the dielectric breakdown lifetime are strong. The other (110) plane and (111) plane are the most reliable. It can be seen that the silicon oxide film formed thereon has low reliability. The gate length L of the samples measured in FIGS. 5 and 6 is 100 μm, and the gate width W is 200 μm. Further, the horizontal axis in FIG. 5 indicates the stress application time, and the vertical axis in FIG. 6 indicates the thickness t _ox of the silicon oxide film. In FIGS. 5 and 6, J _G and J _g ^SL indicate the stress gate current density.

  Therefore, in this embodiment, since the floating gate electrode 16 is made of single crystal silicon having a plane orientation of (100), the bird's beak 15 becomes a highly reliable oxide film, and a high electric field applied during writing / erasing. Generation of traps and defects against stress is suppressed, and stress-induced leakage current can be suppressed. Furthermore, since the floating gate electrode is a single crystal, the shape of the side surface after processing is small in roughness as compared with the conventional case made of polycrystalline silicon, and variation between elements can be suppressed.

  On the other hand, in the case of a floating gate electrode made of polycrystalline silicon as in the prior art, it includes a silicon oxide film grown on a (110) plane or a (111) plane different from the (100) plane, and the tunnel as a whole cell. The reliability of the insulating film is strongly influenced by the oxide film characteristics with low surface orientation other than these (100) planes, so that traps and defect generation become prominent, causing deterioration of data retention characteristics and disturb characteristics. .

  As described in the background art, the technology relating to the floating gate electrode made of single crystal silicon is disclosed in Japanese Patent Application Nos. 07-273229, 2000-260889, and 10-107165. Has been. In these techniques, a semiconductor substrate surface exposed portion is formed at a position away from the element portion, and an amorphous silicon film is solid-phase grown using the exposed portion as a seed. Therefore, these techniques require a lithography process for forming an exposed portion on the surface of the semiconductor substrate, and the exposed portion on the surface of the semiconductor substrate must be formed separately from the elements, which is disadvantageous for miniaturization. In addition, since single crystal can be crystallized by solid phase growth in about 1 micron in the in-plane direction, if a seed is formed at a position distant from the element part, a portion where the floating gate electrode cannot be single crystallized is formed. There are disadvantages such as.

  In contrast, as can be seen from the manufacturing method described later, in this embodiment, since the seed portion is formed at a position adjacent to the tunnel insulating film and the floating gate electrode, the floating gate electrode can be sufficiently single-crystallized. In addition, since this seed part is a part that will be element isolation in the subsequent process, it does not require a new lithography process, so in terms of variation in element characteristics and manufacturing cost, it is conventional technology Better than.

  In addition, when the floating gate electrode is made of polycrystalline silicon as in the prior art, if a highly reliable additive such as fluorine or deuterium is diffused through the floating gate electrode, the floating gate electrode These additives are supplied at high speed and in large quantities due to the grain boundaries present in the. In particular, in the case of fluorine, it is known that the addition of an appropriate amount improves the reliability of the tunnel insulating film, but excessive addition conversely promotes deterioration. For this reason, when the floating gate electrode is made of polycrystalline silicon, it is difficult to control the concentration of additive introduction. Further, with the miniaturization of elements, the amount of crystal grain boundaries contained in one memory cell varies, the distribution of additive elements also varies, and the variation in reliability increases.

  On the other hand, in the present embodiment, the additive diffuses through the subgrain boundaries at a higher speed than in the crystals located on both sides thereof, but the subgrain boundaries are the same for each cell, and the positions thereof are also the same. Since each memory cell is almost the same, it is possible to efficiently supply an additive to the central portion of the tunnel insulating film where the electric field is concentrated by bird's beaks, and to improve the reliability and the variation thereof. Is possible.

  In this embodiment, a single crystal silicon film is used as the floating gate electrode 16, but a Ge single crystal film or a single crystal film in which Ge is added to Si can be used.

  In the present embodiment, tungsten silicide is used as the control gate electrode 20 in the layer 20b stacked on the polycrystalline silicon film 20a. However, other than that, low resistance silicide such as nickel silicide or cobalt silicide, or metal-based conductivity is used. The material can be widely used.

In this embodiment, the interelectrode insulating film 18 has an ONO structure that is a stacked structure of a silicon oxide film, a CVD silicon nitride film, and a CVD silicon oxide film. However, the present invention is not limited to this. rather, such as aluminum oxide _(Al 2 _{O 3)} and HfAlOx, may be used a high dielectric constant material. In addition, oxides, nitrides, or oxynitrides containing at least one element selected from Al, Hf, La, Y, Ce, Ti, Zr, Si, and Ta are widely used as a material for the interelectrode insulating film. And a stack of these films can also be used. Furthermore, a laminate in which these high dielectric insulating films and Si oxide films, Si oxynitride films or nitride films are combined may be used.

  Next, a method for manufacturing the nonvolatile semiconductor memory device of this embodiment will be described with reference to FIGS. FIGS. 8A to 15B are cross-sectional views illustrating the manufacturing process of the nonvolatile semiconductor memory device of the present embodiment, and are FIGS. 8A, 9A, 10A, and 11. (A), 12 (a), 13 (a), 14 (a), and 15 (a) are cross-sectional views in the direction parallel to the bit line, and FIGS. 8 (b), 9 (b), 10 ( b), 11 (b), 12 (b), 13 (b), 14 (b), and 15 (b) are cross-sectional views in the direction parallel to the word lines. 8 (a), 9 (a), 10 (a), 11 (a), 12 (a), 13 (a), 14 (a), and 15 (a) are shown in FIG. ), 9 (b), 10 (b), 11 (b), 12 (b), 13 (b), 14 (b), and 15 (b) are sectional views cut along the cutting line BB shown in FIG. is there.

  First, as shown in FIG. 8A, a SiON film having a thickness of about 7 nm to 8 nm serving as a tunnel insulating film is formed on the surface of a p-type silicon substrate 1 doped with a desired impurity and having a plane orientation of (100). 14 was formed by a thermal oxidation method and a thermal nitridation method, and then an amorphous silicon film 31 doped with phosphorus and having a thickness of 60 nm serving as a floating gate electrode was deposited by a CVD (chemical vapor deposition) method. The temperature at this time was 420 degreeC. Subsequently, a silicon nitride film 32 serving as a mask material was deposited on the amorphous silicon film 31. At this time, the deposition temperature of the silicon nitride film 32 needs to be performed at a temperature at which the amorphous silicon film 31 does not crystallize, and is preferably 600 ° C. or lower, preferably 500 ° C. or lower. Further, instead of thermal CVD, a deposition method using excited species such as plasma CVD may be used. In this case, the silicon nitride film 32 can be sufficiently deposited at 500 ° C. or lower. Thereafter, a resist mask (not shown) is formed on the silicon nitride film 32, and the silicon nitride film 32, the amorphous silicon film 31, and the tunnel insulating film 14 are formed by reactive ion etching (RIE). Etching was sequentially performed until the surface of the silicon substrate 1 was exposed, and the region where the surface of the silicon substrate 1 was exposed was etched to form an element isolation groove 33 having a depth of 100 nm (see FIG. 8B). Thereafter, the resist mask is removed.

Next, as shown in FIGS. 9A and 9B, an amorphous silicon film 34 is deposited again on the entire surface. The temperature at this time was 420 degreeC. Prior to the deposition of the amorphous silicon film 34, the natural oxide film on the exposed surface of the silicon substrate 1 serving as a seed for crystal growth (solid phase growth) is removed by, for example, dilute hydrofluoric acid treatment. Yes. Furthermore, it is preferable that the surface density of oxygen at the interface 35 between the silicon substrate 1 serving as a seed and the amorphous silicon film 34 is 1 × 10 ¹⁵ atoms / cm ² or less. If this condition is satisfied, solid phase epitaxial growth described later becomes possible.

  Next, for example, heat treatment is performed between 550 ° C. and 700 ° C. Then, as shown in FIGS. 10A and 10B, solid phase epitaxial growth starts from the surface 35a of each silicon substrate 1 to be the seed, and the amorphous silicon film 34 becomes a single crystal silicon film 36. The amorphous silicon film 31 to be the floating gate electrode 16 is also solid-phase epitaxially grown in the lateral direction to be single crystallized. Then, the solid phase growth is completed when the forefront of solid phase epitaxial growth from adjacent seeds collides. At this time, as shown in FIG. 10B, a portion where the forefront of solid phase epitaxial growth collides is formed as a sub-grain boundary 17 in the central portion of the floating gate electrode 16.

  Next, as shown in FIGS. 11A and 11B, the entire surface is etched again by the reactive ion etching method. At this time, the silicon nitride film 32 deposited on the floating gate electrode 16 again functions as a mask material, and the element isolation trench 37 is formed. Thereafter, a silicon oxide film (not shown) having a thickness of 5 nm was formed by a thermal oxidation method for the purpose of damage recovery by etching or the like. At this time, bird's beaks are generated in the tunnel insulating film 14. However, this bird's beak is an oxide film similar to the thermal oxide film on the (100) plane of the silicon substrate 1 with little variation between the elements because the floating gate electrode 16 is a single crystal silicon film. It has the property that it is difficult to generate traps and defects against electrical stress.

  Next, as shown in FIGS. 12A and 12B, a silicon oxide film 3 for element isolation was deposited on the entire surface to completely fill the element isolation trench 37. Thereafter, the silicon oxide film 3 was removed by CMP (chemical mechanical polishing) method until the upper surface of the silicon nitride film 32 was exposed, and the surface of the silicon oxide film 3 was planarized.

  Next, as shown in FIGS. 13A and 13B, the exposed silicon nitride film 32 is selectively removed by etching. Then, a part of the side surface of the silicon oxide film 3 is exposed. Thereafter, the exposed upper surface and part of the side surface of the silicon oxide film 3 were removed by etching with a diluted hydrofluoric acid solution or the like to expose part of the side surface of the floating gate electrode 16 made of single crystal. Subsequently, an interelectrode insulating film 18 having an ONO structure made of a silicon oxide film having a thickness of 15 nm, a CVD silicon nitride film, and a CVD silicon oxide film was formed on the entire surface.

Next, as shown in FIGS. 14A and 14B, an n ⁺ -type polycrystalline silicon film 20a doped with phosphorus by a CVD method is deposited as a control gate electrode at 620 ° C. and formed thereon. By forming a tungsten silicide (WSi _x ) film 22b, a conductive layer 20 having a two-layer structure of WSi _x film 20b / polycrystalline Si film 20a and having a thickness of 100 nm was formed. Here, the WSi _x film 20a was formed by depositing W using a CVD method using W (CO) ₆ as a source gas, and converting the polycrystalline silicon film 20a to WSi _x in a subsequent thermal process.

  Note that the manufacturing method of these films is not limited to the method shown here, and other source gases may be used. In addition to ALD (Atomic Layer Deposition) and CVD methods, for example, sputtering, vapor deposition, laser ablation, MBE (Molecular Beam Epitaxy), and film formation methods combining these methods are also possible.

  Thereafter, the WSix film 20b, the polycrystalline silicon film 20a, the interelectrode insulating film 18, the floating gate electrode 16 made of single crystal silicon, and the tunnel insulating film 14 are sequentially etched by RIE using a resist mask (not shown). Thus, a groove 38 was formed in a direction parallel to the word line. As a result, a gate shape composed of a laminated structure of the tunnel insulating film 14, the floating gate electrode 16, the interelectrode insulating film 18, and the control gate electrode 20 is defined.

Finally, as shown in FIGS. 15A and 15B, a silicon oxide film 22 called an electrode side wall oxide film is formed on the exposed surface of the gate by a thermal oxidation method, and then n is formed using an ion implantation method. ^{A +} -type source / drain region 12 was formed. Further, an interlayer insulating film 24 such as a silicon oxide film was formed by a CVD method so as to cover the entire surface. Thereafter, a wiring layer and the like are formed by a well-known method to complete the nonvolatile semiconductor memory device.

As described above, the results of comparison between SILC and ΔVge when a constant current stress is applied to the memory cell formed according to the present embodiment are compared with the conventional technique, that is, when the floating gate electrode is formed of a polycrystalline silicon film. 16 shows. Here, the values are standardized with reference to the values of the conventional memory cells. Further, as shown in FIG. 17, the ΔVge described here changes the gate voltage when a constant current stress corresponding to the write voltage is applied. At this time, the amount of electron injection is 2 C / cm ^2. Is defined as ΔVge. That is, ΔVge is related to the amount of traps formed in the film at the time of constant current stress. As can be seen from FIG. 16, both the SILC and ΔVge are suppressed to be lower in the memory cell according to the present embodiment than in the prior art. As described above, the origins of SILC and ΔVge are traps and defects generated due to local breakdown of weak structural portions in the tunnel insulating film by hot carriers due to application of electrical stress.

  In the conventional memory cell, as shown in FIG. 18, since the floating gate electrode 50 is a polycrystalline silicon film, the bird's beak portion 52 formed in the tunnel insulating film 14 is formed by oxidation of crystal grains having various plane orientations. The film is increased by an oxide film containing a lot of unstable weak bonds other than the (100) plane. For this reason, the deterioration of ΔVge and SILC due to the application of electrical stress is remarkable.

  On the other hand, in this embodiment, as described above, the floating gate electrode is a single crystal silicon film, and the plane orientation is the same as that of the silicon substrate. Therefore, the increased portion (bird's beak) of the tunnel insulating film is As a result, the oxide film has a stronger bond. For this reason, it becomes possible to suppress deterioration against electrical stress application. In addition, since the floating gate electrode is a single crystal silicon film, variations in dimensions and the like due to processing (patterning) of the floating gate electrode can be suppressed. Therefore, variations in characteristics and reliability among elements (memory cells) are also caused. Therefore, it is possible to suppress more than the conventional memory cell.

  As described above, according to the present embodiment, variation in characteristics of the floating gate electrode can be suppressed to the minimum, deterioration of the reliability of the tunnel insulating film can be prevented, and stress-induced leakage current can be suppressed. can do.

(Second Embodiment)
Next, a method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the present invention will be described with reference to FIGS. The nonvolatile semiconductor memory device manufactured by the manufacturing method of this embodiment is the nonvolatile semiconductor memory device of the first embodiment shown in FIGS. 1 and 2, and the manufacturing process thereof is shown in FIGS. Shown in (b). 19 (a), 20 (a), 21 (a), and 22 (a) are cross-sectional views in the direction parallel to the bit line, and FIGS. 19 (b), 20 (b), 21 (b), And 22 (b) are sectional views in the direction parallel to the word lines. 19 (a), 20 (a), 21 (a), and 22 (a) are cuts shown in FIGS. 19 (b), 20 (b), 21 (b), and 22 (b), respectively. It is sectional drawing cut | disconnected by line BB.

  First, as shown in FIGS. 19A and 19B, a thickness of about 7 nm serving as a tunnel insulating film is formed on the surface of a p-type silicon substrate 1 doped with a desired impurity and having a plane orientation of (100). The SiON film 14 having a thickness of 8 nm was formed by thermal oxidation and thermal nitridation, and then an amorphous silicon film 31 doped with phosphorus having a thickness of 60 nm to be a floating gate electrode was deposited by CVD. The temperature at this time was 420 degreeC. Subsequently, a silicon nitride film 32 serving as a mask material was deposited on the amorphous silicon film 31. At this time, the deposition temperature of the silicon nitride film 32 needs to be a temperature at which the amorphous silicon film 31 does not crystallize, and is preferably 600 ° C. or less, preferably 500 ° C. or less. Further, instead of thermal CVD, a deposition method using excited species such as plasma CVD may be used. In this case, it is possible to sufficiently deposit a silicon nitride film at 500 ° C. or lower. Thereafter, a resist mask (not shown) is formed on the silicon nitride film 32, and the silicon nitride film 32, the amorphous silicon film 31, and the tunnel insulating film 14 are sequentially formed by RIE until the surface of the silicon substrate 1 is exposed. Etching process. In the manufacturing method of the present embodiment, unlike the manufacturing method described in the first embodiment, the groove 33 is not formed in the silicon substrate 1, and the etching is terminated when the surface of the silicon substrate 1 is exposed.

Next, as shown in FIGS. 20A and 20B, an amorphous silicon film 34 is deposited on the entire surface. The temperature at this time was 420 degreeC. Before the amorphous silicon film 34 is deposited, the natural oxide film on the surface of the silicon substrate 1 that becomes a seed for crystal growth (solid phase growth) is removed by, for example, dilute hydrofluoric acid treatment. Furthermore, it is preferable that the surface density of oxygen at the interface 35 between the silicon substrate 1 serving as a seed and the amorphous silicon film 34 is 1 × 10 ¹⁵ atoms / cm ² or less. If this condition is satisfied, solid phase epitaxial growth described later becomes possible.

  Next, for example, when heat treatment is performed between 550 ° C. and 700 ° C., as shown in FIGS. 21A and 21B, solid phase epitaxial growth starts from the surface 35a of each silicon substrate 1 serving as the seed, While the amorphous silicon film 34 becomes the single crystal silicon film 36, the portion of the amorphous silicon film 31 that becomes the floating gate electrode 16 is also crystallized by solid phase epitaxial growth in the lateral direction. Then, the solid phase growth is completed when the forefront of solid phase epitaxial growth from adjacent seeds collides. At this time, as shown in FIG. 21B, as in the first embodiment, a portion where the forefront of solid-phase epitaxial growth collides is formed as a subgrain boundary 17 in the central portion of the floating gate electrode 16.

  Next, as shown in FIGS. 22A and 22B, the entire surface is etched again by the reactive ion etching method. At this time, the silicon nitride film 32 deposited on the floating gate electrode 16 again functions as a mask material, and the single crystal silicon layer 36 and the silicon substrate 1 are etched to form an element isolation groove 37 having a depth of about 100 nm. Is done. Thereafter, in the same manner as described in the first embodiment, a silicon oxide film (not shown) having a thickness of 5 nm was formed by thermal oxidation for the purpose of damage recovery by etching and the like. At this time, bird's beaks are generated in the tunnel insulating film, but since the floating gate electrode 16 is a single crystal silicon film, there is little variation between elements (memory cells) and the plane orientation of the silicon substrate 1 ( Since it is the same as the thermal oxide film on the (100) plane, an oxide film that hardly generates traps and defects with respect to electrical stress is formed as a bird's beak.

  Thereafter, the steps shown in FIGS. 12A, 12B to 15A, 15B of the first embodiment are similarly performed to complete the nonvolatile semiconductor memory device.

  Unlike the manufacturing method described in the first embodiment, the manufacturing method according to the present embodiment has no trench formed in the silicon substrate 1 before the single crystallization step. And the seed portion that is the starting point of solid phase epitaxial growth is closer. That is, since the distance from the seed portion to the floating gate electrode 16 is shortened, the time required for solid phase epitaxial growth (time required for single crystallization of the floating gate electrode 16) can be shortened, and the solid phase growth distance. Therefore, generation of crystal defects can be further suppressed.

  Similar to the first embodiment, this embodiment can also minimize the variation in characteristics of the floating gate electrode, can prevent a decrease in the reliability of the tunnel insulating film, and can suppress the stress-induced leakage current. be able to.

(Third embodiment)
Next, a method for fabricating the nonvolatile semiconductor memory device according to the third embodiment of the present invention will be described with reference to FIGS. The nonvolatile semiconductor memory device manufactured by the manufacturing method of this embodiment is the nonvolatile semiconductor memory device of the first embodiment shown in FIGS. 1 and 2, and the manufacturing process thereof is shown in FIGS. Shown in (b). 23 (a), 24 (a), 25 (a), 26 (a), 27 (a), and 28 (a) are cross-sectional views in a direction parallel to the bit line, and FIG. Reference numerals 24 (b), 25 (b), 26 (b), 27 (b), and 28 (b) are cross-sectional views in the direction parallel to the word lines. 23 (a), 24 (a), 25 (a), 26 (a), 27 (a), and 28 (a) are respectively shown in FIGS. 23 (b), 24 (b), and 25 (b). ), 26 (b), 27 (b), and 28 (b) are cross-sectional views taken along the cutting line BB.

  The process up to the step of forming the interelectrode insulating film 18 having the ONO structure is performed in the same manner as in the first embodiment (see FIGS. 13A and 13B). Therefore, as in the first embodiment, this embodiment can also minimize the variation in characteristics of the floating gate electrode, can prevent a decrease in the reliability of the tunnel insulating film, and can reduce the stress-induced leakage current. Can be suppressed.

After the interelectrode insulating film 18 is formed, as shown in FIGS. 23A and 23B, an n ⁺ -type amorphous silicon film 19 doped with phosphorus by CVD is used as a control gate electrode at 420 ° C. A tungsten silicide (WSi _x ) film 20b is formed thereon, thereby forming an electrode layer having a two-layer structure of WSi film 20b / amorphous silicon film 19 and a thickness of 100 nm. Here, the WSi film 20b was formed by depositing W using a CVD method using W (CO) ₆ as a source gas and converting the amorphous silicon film 19 into WSi _x in a subsequent thermal process. Note that the manufacturing method of these films is not limited to the method shown here, and other source gases may be used. In addition to ALD and CVD methods, for example, sputtering, vapor deposition, laser ablation, MBE, and film formation methods combining these methods are also possible. Subsequently, a silicon nitride film 21 serving as a mask material was deposited on the WSi _x film 20b. At this time, the silicon nitride film 21 needs to be deposited at a temperature at which the amorphous silicon film 19 does not crystallize, and is deposited at 600 ° C. or lower, preferably 500 ° C. or lower. Further, instead of thermal CVD, a deposition method using excited species such as plasma CVD may be used. In this case, a silicon nitride film can be sufficiently deposited at 500 ° C. or lower.

Next, a resist mask (not shown) is formed on the silicon nitride film 21, and the silicon nitride film 21, the WSi _x film 20b, the amorphous silicon film 19, the interelectrode insulating film 18 having an ONO structure are formed by RIE. The floating gate electrode 16 and the tunnel insulating film 14 made of single crystal silicon were sequentially etched to form a trench 38 in the word line direction as shown in FIGS. 24 (a) and 24 (b).

Next, as shown in FIGS. 25A and 25B, an amorphous silicon film 23 is deposited again on the entire surface. The temperature at this time was 420 degreeC. Before the amorphous silicon film 23 is deposited, the natural oxide film on the surface of the silicon substrate 1 that serves as a seed for crystal growth (solid phase growth) is removed by, for example, dilute hydrofluoric acid treatment. In this case, the seed portion for solid phase epitaxial growth is a portion that becomes a source / drain region in a later step. Further, it is preferred that the oxygen of the surface density at the interface between the silicon substrate 1 and the amorphous silicon film 32 serving as a seed for this time is 1 × ¹⁰ 15 atom / cm ² or less. If this condition is satisfied, solid phase epitaxial growth is possible.

  Next, for example, heat treatment is performed between 550 ° C. and 700 ° C. Then, as shown in FIGS. 26 (a) and 26 (b), solid phase epitaxial growth starts from the surface 35a of each silicon substrate 1 serving as a seed, and the amorphous silicon film 23 becomes the single crystal silicon film 26. The amorphous silicon film 19 to be the control gate electrode is also solid-phase epitaxially grown in the lateral direction to be single crystallized. Then, the solid phase growth is completed when the forefront of solid phase epitaxial growth from adjacent seeds collides. At this time, a portion where the forefront of the solid phase epitaxial growth collides is formed as a sub-grain boundary 27 in the central portion of the control gate electrode 20c and in the word line direction. That is, the sub-boundary 17 at the center of the floating gate electrode 16 and the sub-boundary 27 at the center of the control gate electrode 20c are substantially orthogonal to each other.

Next, as shown in FIGS. 27A and 27B, the entire surface is etched again by the reactive ion etching method. At this time, the silicon nitride film 21 deposited on the WSi _x film 20b again functions as a mask material, and is made of the WSi _x film 20b, the single crystal silicon film 20c, the interelectrode insulating film 18 having an ONO structure, and single crystal silicon. The floating gate electrode 16 and the tunnel insulating film 14 are sequentially etched to form a trench 38 in the word line direction again as shown in FIG. Here, since the silicon nitride film 21 functions as a mask, a lithography process is not added, and an element region is formed in a self-aligning manner. As a result, a gate shape composed of a laminated structure of the tunnel insulating film 14, the floating gate electrode 16, the interelectrode insulating film 18, and the control gate electrode 20 is defined.

Finally, as shown in FIGS. 28A and 28B, a silicon oxide film 22 called an electrode side wall oxide film is formed on the exposed surface of the gate by a thermal oxidation method, and then an n ⁺ type is formed using an ion implantation method. Source / drain regions 12 were formed. Further, an interlayer insulating film 24 such as a silicon oxide film was formed by a CVD method so as to cover the entire surface. Thereafter, a wiring layer and the like are formed by a well-known method to complete the nonvolatile semiconductor memory cell.

  As described above, in the memory cell formed according to the present embodiment, not only the floating gate electrode 16 but also the control gate electrode 20 can be single-crystallized. It is possible to suppress the deterioration of characteristics with respect to application of a high electric field during erasing. Further, as in the case of single crystallization of the floating gate electrode 16, the shape of the side surface after processing of the control gate electrode 20 and the shape of the side surface after the post-oxidation process are smoother than in the case of polycrystalline silicon, and between the memory cells. Variation can also be reduced. Thereby, especially when the miniaturization of the memory cell is advanced, the variation in the area of the control gate electrode 20 is suppressed, and the variation in the coupling ratio between the inter-electrode insulating film and the tunnel insulating film, which is important in the nonvolatile semiconductor memory device. Thus, the memory cell characteristics can be homogenized.

In the present embodiment, the ONO film is used as the interelectrode insulating film. However, when a high dielectric material such as HfO ₂ or HfSiO is used as the interelectrode insulating film material, Oxygen easily oxidizes silicon that comes into contact with it, and a low dielectric constant layer called a interface layer composed mainly of a silicon oxide film is formed.

  When the floating gate electrode and the control gate electrode are made of a polycrystalline silicon film as in the prior art, the thickness of the interface layer that grows because of the polycrystalline silicon film varies depending on the plane orientation, particularly at the edges. Cause variations. This causes variations in the characteristics and reliability between elements.

  In contrast, in this embodiment, both the floating gate electrode and the control gate electrode are made into a single crystal, and since both use the silicon substrate as a seed for solid phase epitaxial growth, the plane orientation of both gate electrodes is The film quality and film thickness of the interface layer above and below the high dielectric film are made uniform, and variations in characteristics and reliability between elements can be suppressed.

(Fourth embodiment)
Next, a non-volatile semiconductor memory device according to a fourth embodiment of the present invention is described with reference to FIGS.

  The nonvolatile semiconductor memory device according to the present embodiment is the same as the nonvolatile semiconductor memory device according to the first embodiment shown in FIGS. 1 and 2, in order to make the tunnel insulating film 14 highly reliable. The structure is introduced into the membrane.

  In general, a technique for introducing deuterium or a halogen element, which is an isotope of hydrogen, is known in order to improve the reliability of a tunnel insulating film. For example, as disclosed in JP-A-8-116059, when fluorine is introduced into the tunnel insulating film, the fluorine diffuses into the tunnel film. However, as shown in FIG. 29, the floating gate electrode 50 made of polycrystalline silicon is introduced into the tunnel insulating film 14 because the diffusion of the halogen element through the polycrystalline silicon grain boundary is fast. It is difficult to control the fluorine concentration. Further, when the memory cell is miniaturized, the position and amount of crystal grain boundaries vary from memory cell to memory cell, and the amount of fluorine added to the tunnel insulating film 14 varies accordingly. It becomes difficult to realize.

  On the other hand, in the nonvolatile semiconductor memory device of this embodiment, the floating gate electrode 16 is a single crystal silicon film, and the sub-grain boundary 17 in the floating gate electrode 16 is a bit line at the center of the floating gate electrode 16. Therefore, the positions of the sub-grain openings 17 substantially coincide with each other between the memory cells. For this reason, when deuterium or a halogen element is added to the tunnel insulating film 14 through the floating gate electrode 16, it is possible to suppress the diffusion of an excessive additive element through the crystal grain boundary, and it is uniform and highly reliable. The tunnel insulating film can be obtained.

  In addition, since the sub-grain boundary 17 is formed at substantially the central portion of the floating gate electrode 16, the central portion of the tunnel insulating film 14 has a peak of the concentration of the additive element due to the diffusion of the additive element through the sub-grain boundary 17. The additive is distributed in the area. As described above, the central portion of the tunnel insulating film is thinner than the end portion due to the formation of the bird's beak 15, so that the electric field is concentrated. As a result, the tunnel insulating film is locally deteriorated. However, in this embodiment, since the sub-grain boundary 17 is formed in the substantially central portion of the floating gate electrode 16, an additive is efficiently introduced into that portion. Is possible. In addition, the distribution of the additive element in the tunnel insulating film 14 can be controlled by the timing of fluorine addition. For example, when the additive element is introduced before the floating gate electrode 16 is processed, for example, before the step shown in FIG. 11 in the first embodiment is performed, a peak is formed at the center of the tunnel insulating film 14 as shown in FIG. To be distributed. In this case, the additive element is introduced only in the central portion of the tunnel insulating film 14 where the electric field concentrates, which is suitable for achieving high reliability.

  Further, after the gate electrode 16 is processed, for example, when fluorine is introduced after the step shown in FIG. 11 in the first embodiment is performed, fluorine is also introduced from the end portion. Therefore, as shown in FIG. Can be distributed in a W shape. In this distribution, for example, in the case of a process condition in which processing damage enters remarkably, a strong post-oxidation is performed to recover the damage, but at this time, a trap is applied against application of a high electric field at the time of writing / erasing. It is also possible to apply modification to the end portion that becomes a bird's beak that easily generates defects. Further, the additive element can be selectively introduced into the central portion of the tunnel insulating film 14 due to the formation of the bird's beak, and the trapping and defect generation in the central portion can be suppressed. Become.

  FIG. 32 shows the result of actually evaluating and comparing SILC. Here, the additive element for improving reliability used is fluorine, and the introduction is performed by a general method in which ions are implanted into the gate electrode and introduced into the tunnel insulating film by thermal diffusion. Further, since the concentration of the additive element is proportional to the dose amount of ion implantation into the gate electrode, the horizontal axis represents the dose amount of additive element. As can be seen from FIG. 32, SILC is suppressed by addition of fluorine even when the gate electrode is polycrystalline as in the prior art. In addition, it can be seen that SILC is further suppressed when the gate electrode according to the present embodiment is single-crystallized and a sub-grain boundary is formed at the center. This is presumably because fluorine atoms were efficiently introduced into the tunnel insulating film where defects and traps were mainly formed when a high electric field stress was applied.

  In the present embodiment, fluorine is used as an additive element, but other halogen elements or deuterium can be used.

  As described above, according to the present embodiment, it is possible to efficiently introduce an additive element for high reliability into a portion where defects and traps are mainly formed in a tunnel insulating film when a high electric field stress is applied. Therefore, it is possible to make a tunnel insulating film with high reliability, minimizing variation in characteristics of the floating gate electrode, preventing deterioration of the reliability of the tunnel insulating film, and suppressing stress-induced leakage current It becomes possible to do.

(Fifth embodiment)
Next, a method for manufacturing a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention will be described. The nonvolatile semiconductor memory device manufactured by the manufacturing method according to the present embodiment is a SONOS type nonvolatile semiconductor memory device, and its manufacturing process is shown in FIGS. 33 (a) to 41 (b). 33 (a), 34 (a), 35 (a), 36 (a), 37 (a), 38 (a), 39 (a), 40 (a), and 41 (a) are bit lines. It is sectional drawing of a parallel direction, FIG. 33 (b), 34 (b), 35 (b), 36 (b), 37 (b), 38 (b), 39 (b), 40 (b), And 41 (b) are cross-sectional views in the direction parallel to the word lines. 33 (a), 34 (a), 35 (a), 36 (a), 37 (a), 38 (a), 39 (a), 40 (a), and 41 (a) are respectively shown in FIG. 33 (b), 34 (b), 35 (b), 36 (b), 37 (b), 38 (b), 39 (b), 40 (b), and 41 (b) shown in FIG. It is sectional drawing cut | disconnected by line BB.

First, as shown in FIGS. 33 (a) and 33 (b), a thickness of about a tunnel insulating film is formed on the surface of a p-type silicon substrate 1 doped with a desired impurity and having a plane orientation of (100). A 4 nm to 5 nm SiON film 14 is formed by a thermal oxidation method and a thermal nitridation method. Thereafter, a silicon nitride film 60 having a thickness of 60 nm serving as a charge storage layer was deposited by a CVD method. Gas used at this time, for example, dichlorosilane performed using _(SiH 2 Cl ₂₎ and ammonia _(NH 3), or hexachlorodisilane _(Si 2 Cl ₆₎ and ammonia (NH _3), the deposition temperature is about 450 ° C. To 800 ° C. Subsequently, a resist mask (not shown) is formed on the silicon nitride film 60, and the silicon nitride film 60 and the SiON film 14 are sequentially etched by RIE until the surface of the silicon substrate 1 is exposed. The exposed region of the substrate 1 was etched to form an element isolation groove 62 having a depth of 100 nm. Thereafter, the resist mask is removed.

  Next, as shown in FIGS. 34A and 34B, a silicon oxide film 3 for element isolation was deposited on the entire surface to completely fill the element isolation trench 62. Thereafter, the silicon oxide film 3 was removed by CMP until the upper surface of the silicon nitride film 60 was exposed, and the surface of the silicon oxide film 3 was planarized.

Next, as shown in FIGS. 35A and 35B, the exposed surface of the silicon oxide film 3 was removed by etching with a dilute hydrofluoric acid solution to expose the side wall surface of the silicon nitride film 60. Thereafter, a hafnium aluminate (HfAlO _x ) film 64 having a thickness of 15 nm to be a block insulating film was formed on the entire surface. The formation of the HfAlO _x film 64 is performed at 250 ° C. using an ALD method using Al (CH ₃ ) ₃ , Hf [N (CH ₃ ) ₂ ] ₄ and H ₂ O as raw materials, and subsequently 1000 ° C. , N ₂ , and annealing at 1 atmosphere. Here, in the present embodiment, the HfAlOx film has been described as an example of the block insulating film 64. However, the present invention is not limited to this. For example, the silicon oxide film, the SiON film, the alumina (Al ₂ O ₃ ) film, the hafnia (HfO) ₂ ), zirconia (ZrO ₂ ), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminate (LaAlO ₃ ), or these silicate materials and laminated films can be used to obtain the same effect. Further, in this embodiment, a structure is used in which the surface of the element isolation silicon oxide film 3 is slightly etched so that the block insulating film 64 has a step, but the present invention is not limited to this. The insulating film 64 may be configured to be flat, and this can be selected according to a desired capacitance ratio between the tunnel insulating film 14 and the charge storage layer 60.

Next, as shown in FIGS. 36A and 36B, an n ⁺ -type amorphous silicon film 66 doped with phosphorus by a CVD method is deposited and formed at 420 ° C. as a control gate electrode. A WSi _x film 68 was formed thereon, thereby forming an electrode layer having a two-layer structure of WSi _x film 68 / amorphous silicon film 66 with a thickness of 100 nm. Here, the WSi _x film 68 is formed by depositing W using a CVD method using W (CO) ₆ as a source gas and converting the amorphous silicon film 66 into WSi _x in a subsequent thermal process. . Note that the manufacturing method of these films is not limited to the method shown here, and other source gases may be used. In addition to ALD and CVD methods, for example, sputtering, vapor deposition, laser ablation, MBE, and film formation methods combining these methods are also possible. Subsequently, a silicon nitride film 70 serving as a mask material was deposited on the WSix film 68 serving as a control gate electrode. At this time, the silicon nitride film 70 needs to be deposited at a temperature at which the amorphous silicon film 66 does not crystallize, and is deposited at 600 ° C. or lower, preferably 500 ° C. or lower. Further, instead of thermal CVD, a deposition method using excited species such as plasma CVD may be used. In this case, the silicon nitride film 70 can be sufficiently deposited at 500 ° C. or lower.

Next, a resist mask (not shown) is used as a silicon nitride film 70, a WSi _x film 68, an amorphous silicon film 66, an HfAlOx film 64, a silicon nitride film 60 as a charge storage film, and a SiON film 14 as a tunnel insulating film. Were sequentially etched to form a groove 72 in the word line direction (see FIGS. 37A and 37B).

Next, as shown in FIGS. 38A and 38B, an amorphous silicon film 74 is deposited on the entire surface. The temperature at this time was 420 degreeC. Further, before the amorphous silicon film 74 is deposited, the natural oxide film on the surface of the silicon substrate 1 that becomes a seed for crystal growth (solid phase growth) is removed by, for example, dilute hydrofluoric acid treatment. In this case, the seed part for solid phase epitaxial growth is a part that becomes a source / drain region in a later step. Furthermore, it is preferable that the surface density of oxygen is 1 × 10 ¹⁵ atoms / cm ² or less at the interface between the silicon substrate serving as a seed and the amorphous silicon film. If this condition is satisfied, solid phase epitaxial growth is possible.

  Next, for example, heat treatment is performed between 550 ° C. and 700 ° C. Then, as shown in FIGS. 39 (a) and 39 (b), solid phase epitaxial growth starts from the surface 35a of each silicon substrate 1 to be a seed, and the amorphous silicon film 74 becomes a single crystal silicon film 75. The amorphous silicon film 66 that becomes the control gate electrode is also crystallized by solid phase epitaxial growth in the lateral direction. Then, the solid phase growth is completed when the forefront of solid phase epitaxial growth from adjacent seeds collides. At this time, the portion where the forefront of the solid phase epitaxial growth collides is the sub-grain boundary 69 in the central portion of the single crystal silicon film 67 and in the direction parallel to the word line, that is, the direction in which the source region and drain region 80 described later are opposed. It is formed along the orthogonal direction.

  Next, as shown in FIGS. 40A and 40B, the entire surface is etched again by the reactive ion etching method. At this time, the silicon nitride film 70 again functions as a mask material, and the control gate electrode 65, the block insulating film 64, the silicon nitride film 60, and the tunnel insulating film 14 composed of the WSix film 68 and the single crystal silicon film 67 are sequentially etched. Thus, as shown in FIG. 40A, the trench 76 in the word line direction is formed again. Here, since the silicon nitride film 70 functions as a mask, a lithography process is not added, and an element region is formed in a self-aligning manner. Thereby, a gate shape composed of a laminated structure of the gate insulating film 14, the charge storage film 60, the block insulating film 64, and the control gate electrode 65 is defined.

Finally, as shown in FIGS. 41A and 41B, a silicon oxide film 78 called an electrode sidewall oxide film is formed on the exposed surface of the gate by a thermal oxidation method, and then an n ⁺ type is formed by using an ion implantation method. Source / drain regions 80 were formed. Further, an interlayer insulating film 82 such as a silicon oxide film was formed by a CVD method so as to cover the entire surface. Thereafter, a wiring layer or the like is formed by a well-known method to complete the SONOS type nonvolatile semiconductor memory device.

  As described above, according to the present embodiment, the control gate electrode 65 of the SONOS type nonvolatile semiconductor memory device can be single-crystallized. Therefore, the roughness of the edge during gate processing is reduced, and the characteristic variation between the memory cells is reduced. Can be suppressed. In this embodiment, HfAlOx is used as the block insulating film 64. However, when such a high dielectric is brought into contact with the silicon film, oxygen in the high dielectric film reacts with the silicon film in a high-temperature heat process, The interface is easily oxidized, and a low dielectric constant layer having a silicon oxide film as a main component called an interface layer is formed.

  When the control gate electrode is a polycrystalline silicon film as in the prior art, the film thickness of the interface layer grown due to the polycrystalline silicon film varies depending on the plane orientation, and the film thickness varies particularly in the short part. This causes variations in the characteristics and reliability between elements.

  In contrast, in the present embodiment, the control gate electrode is made into a single crystal, so that the film quality and film thickness of the interface layer on the high dielectric film are made uniform, and variations in characteristics and reliability between memory cells are suppressed. Is possible.

  In the first to fifth embodiments, the source / drain regions of the memory cell are n-type, but may be p-type. In this case, the semiconductor substrate is n-type. A Ni or Co silicide layer may be formed in the source / drain regions.

  In the first to fifth embodiments, the semiconductor substrate is a bulk substrate, but various semiconductor substrates such as an SOI (Silicon On Insulator) substrate can be used.

  In the first to fifth embodiments, the NAND type nonvolatile semiconductor memory device has been described. However, the present invention can also be applied to a NOR type nonvolatile semiconductor memory device.

  The present invention is not limited to the above-described embodiments, and can be implemented with various modifications to a system LSI semiconductor device in which a memory device and a logic circuit are mounted together.

1 is a cross-sectional view showing a NAND nonvolatile semiconductor memory device according to a first embodiment of the present invention. 1 is a cross-sectional view showing a NAND nonvolatile semiconductor memory device according to a first embodiment. 1 is a perspective view showing a memory cell of a memory device according to a first embodiment. Sectional drawing explaining the problem of the memory cell from which a floating gate electrode consists of polycrystalline silicon. The characteristic view explaining the effect of the memory device of a 1st embodiment. The characteristic view explaining the effect of the memory device of a 1st embodiment. The figure explaining a stress induction leak current. Sectional drawing which shows the manufacturing process of the memory device of 1st Embodiment. Sectional drawing which shows the manufacturing process of the memory device of 1st Embodiment. Sectional drawing which shows the manufacturing process of the memory device of 1st Embodiment. Sectional drawing which shows the manufacturing process of the memory device of 1st Embodiment. Sectional drawing which shows the manufacturing process of the memory device of 1st Embodiment. Sectional drawing which shows the manufacturing process of the memory device of 1st Embodiment. Sectional drawing which shows the manufacturing process of the memory device of 1st Embodiment. Sectional drawing which shows the manufacturing process of the memory device of 1st Embodiment. The figure explaining the effect with respect to the conventional memory device of 1st Embodiment. The figure explaining the definition of (DELTA) Vge. The perspective view explaining the problem of the memory cell in which a floating gate electrode consists of polycrystalline silicon. Sectional drawing which shows the manufacturing process of the manufacturing method by 2nd Embodiment. Sectional drawing which shows the manufacturing process of the manufacturing method by 2nd Embodiment. Sectional drawing which shows the manufacturing process of the manufacturing method by 2nd Embodiment. Sectional drawing which shows the manufacturing process of the manufacturing method by 2nd Embodiment. Sectional drawing which shows the manufacturing process of the manufacturing method by 3rd Embodiment. Sectional drawing which shows the manufacturing process of the manufacturing method by 3rd Embodiment. Sectional drawing which shows the manufacturing process of the manufacturing method by 3rd Embodiment. Sectional drawing which shows the manufacturing process of the manufacturing method by 3rd Embodiment. Sectional drawing which shows the manufacturing process of the manufacturing method by 3rd Embodiment. Sectional drawing which shows the manufacturing process of the manufacturing method by 3rd Embodiment. The perspective view explaining the problem of the memory cell in which a floating gate electrode consists of polycrystalline silicon. The perspective view explaining the characteristic of the non-volatile semiconductor memory device by 4th Embodiment. The perspective view explaining the characteristic of the non-volatile semiconductor memory device by 4th Embodiment. The figure explaining the effect of the non-volatile semiconductor memory device by 4th Embodiment. Sectional drawing which shows the manufacturing process of the manufacturing method by 5th Embodiment. Sectional drawing which shows the manufacturing process of the manufacturing method by 5th Embodiment. Sectional drawing which shows the manufacturing process of the manufacturing method by 5th Embodiment. Sectional drawing which shows the manufacturing process of the manufacturing method by 5th Embodiment. Sectional drawing which shows the manufacturing process of the manufacturing method by 5th Embodiment. Sectional drawing which shows the manufacturing process of the manufacturing method by 5th Embodiment. Sectional drawing which shows the manufacturing process of the manufacturing method by 5th Embodiment. Sectional drawing which shows the manufacturing process of the manufacturing method by 5th Embodiment. Sectional drawing which shows the manufacturing process of the manufacturing method by 5th Embodiment.

Explanation of symbols

1 Silicon substrate
3 Device isolation region 12 Source / drain region 14 Tunnel insulating film
15 Bird's beak 16 Floating gate electrode 17 Subgrain boundary 18 Interelectrode insulating film 19 Amorphous silicon film 20 Control gate electrode 20a Polycrystalline silicon film 20b Tungsten silicide film 21 Silicon nitride film 22 Insulating film (electrode sidewall oxide film)
23 Amorphous silicon film 24 Interlayer insulating film 31 Amorphous silicon film 32 Silicon nitride film 33 Groove 34 Amorphous silicon film 36 Single crystal film 37 Groove 38 Groove 50 Floating gate electrode 52 made of polycrystalline silicon Bird's beak
60 Charge storage layer 64 Block insulating film 65 Control gate electrode 66 Amorphous silicon film 67 Single crystal silicon film 68 Tungsten silicide film 69 Subgrain boundary 70 Silicon nitride film 72 Groove 74 Amorphous silicon film

Claims (12)

A substrate having a semiconductor layer of a first conductivity type;
A pair of second conductivity type source / drain regions provided facing the semiconductor layer;
A first insulating film provided on the semiconductor layer between the source / drain regions;
A floating gate electrode including a single crystal semiconductor provided on the first insulating film and having subgrain boundaries formed in a direction in which the source / drain regions face each other;
A second insulating film provided on the floating gate electrode;
A control gate electrode provided on the second insulating film;
A memory cell having
A semiconductor device comprising:   The first insulating film contains at least one of a halogen element and deuterium as an additive element, and the concentration of the additive element in a cross section of the first insulating film along a direction in which the source / drain regions are opposed to each other. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a distribution that increases immediately below the sub-grain boundary.   The first insulating film includes at least one of a halogen element and deuterium as an additive element, and the concentration of the additive element in a cross section of the first insulating film along a direction in which the source / drain regions are opposed to each other. 2. The semiconductor device according to claim 1, wherein the semiconductor device has a distribution that becomes higher immediately below the sub-grain boundary and at both ends of the first insulating film. A substrate having a semiconductor layer of a first conductivity type;
A pair of second conductivity type source / drain regions provided facing the semiconductor layer;
A first insulating film provided on the semiconductor layer between the impurity regions;
A charge storage film provided on the first insulating film;
A second insulating film provided on the charge storage film;
A control gate electrode including a single crystal semiconductor provided on the second insulating film and having a subgrain boundary formed in a direction orthogonal to a direction in which the source / drain regions oppose each other;
A memory cell having
A semiconductor device comprising: Forming a first insulating film on the semiconductor substrate;
Forming a first amorphous semiconductor film on the first insulating film;
Forming a first mask insulating film on the first amorphous semiconductor film;
Patterning a laminated film composed of the first mask insulating film, the first amorphous semiconductor film, and the first insulating film until at least the surface of the semiconductor substrate is exposed;
Forming a second amorphous semiconductor film so as to cover the patterned laminated film;
By performing heat treatment, the second amorphous semiconductor film is monocrystallized by solid phase epitaxial growth to form a first single crystal film, and the first amorphous semiconductor film is monocrystallized by solid phase epitaxial growth. And forming a second single crystal film;
Removing the first single crystal film by etching;
A method for manufacturing a semiconductor device, comprising: Forming a first insulating film on the semiconductor substrate;
Forming a first amorphous semiconductor film on the first insulating film;
Forming a first mask insulating film on the first amorphous semiconductor film;
Patterning the first laminated film including the first mask insulating film, the first amorphous semiconductor film, and the first insulating film until at least the surface of the semiconductor substrate is exposed;
Forming a second amorphous semiconductor film so as to cover the patterned first laminated film;
By performing heat treatment, the second amorphous semiconductor film is monocrystallized by solid phase epitaxial growth to form a first single crystal film, and the first amorphous semiconductor film is monocrystallized by solid phase epitaxial growth. And forming a second single crystal film;
Removing the first single crystal film by etching and removing a part of the semiconductor substrate; and
Depositing an element isolation insulating film on the entire surface, and planarizing the element isolation insulating film, thereby exposing an upper surface of the first mask insulating film;
Removing the first mask insulating film and exposing an upper surface of the second single crystal film;
Forming a second insulating film so as to cover an upper surface of the second single crystal film;
Forming a third amorphous semiconductor film on the second insulating film;
Forming a second mask insulating film on the third amorphous semiconductor film;
Until the surface of the semiconductor substrate is exposed, the second mask insulating film, the third amorphous semiconductor film, the second insulating film, the second single crystal film, and the first insulating film Patterning a second laminated film made of a film into a gate shape;
Forming a fourth amorphous semiconductor film so as to cover the patterned second laminated film;
By performing heat treatment, the fourth amorphous semiconductor film is monocrystallized by solid phase epitaxial growth to form a third single crystal film, and the third amorphous semiconductor film is monocrystallized by solid phase epitaxial growth. A fourth single crystal film,
Removing the third single crystal film by etching;
A method for manufacturing a semiconductor device, comprising:   7. The method of manufacturing a semiconductor device according to claim 6, wherein the second mask insulating film is formed at a temperature at which the third amorphous semiconductor film is not crystallized.   8. The method of manufacturing a semiconductor device according to claim 5, wherein the first mask insulating film is formed at a temperature at which the first amorphous semiconductor film is not crystallized.   After the step of forming the first single crystal film and before the step of removing the first single crystal film, at least one of a halogen element and deuterium is passed through the second single crystal film. 9. The method for manufacturing a semiconductor device according to claim 5, further comprising a step of adding to the first insulating film.   And a step of adding at least one of a halogen element and deuterium to the first insulating film through the second single crystal film after the step of removing the first single crystal film. A method for manufacturing a semiconductor device according to claim 5. Forming a first insulating film on the semiconductor substrate;
Forming a charge storage film on the first insulating film;
Patterning the first stacked film comprising the charge storage film and the first insulating film by etching and removing a part of the semiconductor substrate;
Depositing an element isolation insulating film on the entire surface, and planarizing the element isolation insulating film, thereby exposing the upper surface of the charge accumulation;
Forming a second insulating film so as to cover the upper surface of the charge storage film;
Forming a first amorphous semiconductor film on the second insulating film;
Forming an insulating film for a mask on the first amorphous semiconductor film;
Until the surface of the semiconductor substrate is exposed, a second insulating film is formed of the mask insulating film, the first amorphous semiconductor film, the second insulating film, the charge storage film, and the first insulating film. Patterning the laminated film into a gate shape;
Forming a second amorphous semiconductor film so as to cover the patterned second laminated film;
By performing heat treatment, the second amorphous semiconductor film is monocrystallized by solid phase epitaxial growth to form a first single crystal film, and the first amorphous semiconductor film is monocrystallized by solid phase epitaxial growth. And forming a second single crystal film;
Removing the first single crystal film by etching;
A method for manufacturing a semiconductor device, comprising:   12. The method of manufacturing a semiconductor device according to claim 11, wherein the formation of the mask insulating film is performed at a temperature at which the first amorphous semiconductor film is not crystallized.

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