JP2009141277A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the damage of a substrate silicon in an opening of an embedded insulating film of an SOI structure and prevent the reduction of contact area with the substrate in the opening of the embedded insulating film. <P>SOLUTION: A semiconductor device, which has SOI structure, is provided with: a silicon substrate 10; an insulating film 11 which is provided on the silicon substrate 10 and has an opening 12 in a part thereof, wherein an upper part of the opening 12 is formed to forward tapered shape structure, in which an upper surface side spread, and a lower part is formed to inverse tapered shape structure, in which a lower surface side spread; a single-crystal silicon layer 14 which is formed on the insulating film 11 and within the opening 12; and a semiconductor device which is formed in the single-crystal silicon layer 14. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device having an SOI (Silicon on Insulator) structure, and more particularly to a semiconductor device in which a seed part is improved and a manufacturing method thereof.

  In recent years, a method of forming a memory cell on an SOI crystal has been proposed in order to suppress the influence of the short channel effect accompanying the miniaturization of the memory cell. In order to manufacture an SOI crystal, a buried oxide film is formed on a silicon substrate, an opening serving as a seed portion is formed in the oxide film, and an amorphous silicon film is formed on and in the oxide film. Then, the amorphous film is annealed to be solid-phase grown to be single crystallized.

  Here, when anisotropic ion etching is performed to form the opening, damage is generated in the silicon substrate, so that crystal defects are likely to occur at the interface between the substrate and the epitaxial layer. Since the crystal defects remaining on the substrate disturb the crystal arrangement even during solid phase epitaxial growth, local crystal defects are likely to occur locally. In the case of anisotropic etching, the buried oxide film is processed at a right angle. However, amorphous silicon deposited in the corner portion accelerates the desorption of hydrogen, so that crystal nuclei are easily formed. When crystal nuclei are formed at the corners, stacking faults and twins are likely to occur.

  For this reason, the opening of the buried oxide film is preferably isotropic etching using hydrofluoric acid or the like rather than reactive ion etching that damages the substrate or opens at a right angle. When the buried oxide film is processed by isotropic etching, the buried oxide film is processed into a forward taper shape with the upper surface widened. The probability of crystal defects is reduced. However, since the opening has a forward tapered shape, there is a problem that the contact area between the opening of the buried oxide film and the substrate becomes extremely small. Further, in the case of isotropic etching, the oxide film has a tail at the bottom of the buried oxide film, which also causes a reduction in the contact area with the substrate.

  When the contact area with the substrate in the opening is reduced, the probability of occurrence of a defective defect locally on the wafer increases. When the omission defect occurs, solid phase growth itself does not occur. Moreover, even if it is electrically conductive, the resistance between the seed layer and the substrate becomes high, so that the substrate voltage of the transistor formed on the seed layer is not constant. For this reason, the threshold value of the transistor varies, which is a factor of decreasing the yield.

Thus, conventionally, the opening of the buried insulating film in the SOI structure is desired to be as small as possible. However, if this is formed by RIE, the substrate silicon is damaged. On the other hand, when the opening is formed by isotropic etching, the contact area with the substrate is reduced due to the bottom of the insulating film under the buried insulating film, and the solid phase growth is adversely affected.
JP 2006-294711 A Japanese Patent Laid-Open No. 11-163303

  The present invention provides a semiconductor device capable of preventing damage to the substrate silicon in the opening of the buried insulating film in the SOI structure and preventing a decrease in contact area with the substrate in the opening of the buried insulating film, and a method for manufacturing the same. With the goal.

  In order to solve the above problems, the present invention adopts the following configuration.

  In other words, a semiconductor device according to one embodiment of the present invention is formed using a silicon substrate and a forward tapered structure which is provided over the silicon substrate, has an opening in a part, and the upper portion of the opening widens on the upper surface side. And an insulating film formed in an inverted taper structure with the lower surface widened at the bottom, a single crystal silicon layer formed on the insulating film and in the opening, and a semiconductor element formed on the single crystal silicon layer, It is characterized by comprising.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming an insulating film on a silicon substrate; and etching a part of the insulating film under a condition that does not damage the surface of the substrate. A step of forming an opening serving as a seed region, and a heat treatment using a gas containing hydrogen or fluorine to round the corners of the insulating film surface of the opening, and the insulating film remaining in the opening Removing the tailing portion, forming an amorphous silicon film on the insulating film and in the opening after the heat treatment, annealing the amorphous silicon film, and solid-phase-growing using the opening as a seed. A step of single-crystallizing the amorphous silicon film, and a step of forming a semiconductor element on the silicon single-crystal layer formed by the solid phase growth. That.

  According to the present invention, it is possible to prevent the substrate silicon from being damaged at the opening of the buried insulating film in the SOI structure, and to prevent the contact area with the substrate at the opening of the buried insulating film from being reduced.

  The details of the present invention will be described below with reference to the illustrated embodiments.

  In the present embodiment, crystal defects in the epitaxial layer, which is a problem in manufacturing a non-volatile semiconductor memory having an SOI structure by solid phase growth, are suppressed, and stable electrical conduction is achieved even in a narrow seed region (opening). Provide a way to get.

  A method for manufacturing the memory cell portion of this embodiment will be described with reference to FIGS. 1 to 7, (a) is a cross-sectional view in the channel length direction (bit line direction), (b) is a cross-sectional view in the channel width direction (word line direction), and (c) is a plan view. Further, (a) shows an A-A ′ section in the plan view (c), and (b) shows a B-B ′ section in the plan view (c).

  First, as shown in FIGS. 1A to 1C, a silicon oxide film 11 serving as a buried insulating film is formed on the surface of a p-type silicon crystal substrate 10 to a thickness of about 30 nm. Subsequently, using a patterned resist (not shown) having an opening width of about 0.1 to 0.2 μm as a mask, a part of the silicon oxide film 11 is isotropically removed using dilute hydrofluoric acid or the like. A part of the silicon crystal substrate was exposed. That is, the openings 12 having a forward taper structure, which become seed regions for solid phase growth described later, were formed in a stripe shape. In this hydrofluoric acid etching, if the opening width 12 is too wide, sufficient overfilling cannot be performed in the subsequent growth of amorphous silicon. Therefore, the etching is performed to a depth of about 30 to 50 nm so as not to spread too much.

  Next, as shown in FIGS. 2A to 2C, heat treatment is performed at a temperature of 800 ° C. to 900 ° C. in a CVD apparatus under a hydrogen atmosphere of 10 to 200 Torr for about 1 to 10 minutes. Thereby, the lower part of the opening part 12 becomes a reverse taper structure where the lower surface side spreads. This is because only the thin portion of the silicon oxide film 11 is removed, and the bottom of the buried insulating film 11 at the bottom of the opening 12 is removed. In addition, this heat treatment rounds the corners of the surface of the silicon oxide film 11 in the opening 12.

  Note that fluorine can be used instead of hydrogen during the heat treatment. In this case, the bottom of the buried insulating film 11 can be removed by lift-off by etching the silicon thinly, and the opening 12 having a reverse tapered structure at the lower portion can be obtained as described above.

  Subsequently, the temperature is lowered to about 500 to 550 ° C. inside the same chamber, and silane gas is introduced under a partial pressure of about 0.2 to 2 Torr. By performing the growth for about 2 hours, an amorphous silicon film 13 of about 200 nm is grown. If the seed region 12 has an opening width of about 0.1 to 0.2 μm, an amorphous silicon surface of about 200 nm is grown so that the surface of the amorphous silicon is substantially flat without a step due to the pattern of the buried insulating film 11. can do.

  Next, as shown in FIGS. 3A to 3C, a heat treatment is performed for about 5 hours in a nitrogen atmosphere at about 600 ° C., and the amorphous silicon film 13 is buried from the seed region 12 into the buried insulating film. Solid-phase growth is performed on the layer 11 to form a single crystal epitaxial silicon layer 14. Subsequently, the epitaxial silicon layer 14 on the buried insulating film 11 is etched back by reactive ion etching, and an epitaxial layer of about 40 nm is formed on the buried insulating film 11 as shown in FIGS. The silicon layer 14 is left.

  In the present embodiment, isotropic etching is performed on the buried insulating film 11, and the processing is performed in a high-temperature reducing atmosphere in the film forming apparatus before the amorphous silicon is grown. For this reason, only the skirt portion of about several nanometers seen in the opening 12 of the buried insulating film 11 can be eliminated. As a result, as shown in FIG. 3A, the shape of the buried insulating film 11 in the vicinity of the seed after the solid phase growth is expanded in the silicon substrate portion below the opening surface and has a narrow constriction on the upper surface of the opening portion. An opening could be obtained.

  As a result of the experiments by the present inventors, in the opening pattern of the seed portion with an opening width of 0.1 μm in the resist, the opening width is expanded to about 0.18 μm above the buried insulating film 11 after the buried insulating film 11 is etched. However, the width of the exposed seed layer under the buried insulating film 11 was only about 0.08 μm. However, by performing 10 Torr hydrogen treatment at 850 ° C. before the amorphous silicon growth, the bottom of the buried insulating film 11 is removed. Crystal defects were hardly observed at the seed part interface, in the vicinity of the opening of the buried insulating film 11, and at the part far from the seed region 12 on the buried insulating film 11. On the other hand, the opening width of the upper surface of the buried insulating film 11 was hardly increased by the hydrogen treatment.

  In addition, according to the present embodiment, the skirt shape in the seed region 12 is improved by the hydrogen treatment before the growth of amorphous silicon, and the area of the seed region 12 is increased. Can be stabilized. For this reason, the variation in the threshold value of the selection gate transistor formed on the seed part region 12 can be improved.

  In this embodiment, the formation of the opening 12 in the buried insulating film 11 is processed only by isotropic etching without performing reactive ion etching. However, when the upper portion of the seed region 12 is further narrowed or when the buried insulating film 11 is thick, anisotropic reactive ion etching is performed partway through the buried insulating film 11, and then wet treatment or bias is performed. Opening may be performed by performing isotropic etching such as radical treatment that does not give any other.

  Here, if only anisotropic ion etching is performed on the opening of the seed region as in the conventional case, the silicon substrate is damaged, and thus crystal defects are likely to occur at the interface between the substrate and the epitaxial layer. In the case of anisotropic etching, since the buried insulating film is processed at a right angle, crystal nuclei are easily formed, and stacking faults and twins are easily generated. Furthermore, in a region away from the seed region, crystal growth from the crystal nucleus formed on the surface of the buried insulating film during the formation of amorphous silicon reaches the surface earlier, and the SOI layer becomes polycrystalline silicon. Sometimes it became. The presence of defects in the SOI layer becomes a carrier trap, which causes a malfunction of a transistor on the SOI.

  On the other hand, when the buried insulating film is processed by isotropic etching, the contact area with the substrate becomes extremely small at the buried insulating film opening, and further, the oxide film is formed below the buried insulating film layer. There is a problem that pulls the tail. This becomes a factor that reduces variations in threshold values of transistors on the SOI and a manufacturing yield.

  On the other hand, as in this embodiment, heat treatment is performed in a hydrogen atmosphere after isotropic etching, and the lower portion of the opening 12 in the seed region is formed in an inverted taper structure to eliminate all of these problems. Can do.

  Next, as shown in FIGS. 4A to 4C, a gate insulating film (tunnel insulating film) 21 having a thickness of about 7 nm is formed on the entire surface by a thermal oxidation method or the like, and a CVD (Chemical Vapor) is formed thereon. A phosphorus-doped polycrystalline silicon layer 22 having a thickness of about 50 nm to be a floating gate electrode was deposited by a Deposition method or the like. Next, a phosphorus-doped polycrystalline silicon layer 22, a gate insulating film (tunnel insulating film) 21, an epitaxial silicon layer 14, a buried insulating film 11, and a silicon crystal substrate 10 are formed using a resist (not shown) patterned in a stripe shape as a mask. The part was removed by the RIE method or the like to form an element isolation trench 23. Subsequently, a silicon oxide film 24 was embedded in the element isolation trench 23 using a coating method or the like. For example, by applying a coating insulating film such as polysilazane, formation of an imperfect buried region called a void can be avoided.

  The lower the dielectric constant of the insulating film 24 of the element isolation material, the higher withstand voltage between adjacent memory cells. Therefore, after application, water vapor oxidation is performed, and impurities such as nitrogen, carbon and hydrogen in the film are formed. It is desirable to desorb and convert it into a silicon oxide film. Further, in order to repair crystal defects generated on the surface of the groove when the element isolation groove 23 is formed, thermal oxidation or radical oxidation may be performed before or after the coating insulating film 24 is embedded. Furthermore, in order to improve the insulating property of the buried insulating film 24, a CVD insulating film and a coating insulating film may be combined and buried.

  Next, as shown in FIGS. 5A to 5C, an alumina film 25 having a thickness of about 15 nm serving as an interelectrode insulating film was formed on the entire surface by an ALD (Atomic Layer Deposition) method or the like. Next, using a patterned resist (not shown) as a mask, a slit portion 26 having a width of about 50 nm is formed in a region where the selection gate transistor is to be formed by using the RIE method or the like, and a part of the phosphorus-doped polycrystalline silicon layer 22 is formed. Was exposed.

  Next, as shown in FIGS. 6A to 6C, a phosphorus-doped silicon layer 27 was formed again on the entire surface. At this time, the phosphorus-doped polycrystalline silicon layer 22 and the phosphorus-doped silicon layer 27 were electrically connected in the slit portion 26. Thereafter, using a resist (not shown) patterned in a stripe shape as a mask, the phosphorus-doped silicon layer 27, the alumina film 25, and part of the phosphorus-doped silicon layer 22 are removed by the RIE method or the like to form a two-layer gate of the memory cell. A stacked gate electrode structure of structure and select gate transistor was formed. That is, the gate structure of the selection transistor was formed in the silicon layer 14 on the seed portion 12, and the gate structure of the nonvolatile memory cell was formed in the silicon layer 14 on the buried insulating film 11.

  Next, as shown in FIGS. 7A to 7C, an n-type impurity diffusion layer 14a having a desired impurity concentration distribution is formed in the epitaxial silicon layer 14 by combining an ion implantation method and a thermal diffusion method. did. Next, an interlayer insulating film 28 is formed by CVD or the like to cover the two-layer gate structure of the memory cell and the stacked gate electrode structure of the select gate transistor, and an opening is formed on the impurity diffusion layer of the select gate transistor by a well-known method. Then, a bit line contact 29 (and source line contact) was formed by embedding a conductor such as tungsten. Thereafter, the nonvolatile semiconductor memory device was completed by a known method.

  As described above, according to this embodiment, since the shape of the buried insulating film 11 in the seed region 12 is smoothly formed, an excellent crystalline memory cell with few twins and stacking faults can be obtained in the memory cell region. Can do. Further, since the bottom of the buried insulating film 11 is removed, reliable contact between the epitaxial silicon layer 14 and the substrate 10 can be realized, and the variation in effective substrate voltage applied to the select gate transistor can be suppressed. it can.

  In addition, this invention is not limited to embodiment mentioned above. FIGS. 7A to 7C show an example in which the n-type impurity diffusion layer 14a of each memory cell in the channel length direction is connected. However, a p-type diffusion layer is used with the gate electrode of the cell transistor as a mask. You may make it form. In the embodiment, the method of manufacturing the memory cell using the floating gate electrode as the charge storage layer has been described. However, the same method can be used for a memory cell such as a MONOS type cell using an insulating film such as a silicon nitride film as the charge storage layer. Is applicable.

  In the embodiment, the nonvolatile semiconductor memory has been described as an example. However, the present invention can be applied to various semiconductor devices in which a semiconductor element is formed on an SOI crystal. In addition, various modifications can be made without departing from the scope of the present invention.

FIG. 4 is a plan view and a cross-sectional view showing a manufacturing process of a nonvolatile semiconductor memory having an SOI structure according to the embodiment, and shows a state where an opening serving as a seed part region is provided. FIG. 4 is a plan view and a cross-sectional view showing a manufacturing process of a nonvolatile semiconductor memory having an SOI structure according to the embodiment, and shows a state in which an amorphous silicon film is formed. FIG. 7 is a plan view and a cross-sectional view showing a manufacturing process of a nonvolatile semiconductor memory having an SOI structure according to an embodiment, and shows a state in which a silicon single crystal layer is formed by solid-phase annealing. It is the top view and sectional view which show the manufacturing process of the non-volatile semiconductor memory of SOI structure concerning one Embodiment, and has shown the state in which the floating gate was formed. It is the top view and sectional view which show the manufacturing process of the non-volatile semiconductor memory of SOI structure concerning one Embodiment, and has shown the state in which the insulating film between electrodes was formed. FIG. 4 is a plan view and a cross-sectional view showing a manufacturing process of a nonvolatile semiconductor memory having an SOI structure according to an embodiment, showing a state in which a control gate is formed. It is the top view and sectional view which show the manufacturing process of the non-volatile semiconductor memory of SOI structure concerning one Embodiment, and has shown the state in which the interlayer insulation film was formed.

Explanation of symbols

10 ... p-type silicon crystal substrate 11 ... silicon oxide film (buried insulating film)
12 ... Seed part (opening)
DESCRIPTION OF SYMBOLS 13 ... Amorphous silicon film 14 ... Epitaxial silicon layer 14a ... N-type impurity diffusion layer 21 ... Gate oxide film (tunnel insulating film)
22 ... Phosphorus-doped polycrystalline silicon layer 23 ... Element isolation trench 24 ... Silicon oxide film (element isolation insulating film)
25 ... Alumina film 26 ... Slit portion 27 ... Phosphorus doped silicon layer 28 ... Interlayer insulating film 29 ... Bit line contact

Claims (5)

A silicon substrate;
Insulation formed on the silicon substrate, having an opening in a part, an upper portion of the opening formed in a forward taper structure with the upper surface widened, and a lower portion formed in a reverse taper structure with the lower surface widened. A membrane,
A single crystal silicon layer formed on the insulating film and in the opening;
A semiconductor element formed in the single crystal silicon layer;
A semiconductor device comprising:   The semiconductor element is a non-volatile semiconductor memory having a non-volatile memory cell having a two-layer gate structure and a select gate transistor, wherein a select gate transistor is formed on the silicon layer of the opening, and on the silicon layer on the insulating film The semiconductor device according to claim 1, wherein a nonvolatile memory cell is formed. Forming an insulating film on the silicon substrate;
Etching a part of the insulating film under a condition that does not damage the surface of the substrate to form an opening to be a seed region;
Performing a heat treatment using a gas containing hydrogen or fluorine, rounding the corners of the insulating film surface of the opening, and removing a tailing portion of the insulating film remaining in the opening;
Forming an amorphous silicon film on the insulating film and in the opening after the heat treatment;
Annealing the amorphous silicon film and subjecting the amorphous silicon film to a single crystal by solid phase growth using the opening as a seed; and
Forming a semiconductor element on the silicon single crystal layer formed by the solid phase growth;
A method for manufacturing a semiconductor device, comprising:   4. The method of manufacturing a semiconductor device according to claim 3, wherein isotropic etching is performed as the etching for forming the opening to form a forward tapered opening having an upper side widened.   The semiconductor element is a non-volatile semiconductor memory having a non-volatile memory cell having a two-layer gate structure and a select gate transistor, the select gate transistor is formed in the silicon layer of the opening, and the non-volatile semiconductor layer is formed on the silicon layer on the insulating film 5. The method of manufacturing a semiconductor device according to claim 4, wherein a memory cell is formed.

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