JP3256375B2 - Method for manufacturing nonvolatile memory cell - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile memory cell and a method for manufacturing the same. In particular, the present invention relates to an electrically rewritable nonvolatile memory cell suitable for a flash memory and a method for manufacturing the same.

[0002]

2. Description of the Related Art A flash memory in which a program is executed by hot electron injection and erasing is executed by Fowler-Nordheim tunneling has been actively developed. The flash memory is a memory in which data can be written or erased in a batch. FIGS. 30, 31 and 32 show memory cells of a typical flash memory currently being manufactured. This memory cell is a NOR flash memory or NA
It is used for an ND type flash memory, and its structure is EPROM (electrically writable ROM).
Is the same as the structure of the memory cell. Hereinafter, the memory cells of the NOR flash memory will be described.

[0005] A nonvolatile memory cell of a conventional flash memory will be described with reference to FIGS. FIG. 30 is a plan view of a conventional memory cell 50,
FIG. 31 is a sectional view taken along section line X31-X31 in FIG. 30. FIG. 32 is a section view taken along section line X32-X32 in FIG.
It is sectional drawing seen from. Although the flash memory has a large number of memory cells 50, one memory cell MC is shown in these drawings for simplicity. The illustrated control gate 56 functions as a control gate for a plurality of memory cells. On the other hand, the floating gate 54 is separated for each memory cell 50 and is in an electrically floating state.

[0004] The surface of the silicon substrate 51 is divided into a plurality of active regions and element isolation regions for isolating the active regions from each other. As shown in FIG. 32, a field oxide film (LO
A COS film 52 is formed. On the other hand, in the active region 51a of the silicon substrate 51, as shown in FIG.
A source region 60 and a drain region 61 are provided. On the active region 51a of the silicon substrate 1, SiO ₂
A tunnel oxide film (first insulating film) 53, a floating gate 54, an ONO insulating film (second insulating film) 55, and a control gate 56 are stacked in this order. Control gate 5
6 includes an N ⁺ polycrystalline silicon film 57 as the lower layer has a polycide structure comprising a WSi _x film 58 and the upper layer.

In a NOR flash memory,
A bit line (not shown), which is a common wiring of the plurality of memory cells 50, is connected to the drain region 61 of the memory cell 50. The source region 60 itself extends in parallel with the direction in which the control gate 56 extends as a diffusion layer wiring, and serves as a common wiring (shared source region) between the plurality of memory cells 50.

In this prior art, the polycrystalline silicon film serving as the floating gate 54 is first processed into a shape (shown by a broken line) extending in the left-right direction in FIG. 30 to become a polycrystalline silicon film 64b. . The polycrystalline silicon film 64b is formed to completely cover the active region of the silicon substrate 51 and also cover a part of the field oxide film 52. Thereafter, the polycrystalline silicon film 64b is reworked when the control gate 56 is formed by patterning the polycide film, and becomes the floating gate 54. As a result, the floating gate 54
Are formed only in the overlapping portion between the polycrystalline silicon film 64b and the control gate 56 shown in FIG. Thus, the position and shape of the floating gate 54 are as shown in FIG.
Self-aligned to control gate 56.

The tunnel oxide film 53 has a thickness t1 of 8 to 1.
It is a thermal oxide film of about 5 nm. The floating gate 54 is usually formed of polycrystalline silicon in which phosphorus is diffused by about 1 × 10 ²⁰ / cm ³ . Usually, the thickness t2 is 100 nm.
About 300 nm. The ONO insulating film 55 is an oxide film (thickness: 5 to 1) formed by thermally oxidizing the floating gate 54.
0 nm) on the surface by CVD (chemical vapor deposition).
An iN film is deposited (about 8 to 15 nm thick), and an oxide film (about 5 to 10 nm thick) is formed by thermal oxidation or CVD. The ONO insulating film 55 is an extremely thin film having a thickness t3 of about 20 nm at most in terms of an oxide film. ONO
A thermal oxide film may be used instead of the insulating film 55.

[0008]

In the prior art described above, the floating gate 54 is etched following the etching of the control gate 56. More particularly, WSi _x film 58 first configure the control gate 56 and the N ⁺
After etching the polycrystalline silicon film 57 and thereby obtaining the control gate 56 shown in FIG.
The insulating film 55 is etched. Thereafter, the floating gate 54 must be formed by further etching the polycrystalline silicon film 64b.

As shown in FIG. 32, floating gate 54
A step portion 55a of the ONO insulating film 55 is formed on the side surface of. This step 55a is to be completely removed during the etching process of the ONO insulating film 55. In order to completely remove the step portion 55a from the upper portion to the lower portion, it takes time to completely etch the insulating film having at least the height of the step portion 55a (equal to the thickness of the floating gate 54). It is necessary to perform an etching step of the film 55.

If the etching of the step portion 55a is insufficient, the following problem occurs. This problem will be described with reference to FIGS. FIG. 33 is a cross-sectional view taken along section line X33-X33 in FIG. If the etching of the step portion 55a is insufficient, the unetched portion of the ONO insulating film 55 forms the fence 70 as shown in FIG. Using the fence 70 as a mask, a fence 71, which is an unetched portion of the polycrystalline silicon constituting the floating gate, is generated.

The fence 71 made of polycrystalline silicon is
The floating gates 54 of the plurality of memory cells 50 are electrically short-circuited, and the charge stored in the floating gates 54 is released. Therefore, in the flash memory cell 50,
The occurrence of the fence 71 must be prevented.

ONO insulating film 5 having a thickness t3 of about 20 nm
In order to remove the gate oxide film 5, the amount of etching close to the thickness t 2 of the floating gate 54 is performed. As a result, the field oxide film 5 not covered by the floating gate 54 and the control gate 56 is formed.
2 is etched, and the field oxide film 52 is
The recess 52a shown in FIG. Since the thickness of the end of the field oxide film 52 gradually decreases, when the recess 52a is formed at the end of the field oxide film 52, a part of the silicon substrate 51 located in the element isolation region is exposed. There is a possibility that. After the etching process of the ONO insulating film 55, a polycrystalline silicon film etching process for forming the floating gate 54 is performed. If a part of the silicon substrate 51 is exposed, the exposed part is also etched by the etching process of the polycrystalline silicon film.

In order to solve such a problem, the floating gate 54 (polycrystalline silicon film 64) is formed so that a thin portion on the active region side of the field oxide film 52 is not exposed.
It is necessary that b) and the field oxide film 52 overlap with a sufficiently wide width. Increasing the amount of overlap corresponds to generally increasing the width (length measured along the direction in which control gate 56 extends) of polycrystalline silicon film 64b in FIG.

One end of the field oxide film 52 in the left-right direction in FIG. 32 has a shape having a flat slope at the interface with the silicon substrate 51 as shown in FIG. Is 45 degrees, and the thickness t2 of the floating gate 54 is 150 degrees.
nm, the floating gate 54 (polycrystalline silicon film 64
b) overlap amount L1 between field oxide film 52
Needs to be at least 150 nm. As a result, the width of the memory cell 50, which is the length in the left-right direction in FIG. 32, of the memory cell 50 is increased by at least 300 nm as compared with the case where such an overlap amount L1 is not necessary.

Since the floating gate 54 exists only in the memory cell array 50 with some exceptions, the memory cell array has at least the floating gate 54 and the control gate 56 as compared with the peripheral circuit of the memory cell array. Get higher. Therefore, the metal wiring connecting the memory cell array and the periphery is formed over the above-mentioned height difference generated at the boundary between the memory cell array and the periphery. As a result, in a photo process such as exposure of a photomask, an extra focus margin by the height difference is required. In order to make this focus margin as small as possible, it is necessary to make the thicknesses of the floating gate 54 and the control gate 56 as small as possible.

If the thickness of the floating gate 54 and the thickness of the control gate 56 are not small, for example, when exposing the silicon substrate 51 using a photomask for forming the metal wiring, the memory cell is focused. Then, the peripheral portion is out of focus. Therefore, the line width of the metal wiring increases or varies, and the line width of the metal wiring cannot be formed as designed, resulting in defective products.

In order to solve the above problems, the polycrystalline silicon film forming the floating gate 54 may be formed thin. However, on the tunnel oxide film 53, a film thickness of 40
It is very difficult to grow a thin and uniform polycrystalline silicon film having a thickness of about 50 nm. When a polycrystalline silicon film having such a small film thickness is formed, a locally thin portion is likely to be generated, and microscopically, the unevenness is large. Therefore, it is also very difficult to diffuse impurities into a polycrystalline silicon film having irregularities when viewed microscopically. This is because, when the ion implantation technique is used, the implanted ions locally pass through the polycrystalline silicon film and reach the tunnel oxide film 53 thereunder, causing damage to the tunnel oxide film 53, This is because the reliability of the electrical insulation performance is deteriorated. POC on the polycrystalline silicon film
Also in the case of performing diffusion by l ₃ , the phosphorus concentration locally increases in the polycrystalline silicon film, and the reliability of the tunnel oxide film 53 is deteriorated.

As a method for forming a silicon film constituting the floating gate 54, a method using an amorphous silicon film in addition to the polycrystalline silicon film is known. JP-A-1-13
No. 771 describes a method of depositing an amorphous silicon film, then proceeding crystallization from a seed region by heat treatment, and forming a floating gate with a single crystal silicon film.
However, this prior art does not describe the thickness of the floating gate, the presence or absence of doping, and the like.

Japanese Patent Application Laid-Open No. 1-129465 discloses a method in which a floating gate has a two-layer structure of a polycrystalline silicon film and an amorphous silicon film. In this prior art, the thickness of the amorphous silicon film is several tens nm.
And the polycrystalline silicon film has a thickness greater than that of the amorphous silicon film. After the formation of the two-layer structure, phosphorus is thermally diffused.

Japanese Patent Application Laid-Open No. 2-31467 discloses a method in which a floating gate is formed of a non-doped polycrystalline silicon film. However, in this prior art, since the thickness of the polycrystalline silicon film is as large as 250 nm, the voltage drop at the floating gate is large,
The voltage required for erasure increases. Even if the polycrystalline silicon film is oxidized and grown as described in this prior art, the following problems occur.

In the polycrystalline silicon film, an average of 10
^Since a grain boundary level or a crystal defect level of ¹⁷ to 10 ¹⁸ / cm ³ exists, even when a weak electric field of about 3 MV / cm is applied to the floating gate surface, for example, 6 μm is applied to the floating gate surface.
A void layer having a thickness of 0 nm or more occurs, and a voltage drop of several volts or more occurs. An extra voltage by the voltage drop must be applied to the control gate. Therefore, the use of such a thick non-doped polycrystalline silicon film for a floating gate of a flash memory, an EPPROM, or the like is new in that the configuration of a power supply section of a peripheral circuit is increased and power consumption is increased. Problems. Further, if the floating gate is formed of a non-doped single-crystal silicon film, the entire floating gate is depleted, resulting in a potential drop of about 25 V in the above example.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a nonvolatile memory cell which has improved reliability, is suitable for miniaturization, and is easy to manufacture. It is to provide a manufacturing method.

[0023]

A nonvolatile memory cell according to the present invention comprises a semiconductor substrate, a source region and a drain region formed in the semiconductor substrate, and a first insulating film formed on the semiconductor substrate. A floating gate formed on the first insulating film; and a second floating gate formed on the floating gate.
A nonvolatile memory cell including an insulating film and a control gate formed on the second insulating film, wherein the floating gate is formed from a polycrystalline silicon film crystallized from an amorphous silicon film. In addition, the dielectric
Impurities in the polycrystalline silicon thin film
A non - doped polycrystalline silicon thin film having a concentration of 1 × 10 ¹⁹ / cm ³ or less , thereby achieving the above object.

[0024]

[0025]

[0026]

Preferably, the thickness of the floating gate is 33
nm or less.

[0028] More preferably, the thickness of said floating gate is in the range from 3 nm to 15 nm.

In one embodiment, the second insulating film is an oxide film formed on a surface of the polycrystalline silicon film.

[0030] In one embodiment, the second insulating film includes a nitride film.

According to the method of manufacturing a nonvolatile memory cell of the present invention, a step of forming a first insulating film on a semiconductor substrate; a step of forming a floating gate on the first insulating film; 2. A method for manufacturing a nonvolatile memory cell, comprising: forming an insulating film; and forming a control gate on the second insulating film, wherein the step of forming the floating gate comprises the step of forming the first insulating film Depositing an amorphous silicon film thereon, and recrystallizing the amorphous silicon film by annealing,
Impurity concentration to be considered as a dielectric during memory operation
Includes a step of forming a non - doped polycrystalline silicon film of 1 × 10 ¹⁹ / cm ³ or less and a step of forming the floating gate from the polycrystalline silicon film , thereby achieving the above object. Is done.

In one embodiment, the step of forming the floating gate from the polycrystalline silicon film includes the steps of: depositing an oxidation resistant film on the polycrystalline silicon film; and patterning the oxidation resistant film into a predetermined shape. And selectively oxidizing a part of the polycrystalline silicon film using the patterned oxidation-resistant film as a mask.

Preferably, the annealing includes a first annealing step performed at a first predetermined temperature and a second annealing step performed at a second predetermined temperature higher than the first predetermined temperature. I have.

[0034]

The thickness of the floating gate of the nonvolatile memory cell device according to the present invention is thinner than before. Such a thin floating gate can be formed by polycrystallizing an amorphous silicon thin film by solid phase growth. The silicon thin film formed according to the present invention has high film thickness uniformity even in a microscopic area. Therefore, according to the present invention, an extremely thin polycrystalline silicon film (specifically, a polycrystalline silicon film having a thickness of 55 nm or less) can be used for the floating gate.

By making the floating gate extremely thin, the etching amount of the element isolation insulating film at the time of processing the second insulating film can be reduced.
Thereby, the amount of overlap between the floating gate and the field oxide film in the semiconductor substrate can be reduced,
The miniaturization of the nonvolatile memory is facilitated. Further, since the thickness of the floating gate is reduced, a focus margin at the time of exposure is increased, manufacturing is facilitated, and a manufacturing yield is improved.

Further, the polycrystalline silicon film is close to a single crystal grain in the thickness direction, and forms an oxide film having a good withstand voltage by thermal oxidation. Therefore, the first insulating film between the floating gate and the control gate can be formed by thermally oxidizing the floating gate. Thereby, an ONO film (SiO ₂ / SiN / SiO ₂ ) used as a conventional insulating film
This makes it possible to form a thin film insulating film, which is difficult in the case described above. The reason why it is difficult to reduce the thickness of the ONO film is that the film quality of SiN is inferior to that of SiO ₂ , and the thickness can be reduced to at most 13 nm.

Further, if the floating gate is made of an ultra-thin film, the voltage loss is small even if the ultra-thin film is a non-doped film, and the step of diffusing impurities into the thin polycrystalline silicon film can be omitted, which facilitates manufacture. .

Further, by forming the pattern of the floating gate by the selective oxidation method, it is not necessary to etch the first insulating film on the step of the floating gate, and the amount of overlap between the field oxide film and the floating gate can be reduced. Can be significantly reduced.

[0039]

The present invention will be described below with reference to examples.

(Embodiment 1) A nonvolatile memory cell according to the present invention will be described below with reference to FIGS. 1 to 3, taking a flash memory as an example.

FIG. 1 is a plan view of the present non-volatile memory cell MC, FIG. 2 is a sectional view taken along the section line X2-X2 of FIG. 1, and FIG. 3 is a section line X3 of FIG. It is sectional drawing seen from -X3.

Although the flash memory has a large number of memory cells, one memory cell MC is shown in these drawings for simplicity. The illustrated control gate 6 functions as a control gate for a plurality of memory cells. On the other hand, the floating gate 4 is separated for each memory cell and is in an electrically floating state.

The surface of the silicon substrate 1 is divided into a plurality of active regions and element isolation regions for isolating the active regions from each other. In the element isolation region of the silicon substrate 1,
As shown in FIG. 3, the field oxide film (LOCOS)
A film 2 is formed. In this embodiment, the recess type LOCOS film 2 is used for the purpose of reducing the surface step. On the other hand, a source region 10 and a drain region 11 are provided in the active region 1a of the silicon substrate 1, as shown in FIG. Active region 1a of silicon substrate 1
On top of this, a tunnel oxide film (first insulating film) 3 made of SiO ₂ , a floating gate 4, an ONO insulating film (second insulating film)
5 and the control gate 6 are stacked in this order.
The control gate 6 comprises an N ⁺ polysilicon film 7 as the lower layer has a polycide structure comprising a WSi _x film 8 as the upper layer.

In a NOR type flash memory,
A bit line (not shown), which is a common wiring of the plurality of memory cells MC, is connected to the drain region 11 of the memory cell MC. The source region 10 itself extends as a diffusion layer wiring in parallel with the direction in which the control gate 6 extends, and serves as a common wiring (shared source region) between the plurality of memory cells MC.

One of the important features of the memory cell of this embodiment is that the floating gate 4 is formed of an extremely thin polycrystalline silicon film. From this, various effects can be obtained as described in detail later. In this embodiment, the polycrystalline silicon film serving as the floating gate 4 is first processed into a shape (shown by a broken line) extending in the left-right direction in FIG. 1 to become the polycrystalline silicon film 14b. The width W of the polycrystalline silicon film 14b is set such that the polycrystalline silicon film 14b completely covers the active region 1a of the silicon substrate 1 and partially covers the field oxide film 2. After that, a part of the polycrystalline silicon film 14b is etched when the control gate 6 is formed by patterning the polycide film, and becomes the floating gate 4. As a result, the floating gate 4
It is formed only in the overlapping portion between the polycrystalline silicon film 14a and the control gate 6 shown in FIG. Thus, the position and the shape of the floating gate 4 are controlled as shown in FIG.
Self-aligned.

Next, a method for manufacturing the present memory cell MC will be described below with reference to FIGS. FIG. 4 (a)
13A to 13A are cross-sectional views taken along a position corresponding to the section line X2-X2 in FIG. 1, and FIGS.
FIG. 2B is a cross-sectional view of a portion corresponding to a section line X3-X3 in FIG. FIGS. 10C and 11C are cross-sectional views of a peripheral circuit portion of the memory cell MC.
FIG. 2C is a cross-sectional view taken along the line Xc-Xc in FIG. 1. FIG. 14 is a process chart showing the manufacturing process of this example.

First, as shown in FIGS. 4A and 4B, a field oxide film (LOCOS film) 2 is selectively formed in a device isolation region on the surface of a P-type silicon substrate 1 (step). a1). Next, as shown in FIGS. 5A and 5B, after forming a tunnel oxide film 3 on the silicon substrate 1 (step a2), an amorphous silicon film 12 is deposited on the tunnel oxide film 3. (Step a3). Tunnel oxide film 3
Is formed, for example, by thermally oxidizing the exposed surface of the silicon substrate 1. The thickness t11 of the tunnel oxide film 3 is preferably about 8 to 12 nm, and is 10 nm in this embodiment.

The thickness t12 of the amorphous silicon film 12 is 10
The thickness is preferably about 40 nm, and in this example, it was 32 nm.
The amorphous silicon film 12 needs to have a uniform thickness in a microscopic area similar to the film thickness t12. Therefore, in the present embodiment, this amorphous silicon film 12 was formed by the method described below. Specifically, low pressure CVD using silane (SiH ₄ ) as a source gas
The non-doped amorphous silicon film 12 is grown at a temperature of about 550 ° C. by using the method. Alternatively, using a low pressure CVD method using disilane (Si ₂ H ₆ ) as a source gas,
The amorphous silicon film 12 may be formed at a temperature of about 500 ° C. Amorphous silicon film 1 thus deposited
No. 2 has been confirmed to satisfy the above conditions.

Next, as shown in FIGS. 6A and 6B, a film thickness t13 of 15 n
An oxide film 13 of about m was formed by the CVD method (step a4).
Thereafter, arsenic ions are implanted into the amorphous silicon film 12 (step a5). The implantation energy is set so that arsenic ions do not reach the tunnel oxide film 3, and the implantation amount is 3 × 10 ¹⁹ to 3 × 10 ¹⁹ to 3 when the average concentration of the floating gate 4 to be described later is completed.
Set so as to be about × 10 ²⁰ / cm ³ . In this embodiment, the implantation energy is 20 keV and the implantation amount is 3 × 1.
It was set at 0 ¹⁴ / cm ² . This ion implantation is performed in order to reduce a depletion layer generated in the floating gate 4 when a voltage is applied to the control gate 6 and to reduce a voltage drop in the floating gate 4. The implanted impurities may be phosphorus or boron.

Next, the oxide film 13 is etched with an HF aqueous solution (step a6). The oxide film 13 has a function of keeping the ion implantation depth within a desired range during the above-described ion implantation, and is unnecessary after the ion implantation.

Next, the amorphous silicon film 12 is crystallized by heat treatment (annealing) to obtain a polycrystalline silicon film 14a as shown in FIGS. 7 (a) and 7 (b). More specifically, first, at 600 ° C. for 24 hours in a nitrogen atmosphere,
Heat treatment is performed to grow the amorphous silicon film 12 in a solid phase (step a7). Next, a second heat treatment is performed at 900 ° C.
Heat treatment is performed (step a8). The temperature of the first heat treatment step is 5
It may be about 50 ° C to 650 ° C. The second heat treatment step may be performed in a nitrogen atmosphere or in a nitrogen atmosphere to which a small amount of oxygen is added, and the temperature may be 800 ° C to 1000 ° C.
By these heat treatments, a polycrystalline silicon film 14a is formed. In the case where the second heat treatment step is performed in an oxygen atmosphere, an oxide film having a thickness of about 5 to 20 nm is formed on the surface of the polycrystalline silicon film 14a. Is removed by etching.

It is not necessary to remove oxide film 13 before the heat treatment for polycrystallization, and oxide film 13 may be removed after the heat treatment. Performing ion implantation into the amorphous silicon film 12 to dope impurities into the floating gate 4 is merely an example.
After the heat treatment for crystallization of PSG 2, PSG (Phospho
(silicate-Glass: phosphor glass), BSG
(Borosilicate-Glass: boron glass) or the like may be deposited on the polycrystalline silicon film 14a, and heat treatment may be performed to diffuse the phosphorus or boron such as PSG or BSG into the polycrystalline silicon film 14a.

Next, as shown in FIGS. 8A and 8B, the polycrystalline silicon film 14a is patterned to obtain a polycrystalline silicon film 14b (step a9). This patterning may be performed by a known lithography technique and etching technique. The polycrystalline silicon film 14b is finally formed with a floating gate 4 having a thickness t14 (for example, 30 nm).
Becomes

The surface of the polycrystalline silicon film 14b is thermally oxidized, whereby a first oxide film of about 5 nm is grown on the surface of the polycrystalline silicon film 14b, and then a silicon nitride film (thickness: 10 nm) by LPCVD, and a second oxide film (commonly referred to as HTO) is formed by LPC.
5 nm is deposited by the VD method (step a10). Thus, as shown in FIGS. 9A and 9B, a film thickness t15 (for example, 20 nm) is formed on the polycrystalline silicon film 14b.
ONO insulating film (having a three-layer structure) 5 is formed.
In this embodiment, the silicon nitride film and the second oxide film of the ONO insulating film 5 are formed so as to cover the entire surface of the silicon substrate 1 by the CVD method, but the first oxide film is polycrystalline by the thermal oxidation method. It is selectively formed on the silicon film 14b. However, for simplicity, the ONO insulating film 5 is shown in the drawing.
Is described so as to cover the entire surface of the silicon substrate 1.

The first oxide film forming the ONO insulating film 5 is
It may be formed from HTO. Polycrystalline silicon film 14b
In the case where the first oxide film is formed by oxidation of the oxide, it is preferable to use a dry oxidation method in order to form an extremely thin first oxide film with good controllability. The silicon nitride film constituting the ONO insulating film 5 can be formed at a temperature of about 600 ° C. to 800 ° C. using SiCl ₂ H ₂ and NH ₃ as source gases.
The second oxide film constituting the ONO insulating film 5 is made of SiH ₄ and N ₂
It can be generated at 700 ° C to 900 ° C using O as a source gas. The source gas may be SiCl ₂ H ₂ and N ₂ O.

Incidentally, instead of the ONO insulating film 5, an insulating film composed of a single thermal oxide film may be used. A case in which an insulating film composed of a single thermal oxide film is used instead of the ONO insulating film 5 will be described in detail in a fourth embodiment.

In this embodiment, the transistors to be formed in the peripheral circuit section of the memory cell array are also formed during the manufacturing process of the nonvolatile memory cell. Immediately after the ONO insulating film 5 is formed, in order to form the gate oxide film 32b (FIG. 11C) of the transistor in the peripheral circuit portion,
As shown in FIGS. 10A and 10B, the memory cell M
A resist pattern 15 covering C is formed (step a1).
1). As shown in FIG. 10C, the resist pattern 15 has an opening 1 on the active region 1a of the peripheral circuit portion.
5a. Next, the opening 15 of the ONO insulating film 5 is formed.
a portion selectively exposed by a is removed by etching,
Exposing the active region 1a of the peripheral circuit section (step a1)
2). After removing the resist pattern 15, the surface of the active region 1a in the peripheral circuit portion is thermally oxidized to form a gate oxide film 32b.
(FIG. 11C) is formed (step a13). Due to this thermal oxidation, the thickness of the ONO insulating film 5 is slightly increased. The final equivalent oxide film thickness of the ONO insulating film 5 is 16 nm.

[0058] Next, FIG. 11 (a), the as shown in FIG. 3 (b) and (c), N ⁺ polycrystalline silicon film 7 and WSi _x
And a film 8 are sequentially formed to obtain a polycide structure (step a1).
4). Thereafter, as shown in FIG. 12 (a) and FIG. (B), to obtain a WSi _x film 8 and N ⁺ control gate 6 polycrystalline silicon film 7 are successively patterned (step a15). Subsequently, the ONO insulating film 5 is etched. As described above, the O on the side surface of the polycrystalline silicon film 14b is
In order to completely remove the NO insulating film 5, the ONO insulating film having the total thickness of the thickness of the polycrystalline silicon film 14b (the thickness of the floating gate 4) and the thickness of the ONO insulating film 5 is etched. Etching is performed for a sufficient time. The etching gas for etching the ONO insulating film 5 is a material (SiO ₂ ) used for the field oxide film 2.
Is also etched. Therefore, the polycrystalline silicon film 14
The upper part of the field oxide film 2 in the region not covered by b is etched during the etching process of the ONO insulating film 5. In particular, in the peripheral circuit section, FIG.
As shown in FIG. 5, since the polycrystalline silicon film 14b does not exist, the etching of the polycide and the O
After the etching of the NO insulating film 5 is completed, the field oxide film 2 is exposed, and thereafter, the etching of the field oxide film 2 proceeds. However, according to the present invention,
Since the polycrystalline silicon film 14a is extremely thin, the etching of the field oxide film is significantly reduced. Subsequent to the etching of the ONO insulating film 5, the polycrystalline silicon film 14b
Is etched. This polycrystalline silicon film 14b
, The formation of the floating gate 4 is completed.
When the formation of the floating gate 4 is completed, a portion of the active region 1a where the source region 10 and the drain region 11 are to be formed is substantially exposed. FIG. 12C is a cross-sectional view of a cutting position corresponding to the cutting plane line Xc-Xc in FIG. As shown in FIG. 12C, a recess 17 having a depth d1 is formed in the field oxide film 2 mainly by the etching process of the ONO insulating film 5. The depth d1 of the recess 17 corresponds to the sum of the thickness t14 of the floating gate 4 and the amount of over-etching of the ONO insulating film 5. According to the present embodiment, the thickness t14 of the floating gate 4 is about 30 nm. Because there is only
The depth d1 of the recess 17 is suppressed to about 50 nm at most. For this reason, the overlap amount L1 between the field oxide film 2 and the floating gate 4 shown in FIG. Therefore, assuming that the alignment margin of the floating gate 4 with respect to the field oxide film 2 is 150 nm, the overlap margin in designing the pattern of the floating gate 4 is at most 200 nm. Therefore, it is possible to provide a nonvolatile memory cell having a reduced size.

Next, using a known method, FIG.
Then, as shown in FIG. 2B, a source region 10 and a drain region 11 are formed (step a16).

The flash memory having the memory cells MC formed through the above manufacturing steps has a control gate 6 / ONO insulating film (thickness t15 is about 21 nm) 5 / floating gate (thickness t14 is about 30 nm) 4 / It has a stacked structure of a tunnel oxide film (thickness t11 is 10 nm) 3.

According to this embodiment, after depositing an ultrathin amorphous silicon film 12 having only irregularities on the order of nanometers and excellent in film thickness uniformity, the amorphous silicon film 12 is polycrystallized. I do. Thereby, the ultra-thin polycrystalline silicon film 1
4 can be formed stably. This allows
The thickness t14 of the floating gate 4 can be reduced to 40 nm or less. Therefore, the degree of etching of the field oxide film 2 generated during the etching process of the ONO insulating film 5 is 50 nm or less, and the overlap margin between the floating gate 4 and the field oxide film 2 is 300 n
m to about 200 nm or less.

In the present flash memory, since the floating gate 4 exists in the memory cell array, the thickness of at least the floating gate 4 and the control gate 6 in the memory cell array is smaller than that in the peripheral circuit portion outside the memory cell array of the flash memory. Above the surface of the silicon substrate 1. The metal wiring connecting the memory cell array section and the peripheral circuit section is formed over the above-mentioned height difference generated at the boundary between the memory cell array and the peripheral circuit section. In this embodiment, since the step between the memory cell array section and the peripheral circuit section due to the floating gate 4 can be reduced by about 100 nm from the level difference of the corresponding step section in the prior art, the focus depth during the exposure in the photolithography process is reduced. Was improved. Thereby, when forming the metal wiring extending between the memory cell array portion and the peripheral circuit portion in the present flash memory, the exposure can be performed in substantially the same focus state in the memory cell array portion and the peripheral circuit portion. So
Metal wiring without disconnection or short circuit can be easily formed. As a result, the reliability of the flash memory of this embodiment is significantly improved.

As described above, the reliability of the memory cell according to the present embodiment is improved, and the nonvolatile memory cell suitable for high integration can be provided by reducing the overlap margin. Moreover, when manufacturing such a memory cell, the height difference of the step between the memory cell portion and the peripheral circuit portion was significantly reduced as compared with the prior art, so that the manufacturing process by the photo process for metal wiring was performed. The process can be greatly simplified.

Embodiment 2 Another nonvolatile memory cell according to the present invention will be described below.

The structure of the memory cell of this embodiment is basically the same as the structure of the memory cell shown in FIGS. The difference between the two is that the memory cell of this embodiment has a thin floating gate (thickness: about 10 nm) 4 formed from a “non-doped polycrystalline silicon film”. In the present specification, the term “non-doped polycrystalline silicon film” indicates a polycrystalline silicon film in which impurity doping has not been actively performed. in this way,
By adopting the “non-doped polycrystalline silicon film” as the floating gate 4, an effect completely different from that of the nonvolatile memory cell of the above-described embodiment is exerted.

Even if the polycrystalline silicon film contains impurities of 1 × 10 ¹⁹ / cm ³ or less, the impurities in the polycrystalline silicon film are not supplied to the carrier supply source (donor or acceptor).
Does not work as well. The reason is that, since the polycrystalline silicon film has a large number of grain boundaries, most of the impurity carriers are trapped in the interface states of the grain boundaries. Therefore, the same effect can be obtained by using a polycrystalline silicon film containing an impurity of 1 × 10 ¹⁹ / cm ³ or less instead of the non-doped polycrystalline silicon film as the floating gate. This effect will be described below.

Since the floating gate 4 is not substantially doped with impurities, a depletion layer spreads over the entire floating gate 4 during operation of the memory cell, and the floating gate 4 can be regarded as a dielectric as a whole. The relative dielectric constant of Si (about 1
2) is three times the relative dielectric constant of the oxide film (SiO ₂ ). Therefore, when the floating gate (thickness: about 10 nm) 4 is regarded as a dielectric, the equivalent oxide film thickness of the floating gate 4 is 3 0.3 nm
About.

Further, since the resistance of the floating gate 4 is high, a potential gradient may occur in the lateral direction of the floating gate 4. More specifically, the potential Vfs of the portion of the floating gate 4 located above the source region (for the drain) and the potential Vfs of the portion located above the drain region (for the drain)
fd.

The programming speed increases as the potential of the floating gate with respect to the drain increases. In the case of a conventional nonvolatile memory cell, the potential Vfc of the floating gate 4 is
The floating gate 4 was strongly affected by the potential of the source region, and had the same potential in the horizontal direction throughout the floating gate 4. In this embodiment, the following relationship is obtained because the floating gate 4 has resistance.

Potential Vfd> potential Vfc> potential V
fs As a result, the programming speed of the memory cell of this embodiment is about twice as fast as that of the conventional memory cell.

Next, the capacitance formed between the control gate 6 and the silicon substrate 1 will be examined. The size of the capacitance formed between the control gate 6 and the silicon substrate 1 is (when other factors are fixed) the oxide-equivalent thickness of the dielectric located between the control gate 6 and the silicon substrate 1. Depends on. The smaller the equivalent oxide thickness of the dielectric, the larger the capacitance. The thickness t15 of the ONO insulating film 5 of this embodiment is 1
Since the thickness is 6 nm, the total thickness of the dielectric located between the control gate 6 and the tunnel oxide film 3 is equivalent to an oxide film thickness,
It becomes about 19 nm. This equivalent oxide film thickness is not much different from the equivalent oxide film thickness of a conventionally used ONO insulating film. Therefore, when comparing the memory cell of this embodiment with the conventional memory cell, there is no great difference in the magnitude of the capacitance formed between the silicon substrate 1 and the control gate 6.

However, when the thickness of the floating gate 4 is increased, the equivalent oxide thickness of the floating gate 4 increases, which may cause a problem that the capacitance increases. Therefore, in the memory cell of the present embodiment in which the floating gate 4 is formed from a non-doped polycrystalline silicon film, it can be said that the thinner the floating gate 4 is, the better from the viewpoint of capacitance. However, if the thickness of the floating gate 4 is thinner than about 3 nm, electric charges cannot be sufficiently accumulated. Therefore, the thickness of the floating gate 4 needs to be at least 3 nm or more.

On the other hand, in order to increase the capacitance formed between the control gate 6 and the silicon substrate 1, the equivalent oxide thickness of the insulating film between the floating gate 4 and the control gate 6 must be reduced. What is necessary is just to reduce. The insulating film between the floating gate 4 and the control gate 6 needs to have a thickness equal to or greater than the minimum limit thickness sufficient to prevent charge transfer. The minimum critical thickness depends on the material and structure of the insulating film. The minimum critical thickness of the SiO ₂ film is, for example, about 6 to 8 nm. On the other hand, the minimum critical film thickness of the ONO insulating film is, for example, about 12 to 18 nm (a film thickness equivalent to an oxide film, a relatively loose limit).
Therefore, it can be seen that it is preferable to use a single-layer SiO ₂ film rather than an ONO insulating film in order to increase the capacity. If the ONO insulating film 5 is replaced with a single-layer SiO ₂
If a film is adopted, it is converted to an oxide film thickness, for example, 12 n
The total thickness of the dielectric film can be reduced by a thickness of m (= 18 nm−6 nm), and the capacitance can be increased accordingly.

In the memory cell of this embodiment, if
By adopting a single-layer SiO ₂ film instead of the ONO insulating film 5, for example, 12 nm
Even if the total thickness of the dielectric film is reduced by the thickness of (= 18 nm−6 nm), the total thickness of the dielectric film is increased by the equivalent oxide thickness of the floating gate 4. Therefore, it is not preferable to use the floating gate 4 having an equivalent oxide thickness of 12 nm from the viewpoint of capacitance. Therefore, when the floating gate 4 is formed from a non-doped polycrystalline silicon film, the thickness of the floating gate 4 is preferably set to 33 nm or less. If you do so, even if it is ON
This is because the required capacitance is maintained even if a single-layer SiO ₂ film is used instead of the O insulating film 5.

More preferably, the thickness of the floating gate 4 is 15
nm or less. If the thickness of the floating gate 4 is 15 nm or less, the ONO insulating film 5 can be used, or a single-layer S
It has been confirmed that even if an iO ₂ film is used, a larger capacity than the conventional example can be obtained.

Hereinafter, a method for manufacturing the memory cell of this embodiment will be described with reference to FIG. FIG. 15 is a process chart for explaining the manufacturing process of the memory cell of the flash memory according to the present embodiment. The cross-sectional views of the memory cells showing the manufacturing process refer to FIGS. 4 to 13 referred to in the first embodiment as necessary.

Steps b1 to b3 shown in FIG. 15 are substantially the same as steps a1 to a3 of the first embodiment. However, in this embodiment, the thickness t12 of the amorphous silicon film 12 was set to 12.5 nm.

For the amorphous silicon film 12,
Arsenic ion implantation or impurity diffusion such as thermal diffusion using PSG or BSG was not performed at all. That is,
Steps a4 to a6 shown in FIG. 6 are omitted.

After the deposition of the amorphous silicon film 12, first and second heat treatments are applied to the amorphous silicon film 12 (step b6,
b7) Thereby, the amorphous silicon film 12 is crystallized, and the polycrystalline silicon film 14 is obtained. Steps b9 to b15 performed after forming the pattern of the floating gate 4 (step b8)
Are steps a10 to a16 described in the first embodiment.
This is the same step.

Through the above-described steps, the thickness t14 of the final floating gate 4 of the memory cell of this embodiment is about 10 nm. Since the thickness t14 of the floating gate 4 is reduced to about 10 nm, the field oxide film 2 formed when the insulating film between the control gate 6 and the floating gate 4 is etched.
It was confirmed that the depth d1 of the recess 17 was 13 nm or less. Therefore, it is sufficient that the overlap margin between the floating gate 4 and the field oxide film is set to 180 nm, and the overlap margin was significantly reduced as compared with the first embodiment. Further, it was also confirmed that the step between the cell array portion and the peripheral portion caused by the floating gate 4 was 30 nm.

As described above, according to the memory cell of the present embodiment, not only the effect similar to that of the memory cell of the first embodiment can be achieved, but also the overlap between the floating gate 4 and the field oxide film. The degree of margin could be further reduced. Further, the above-mentioned height difference of the step at the boundary between the cell array section and the peripheral circuit section could be further reduced.

Since the floating gate 4 has a high resistance,
As mentioned above, the programming speed has been greatly increased, resulting in improved power consumption.

(Embodiment 3) Still another nonvolatile memory cell according to the present invention will be described.

FIGS. 16 and 17 are cross-sectional views for explaining a part of the manufacturing process of the memory cell of this embodiment. For other processing steps of the manufacturing process of the present embodiment, FIGS. 4 to 13 of the first embodiment are appropriately referred to. FIG. 18 is a process chart showing the manufacturing process of this embodiment. FIGS. 16A and 17A are cross-sectional views taken along a cutting position corresponding to the cutting plane line X2-X2 in FIG. 1. FIGS. 16B and 16B are FIGS. 16 (c) and FIG. 17 (c) are cross-sectional views of a portion corresponding to a section line X3-X3 of FIG.
FIG. 3 is a cross-sectional view of a peripheral circuit section of a memory cell MC.

The structure of the flash memory cell obtained by the manufacturing method of this embodiment is almost the same as that of the memory cell MC of the first embodiment. The main difference between the two is that the insulating film (second insulating film) between the floating gate 4 and the control gate 6 in this embodiment is formed not of an ONO insulating film but of a single oxide film. On the point.

Hereinafter, the manufacturing method of this embodiment will be described with reference to FIGS. In the present embodiment, steps c1 to c6 in FIG.
It is almost the same as 1 to a6. In this embodiment, the thickness t12 of the amorphous silicon film 12 is set to 22 nm. After performing arsenic ion implantation in Step c5, Step c6 is performed.
At this time, the oxide film 13 (FIGS. 6A and 6B) is etched. In steps c7 and c8, the amorphous silicon film 12 (FIGS. 6A and 6B) is heated to form a polycrystalline silicon film.

Next, after the polycrystalline silicon film 14b is formed by patterning the polycrystalline silicon film formed on the entire surface of the substrate 1 (step c9), FIG.
As shown in (b) and (c), a 13 nm oxide film 32a is grown by 900 ° C. dry oxidation of hydrochloric acid (HCl / O ₂ ) (step c10). The oxide film 32a is formed not only on the surface of the polycrystalline silicon film 14b but also on the active region 1a of the peripheral circuit portion.
Is also formed. Thereafter, as shown in FIG.
The peripheral circuit portion is covered with a resist pattern 18 (step c1).
1) The oxide film 32a grown on the polycrystalline silicon film 14b shown in FIG. 16B is selectively removed by etching with an HF aqueous solution (step c12). After removing the resist pattern 18 (step c13), cleaning is performed, and an oxide film having a thickness of 7 nm is grown again under the same conditions as the oxidation conditions (step c14). 17 (a), 17 (b) and 1
As shown in FIG. 7C, an oxide film 5a and an oxide film 32b are formed on the polycrystalline silicon film 14b and the active region 1a of the peripheral circuit portion, respectively. The oxide film 32b is obtained by further increasing the thickness of the oxide film 32a by this oxidation step. When the thickness of each oxide film is estimated by measuring the capacitance of the oxide films 5a and 32b, the thickness t13 of the oxide film 5a is calculated.
Is 10 nm, and the thickness t14 of the oxide film 32b is 18 n
m. These values do not always match values measured by physical means such as a TEM (transmission electron microscope). In this manner, an insulating film between the floating gate 4 and the control gate 6, after forming the gate insulating film of the transistor of the peripheral circuit portion, N ⁺ polycrystalline silicon film 7 and WSi _x
The film 8 was deposited (Step c15). Note that the processing steps in the processing step c17 after the formation step of the control gate 6 in the step c16 are the same as the step a16 in the first embodiment.

In the memory cell of this example, it was confirmed by measurement by the present inventor that the thickness t14 of the floating gate 6 was reduced to about 10 nm. As in the second embodiment, the depth d1 of the recess 17 of the field oxide film 2 generated when etching the insulating film 5a is 13 nm.
It was also confirmed that: As a result, the overlap margin between the floating gate 4 and the field oxide film 2 can be set to 163 nm, and similar to the second embodiment,
Significantly reduced compared to the prior art. The step at the boundary between the cell array section and the peripheral circuit section due to the floating gate 4 was confirmed to be 13 nm, which was almost negligible.

When oxide film 5a is formed by thermally oxidizing an ordinary relatively thick polycrystalline silicon film, the withstand voltage of oxide film 5a generally decreases due to the occurrence of so-called asperity. For this reason, it was difficult to reduce the thickness of the oxide film 5a. However, since the polycrystalline silicon thin film 14b of the present invention is formed extremely thin, the degree of surface irregularities is significantly reduced. Since the surface of such a thin polycrystalline silicon film has no projections and depressions that cause electric field concentration, the oxide film 5 grown on the surface does not have any projections and depressions.
The thickness “a” indicates a variation due to the crystal orientation of each crystal grain, but the degree of the variation is negligible as compared with the thickness variation of the prior art. Thus, the thickness uniformity of the insulating film 5a of the present embodiment is high, and the withstand voltage thereof is also good.

Since the insulating film 5a between the control gate 6 and the floating gate 4 is formed of an oxide film having a thickness t13 of 10 nm, the control gate 6 and the floating gate 4 are different from the second embodiment. And the coupling constant, which is the ratio of the capacitance between the control gate 6 and the floating gate 4 to the total capacitance of the floating gate 4, has increased from about 0.5 to 0.6 or more. .

Thus, the voltage applied to the control gate 6 can be reduced. In addition, the first and second
Compared with the ONO insulating film in the example, the thermal oxide film 5a was not inferior to the retention characteristics in terms of retention characteristics, and had no problem. The retention characteristic is a charge retention characteristic. If the retention characteristic is low, the charge moves from the floating gate 4 to the outside.

In the above-described embodiment, the effects described in the first embodiment can be achieved, and the effects unique to the above-described embodiment and further improved from the above-described embodiments can be achieved. can do.

(Example 4) Another method for manufacturing a nonvolatile memory cell according to the present invention will be described. FIG. 19 is a process chart for explaining the manufacturing method of this example. In describing the manufacturing process of this embodiment, FIGS. This embodiment is similar to the first embodiment, and corresponding parts are denoted by the same reference numerals.

Steps d1 to d3 in FIG. 19 are almost the same processing steps as steps a1 to a3 in the first embodiment. In this embodiment, the thickness t12 of the amorphous silicon film 12 is set to 19 nm in steps d1 to d3. In this embodiment, the arsenic ion implantation and PS in the first embodiment are performed.
No impurity diffusion such as thermal diffusion from G and BSG is performed. In this embodiment, the insulating film 5b between the floating gate 4 and the control gate 6 is formed by a thermal oxidation process.

In steps d6 and d7, heat treatment is applied to the amorphous silicon film 12 to convert it to a polycrystalline silicon film 14,
After the pattern of the floating gate 4 is formed in step d8, steps c10 to c1 of FIG. 18 in the third embodiment are performed.
The memory cell MC is formed through the same steps as in step 7.

First, in step d9, a 10 nm oxide film is grown by dry oxidation of hydrochloric acid (Hcl / O ₂ ) at 900 ° C., and in steps d10 to d12, the oxide film in the cell array portion is exposed to an aqueous HF solution. After the etching, in step d13, a 10-nm-thick oxide film was grown under the same oxidation conditions as in the above-described oxidation treatment. The thickness t of the floating gate 4 at this time
14 is about 10 nm. Step d17 after the control gate 6 forming step is the same processing step as step a16 of the first embodiment.

In this embodiment, since the floating gate 4 is not diffused with impurities, the entire floating gate 4 becomes a depletion layer, and the entire floating gate 4 is regarded as a dielectric. When the floating gate 4 is viewed as a dielectric, the equivalent oxide film thickness of the floating gate 4 is about 3.3 nm, and the thickness of the insulating film 5a between the floating gate 4 and the control gate 6 is equivalent to the oxide film. The thickness is about 14 nm, which is sufficiently smaller than the thickness of a conventionally used ONO insulating film.

The thickness t14 of the floating gate 4 is finally 10
It has been confirmed by the measurement of the present inventor that the thickness is reduced to about nm. The depth d1 of the recess 17 of the field oxide film 2 generated at the time of etching the insulating film 5a is 13 nm or less. Therefore, the overlap margin between the floating gate 4 and the field oxide film 2 is 163 nm.
The result was significantly reduced as compared with the first embodiment. Further, it was confirmed that the step due to the floating gate 4 at the boundary between the cell array portion and the peripheral circuit portion was 13 nm, which was almost negligible.

For example, the thinning limit of the ONO insulating film 5 in the first embodiment is considered to be 15 nm in terms of oxide film thickness, and the thinning limit of the tunnel oxide film 3 on the floating gate 4 is considered to be 8 nm. To be effectively used, the equivalent increase in the thickness of the upper oxide film due to the floating gate 4 is 7n.
m or less. Under the worst-case condition that the floating gate 4 acts as a dielectric, 7 nm in terms of an oxide film corresponds to a thickness of the floating gate 4 of 21 nm. In this embodiment, the final thickness of the floating gate 4 is 10 nm.
Since it has been confirmed by the present inventor, it falls within the above-mentioned restrictions. Therefore, according to this embodiment, a nonvolatile memory can be manufactured.

In this embodiment as well, the first
The same effects as the effects described in the embodiments can be achieved, and the effects unique to the present embodiment as described above and further improved from the above embodiments can be achieved.

(Embodiment 5) Still another nonvolatile memory cell according to the present invention will be described. The structure of the memory cell of this embodiment is basically the same as the structure of the memory cell shown in FIGS. This embodiment is characterized by its manufacturing method.

Hereinafter, referring to FIGS. 20 to 24,
A method for manufacturing the memory cell according to the present embodiment will be described. FIG.
FIG. 24 is a cross-sectional view for explaining a part of the manufacturing process of the memory cell of the flash memory according to the present embodiment. 4 to 13 for other steps of the manufacturing process of this embodiment. FIG. 25 is a process chart showing the manufacturing process of this example. FIGS. 20 (a) to 23 (a) are cross-sectional views taken along a cutting position corresponding to the cutting plane line X2-X2 in FIG. 1, and FIGS. 20 (b) to 23 (b) correspond to FIGS. 22 (c) and FIG. 23 (c) are cross-sectional views of a peripheral circuit portion of the memory cell MC. FIG. 24 is an enlarged sectional view near the memory cell MC. This embodiment is similar to the first embodiment, and corresponding parts are denoted by the same reference numerals.

First, in steps e1 to e8, processing steps substantially the same as steps a1 to a8 of the first embodiment are performed. In this embodiment, the amorphous silicon film 1 is formed in the same manner as in the first embodiment.
The thickness t12 of No. 2 was 32 nm. After the arsenic ion implantation, the polycrystalline silicon film 14 formed by performing the two-step heat treatment is subjected to a CVD method to form a film t20 on the polycrystalline silicon film 14, as shown in FIGS. Is 120 nm
Is formed (step e9).

Next, a resist (not shown) having a pattern corresponding to the pattern of the polycrystalline silicon film 14b in the memory cell portion and a pattern covering at least the active region 1a in the peripheral circuit portion is formed (step e10). 21A and 21B by patterning the nitride film 22 using the resist as an etching mask.
Is obtained (step e11).

The resist was stripped (step a12).
Thereafter, thermal oxidation is performed (step a13). By this thermal oxidation,
As shown in FIGS. 21A, 21B and 21C, the silicon nitride film 2 of the polycrystalline silicon film 14a is formed.
3 is selectively oxidized to form an oxide film 2
4 are formed. By this selective oxidation, a polycrystalline silicon film 14b whose both side surfaces are covered with the oxide film 24 is formed. During this thermal oxidation step, a thin oxide film 24 also grows on the surface of the silicon nitride film 23. The oxide film 24 on the nitride film 23 is etched with an HF aqueous solution (step e14).
After exposing the nitride film 23, the nitride film 2 is
3 is completely removed (step e15).

Next, as in the first embodiment, FIG.
(A), (b) and (c) of FIG.
The O insulating film 5 is formed (Step e16). Next, FIG.
(A), after forming a resist pattern 25 having an opening in the peripheral circuit portion as shown in FIGS. 6 (b) and 6 (c), the ONO insulating film 5 in the peripheral circuit portion is removed by etching (step). e18). In this embodiment, when the ONO insulating film 5 is etched, a portion of the polycrystalline silicon film 14b existing in the active region 1a of the peripheral circuit portion is removed. The subsequent steps are the same as in the first embodiment.

As described above, according to this embodiment, when the polycrystalline silicon film 14b is obtained from the polycrystalline silicon film 14a, the portion of the polycrystalline silicon film 14a to be removed is not removed by etching. Part is nitride film 2
3 is oxidized by a selective oxidation method using the mask as a mask. This oxidized portion is etched after the ONO insulating film 5 is etched. Therefore, when the ONO insulating film 5 is etched, the oxide film 24
The field oxide film 2 does not need to be etched because it is covered by the metal oxide. Therefore, the recess 17 is not formed in the field oxide film 2. Therefore, when manufacturing a memory cell by this method, the overlap margin between the field oxide film 2 and the floating gate 4 is set to 150.
nm. In this example, it was confirmed that the step at the boundary between the cell array section and the peripheral circuit section could be reduced to zero.

The thickness t14 of the polycrystalline silicon film 14a is
For example, the thickness is preferably as thin as 40 nm or less.
When the thickness t14 of the polycrystalline silicon film 14a is large, bird's beaks enter the interface between the nitride film 23 and the polycrystalline silicon film 14b when selectively oxidizing the same, and as a result, the floating gate 4 and the control gate 6 The facing area is reduced. For this reason, the coupling constant becomes small, and the current holding characteristic in the floating gate 4 is reduced. Further, the polycrystalline silicon film 14 may have a shape as shown in FIG. 24, and the floating gate 4 may remain without being etched when the control gate 6 is processed. Therefore, it is preferable that the polycrystalline silicon film 14 be thin. Incidentally, the polycrystalline silicon film 14 may be a non-doped film as in the second embodiment.

According to the memory cell manufactured by this manufacturing method, it is possible to achieve the same effect as that of each of the above-described embodiments, and also to achieve the above-described effect unique to this embodiment. Can be.

(Embodiment 6) Still another nonvolatile memory cell according to the present invention will be described. The structure of the memory cell of this embodiment is basically the same as the structure of the memory cell shown in FIGS. The present embodiment is characterized by its manufacturing method.

FIGS. 26 to 28 are cross-sectional views for explaining a part of the manufacturing process of the memory cell of this embodiment. For other processing steps of the manufacturing process of the present embodiment, FIGS. 4 to 13 of the first embodiment are appropriately referred to. FIG. 29 is a process diagram showing a manufacturing process of this example. FIG. 26 (a), FIG.
7 (a) and FIG. 28 (a) are cross-sectional lines X2-X of FIG.
27 is a sectional view taken along a cutting position corresponding to FIG.
(B), FIG. 28 (b) and FIG. 29 (b) are cross-sectional views of a portion corresponding to the section line X3-X3 in FIG.
(C), FIG. 27 (c), and FIG. 28 (c) are cross-sectional views of the peripheral circuit portion of the memory cell MC. This embodiment is similar to the first embodiment, and corresponding parts are denoted by the same reference numerals.

In steps f1 to f8 in this embodiment, the thickness t12 of the amorphous silicon film 12 was set to 22 nm as in the third embodiment. After performing arsenic ion implantation,
On the polycrystalline silicon film 14 formed by performing the first and second heat treatments, a film thickness t20 of 20 n
An m-th silicon nitride film is formed (step f9). Then
The memory cell portion has a pattern corresponding to the polycrystalline silicon film 14b, and the peripheral circuit portion has at least the active region 1a.
(Step f1)
0) After that, a portion of the silicon nitride film not covered with the resist is selectively etched (step f11). After the resist is stripped (step f12), thermal oxidation is performed (step f13), and the portion of the polycrystalline silicon film 14b that is not covered with the silicon nitride film is selectively thermally oxidized to form the oxide film 3
5 is formed. The steps up to here are substantially the same as the steps of the fifth embodiment.

Next, as shown in FIGS. 26A, 26B and 26C, a resist pattern 31 having an opening in a peripheral circuit portion is formed (step f14). The nitride film 30 and the polycrystalline silicon film 14b that are not covered with the pattern 31 are etched. Thus, FIG.
As shown in FIG. 6C, the tunnel oxide film 3 is exposed in the peripheral circuit portion. Next, FIG. 27A and FIG.
And, as shown in FIG.
After removing 1 (step f15), the tunnel oxide film 3 remaining in the active region 1a of the peripheral circuit portion is removed by etching with an HF aqueous solution. Thereafter, the portion where the tunnel oxide film 3 was located is thermally oxidized (step f16). At this time, a thin oxide film also grows on nitride film 30 left in the cell array portion. After the thin oxide film grown on the nitride film 30 is etched with an HF aqueous solution (step f17), the nitride film 30 is heated with a hot concentrated phosphoric acid solution.
Is removed (step f18).

After the cleaning, as shown in FIGS. 28 (a), (b) and (c), an oxidation step is performed again to form a gate oxide film 34 on the active region 1a of the peripheral circuit portion.
Is formed (step f19), and an oxide film 32 having a thickness of 10 nm is grown on the floating gate 4 (step f20).

[0115] The subsequent step of depositing a WSi _x 8 / polycrystalline silicon film 7 for control gate 6 step f21, f2
Steps f2 and f23 are the same as steps a14 to a16 in the first embodiment.

As described above, according to this embodiment, when the polycrystalline silicon film 14b is obtained from the polycrystalline silicon film 14a, the portion of the polycrystalline silicon film 14a to be removed is not removed by etching. Part is nitride film 3
Oxidation is performed by a selective oxidation method using 0 as a mask. This oxidized portion is etched after the ONO insulating film 5 is etched. Therefore, when the ONO insulating film 5 is etched, the field oxide film 2 does not need to be etched because the periphery of the polycrystalline silicon film 14b is covered with the oxide film. Therefore, the recess 17 is not formed in the field oxide film 2. Therefore, when a memory cell is manufactured by this method, the overlap margin between the field oxide film 2 and the floating gate 4 is set to 150 nm.
Can be In this example, it was confirmed that the step at the boundary between the cell array section and the peripheral circuit section could be reduced to zero. The floating gate 4 may be non-doped as in the fourth embodiment.

According to the present embodiment as described above, the same effects as those described in each of the above embodiments can be achieved, and the effects unique to the present embodiment as described above can be achieved. it can.

[0118]

As described above, according to the present invention, the floating gate is ultra-thinned to a thickness of 55 nm or less, preferably 40 nm or less, so that the element isolation film can be formed at the time of processing the second insulating film on the floating gate. The conventional problem that a recess is formed is solved, and high integration of a memory cell is facilitated. Also,
By reducing the step caused by the floating gate,
The focus margin at the time of exposure increases, and manufacturing becomes easy.

By using a polycrystalline silicon film crystallized from an amorphous silicon layer as a material, a floating gate with less surface irregularities can be realized. By using such a floating gate, the surface of the floating gate can be thermally oxidized to form a high-quality second insulating film. This allows
The second insulating film thinner than the conventional ONO thin film can be formed.

By forming the floating gate with an ultra-thin film, it becomes possible to use a floating gate using a non-doped polycrystalline silicon film. According to such a floating gate, not only the step of diffusing impurities into the thin polycrystalline silicon film can be omitted, but also the operation speed is significantly improved by the dielectric properties of the non-doped polycrystalline silicon film.

Further, by forming a floating gate pattern from a polycrystalline silicon film by a selective oxidation method,
The etching of the second insulating film does not need to be performed on the step of the floating gate, and the overlap margin between the field oxide film and the floating gate can be ideally reduced to zero.

[Brief description of the drawings]

FIG. 1 is a plan view of a memory cell MC of a flash memory according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along a section line X2-X2 in FIG.

FIG. 3 is a cross-sectional view taken along the line X3-X3 of FIG. 1;

FIG. 4 is a cross-sectional view for explaining a manufacturing process of the memory cell MC of the present embodiment.

FIG. 5 is a cross-sectional view for explaining a manufacturing process of the memory cell MC of the present embodiment.

FIG. 6 is a cross-sectional view for explaining a manufacturing process of the memory cell MC of the present embodiment.

FIG. 7 is a cross-sectional view for explaining a manufacturing process of the memory cell MC of the present embodiment.

FIG. 8 is a cross-sectional view for explaining a manufacturing process of the memory cell MC of the present embodiment.

FIG. 9 is a cross-sectional view for explaining a manufacturing step of the memory cell MC of the present embodiment.

FIG. 10 is a cross-sectional view for explaining a manufacturing step of the memory cell MC of the present embodiment.

FIG. 11 is a cross-sectional view for explaining a manufacturing step of the memory cell MC of the present embodiment.

FIG. 12 is a cross-sectional view for explaining a manufacturing step of the memory cell MC of the present embodiment.

FIG. 13 is a cross-sectional view for explaining a manufacturing step of the memory cell MC of the present embodiment.

FIG. 14 is a process chart showing a manufacturing process of the present example.

FIG. 15 is a process chart illustrating a process of manufacturing a memory cell according to the second embodiment of the present invention.

FIG. 16 is a cross-sectional view for explaining a part of the manufacturing process of the memory cell according to the third embodiment of the present invention.

FIG. 17 is a cross-sectional view for describing a part of the manufacturing process of the memory cell according to the present embodiment.

FIG. 18 is a process chart showing a manufacturing process of this example.

FIG. 19 is a process chart illustrating a manufacturing method according to a fourth example of the present invention.

FIG. 20 is a cross-sectional view for explaining a part of the manufacturing process according to the fifth embodiment of the present invention.

FIG. 21 is a cross-sectional view for explaining a part of the manufacturing process of the present embodiment.

FIG. 22 is a cross-sectional view for explaining a part of the manufacturing process of the present embodiment.

FIG. 23 is a cross-sectional view for explaining a part of the manufacturing process of the present embodiment.

FIG. 24 is a cross-sectional view for explaining a part of the manufacturing process of the present embodiment.

FIG. 25 is a process chart showing a manufacturing process of the present example.

FIG. 26 is a cross-sectional view for explaining a part of the manufacturing process according to the sixth embodiment of the present invention.

FIG. 27 is a cross-sectional view for explaining a part of the manufacturing process of the present embodiment.

FIG. 28 is a cross-sectional view for explaining a part of the manufacturing process of the present embodiment.

FIG. 29 is a process chart showing the manufacturing process of this example.

FIG. 30 is a plan view of a conventional memory cell.

FIG. 31 is a section line X31 of FIG. 30 of the conventional memory cell;
It is sectional drawing seen from -X31.

32 is a sectional line X32 of FIG. 30 of the conventional memory cell;
It is sectional drawing seen from -X32.

FIG. 33 is a section line X33 of FIG. 30 of the conventional memory cell;
It is sectional drawing seen from -X33.

FIG. 34 is a cross-sectional view illustrating a problem of a conventional memory cell.

[Explanation of symbols]

Reference Signs List 1 silicon substrate 1a active region 2 field oxide film (LOCOS film) 3 tunnel oxide film (first insulating film) 4 floating gate 5 ONO insulating film (second insulating film) 6 control gate 6 7 N ⁺ polycrystalline silicon film 8 WSi _x film 10 source region 11 drain region 14a polycrystalline silicon film 14b polycrystalline silicon film

Continuation of front page (56) References JP-A-4-239180 (JP, A) JP-A-3-196673 (JP, A) JP-A-5-267683 (JP, A) JP-A-2-31467 (JP, A) JP-A-6-204486 (JP, A) JP-A-6-163925 (JP, A) JP-A-5-121755 (JP, A) JP-A-5-110107 (JP, A) JP-A-4-208574 (JP, A) JP-A-4-57369 (JP, A) JP-A-1-129465 (JP, A) JP-A-64-13771 (JP, A) JP-A-63-111670 (JP, A) A) JP-A-63-1076 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (3)

(57) [Claims] A step of forming a first insulating film on the semiconductor substrate; a step of forming a floating gate on the first insulating film; a step of forming a second insulating film on the floating gate; Forming a control gate on a second insulating film, wherein the step of forming the floating gate comprises: depositing an amorphous silicon film on the first insulating film. And recrystallizing the amorphous silicon film by annealing, so that the impurity concentration becomes 1 so as to be regarded as a dielectric during memory operation.
Forming a non-doped polycrystalline silicon film of × 10 ¹⁹ / cm ³ or less; depositing an oxidation resistant film on the polycrystalline silicon film; patterning the oxide resistant film into a predetermined shape; Selectively oxidizing a portion of the polycrystalline silicon film using the anti-oxidation film as a mask. 2. The annealing includes a first annealing step performed at a first predetermined temperature and a second annealing step performed at a second predetermined temperature higher than the first predetermined temperature. The method according to claim 1. Forming a first insulating film on the semiconductor substrate; forming a floating gate on the first insulating film; forming a second insulating film on the floating gate; Forming a control gate on a second insulating film, wherein the step of forming the floating gate comprises: depositing an amorphous silicon film on the first insulating film. And recrystallizing the amorphous silicon film by annealing, so that the impurity concentration becomes 1 so as to be regarded as a dielectric during memory operation.
Forming a non-doped polycrystalline silicon film of × 10 ¹⁹ / cm ³ or less; and forming the floating gate from the polycrystalline silicon film, wherein the annealing is performed at a first predetermined temperature. And a second annealing step performed at a second predetermined temperature higher than the first predetermined temperature.