JP2727136B2 - Electrically erasable and electrically programmable memory device having self-aligned tunnel dielectric region and method of making same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically erasable and electrically programmable memory device having a floating gate self-aligned thin tunnel dielectric region and a method of making the same.

[0002]

2. Description of the Related Art U.S. Pat. No. 4,115,914 (issued to Harari on September 26, 1978); U.S. Pat. No. 4,203,158 (Froman-Bentch, May 13, 1980). Since the invention of a non-volatile memory cell having both electrically erasable and electrically programmable capabilities as disclosed in US Pat. EE using dielectric
Industrial mass production of PROMs has become increasingly real. The EEPROM comprises a selection device in series with a memory device having a floating gate on the channel and a tunnel dielectric region on the drain and a control gate stacked on the floating gate.

[0003] Programming of a memory device is accomplished by applying a suitable voltage across the drain and control gate of the memory device to tunnel charge carriers from the floating gate to the drain through the tunnel dielectric. Erasing the memory device is accomplished by applying an appropriate voltage across the control gate and drain of the memory device to tunnel charge carriers from the drain to the floating gate through the tunnel dielectric.

[0004]

SUMMARY OF THE INVENTION The tunnel dielectric region on the drain of a memory device is usually determined by photo-etching techniques. The area required to accommodate the tunnel dielectric region is usually large due to the dimensional limitations and alignment tolerances of photolithography. In addition to area requirements, the tunnel dielectric region alone has important effects. The smaller the tunnel dielectric region, the lower the high voltage required for programming and erasing the memory device. Furthermore, the larger the tunnel dielectric region, the higher the defect density and the lower the yield.

[0005]

SUMMARY OF THE INVENTION It is, therefore, a primary object of the present invention to provide an improved EEPROM. The proposed improved buried drain and buried source are located above the channel and between 200A and 1000A
A floating gate insulated from the channel by the gate oxide of A, additional floating gate electrically shorted to the floating gate and insulated from the buried drain by the tunnel dielectric of 40A-120A; A selection device is provided in series with a memory device having a control gate over and insulated from the floating gate. EEPRO
The improvement with the proposed memory device in M is that the tunnel dielectric region is very small and self-aligned to the floating gate.

Another object of the present invention is to provide a method for making an electrically erasable and electrically programmable memory storage device according to two advantageous implementations of the present invention.

[0007] These and other objects of the present invention are achieved by a method of manufacturing an EEPROM memory device on a semiconductor substrate. The method includes etching the first polysilicon layer into a floating gate and sealing the floating gate sidewall with nitride to prevent oxidation of the floating gate sidewall during tunnel dielectric formation. The nitride is removed from all regions except the region of the floating gate sidewall using anisotropic etching properties. After the impurity implantation to form the buried source / drain regions, the oxide is removed from the tunnel dielectric region to form a tunnel dielectric.

Next, the sealing nitride on the side walls of the floating gate is removed in hot phosphoric acid, and an additional polysilicon layer is deposited and doped. The properties of the anisotropic polysilicon etch are used for all additional polysilicon removal except for the floating gate sidewall only. The first floating gate with the additional polysilicon on the sidewall becomes the new floating gate.

Next, an oxide is grown to seal the edges of the additional polysilicon and the exposed tunnel dielectric regions. The small tunnel dielectric region under the additional polysilicon becomes a new tunnel dielectric self-aligned to the original floating gate. This method of forming a small self-aligned tunnel dielectric region is used in two advantageous implementations of non-self-aligned and self-aligned EEPROM manufacturing.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The method of the present invention comprises a non-self-aligned EEPROM as described in the first preferred embodiment shown in FIG.
4 to produce a self-aligned EEPROM as described in the second preferred embodiment.

FIGS. 1, 2 and 3 show a first preferred embodiment of a set of mirror image non-self-aligned EEPROMs. The EEPROM including the selection device 1 and the memory device 2 is formed on a P-type substrate 9 made of single crystal silicon. The memory device 2 is located above the channel region and is electrically shorted to the floating gate 30, the floating gate 30 separated from the channel region by the gate oxide 21; An additional floating gate 31, separated from the buried drain by a dielectric 22, a floating gate 30, and a control disposed on the additional floating gate 31 and separated from these floating gates by inter-gate dielectrics 40 and 41 It includes a gate 50, and a buried n + junction 10 which serves as the buried source and buried drain of the EEPROM.

The buried source and buried drain are located below the additional floating gate 31 and the control gate 50, and are separated from the control gate 50 by an inter-gate dielectric 41 and an oxide layer 23. The shallow junction 11 forms the source and drain of the peripheral transistor. Metal wiring 80
Is connected via the contact 70 to the drains of all selected devices of the EEPROM in the same row. Doped C
The VD oxide film 60 is under the metal wiring to smooth sharp edges. Thick field oxide 20 helps to isolate between different devices.

When an appropriate voltage is applied to the control gate 50 while the buried drain is grounded, electrons tunnel from the buried drain through the tunnel dielectric 22 to the floating gate 30 and the additional floating gate 31. On the other hand, when the appropriate voltage is applied to the buried drain with the control gate 50 grounded, electrons tunnel from the additional floating gate 31 through the tunnel dielectric 22 to the buried drain. If the floating gate 30 and the additional floating gate 31 of the EEPROM memory device 2 have excess electrons, the EEPROM
Since the current is conducted through the OM memory device 2, the positive voltage required for the control gate 50 is high.

On the other hand, if the floating gate 30 and the additional floating gate 31 of the memory device 2 of the EEPROM lack electrons, the EEPROM
Since the current is conducted through the M memory devices 2, the positive voltage required for the control gate 50 is reduced. Therefore, it is determined whether or not there is a current conducted through the memory device 2 of the EEPROM at the voltage applied to the control gate 50.
Indicates whether 1 or 0 is stored in the memory device 2 of the EPROM.

FIGS. 1 to 3 also show how the EEPROM is connected to the memory array. Diffusion line 225 is the common source line for the EEPROM in two adjacent columns, control gate 50 is the common control gate line for all EEPROMs in the same column, and common control gate line 90 is the same for all select lines. The gate of the device, the metal bit line 80 is connected via the contact 70 to the EEPROM of the same row.
The drains of all selected devices. All EEPROMs in the memory array can be arranged as mirror images as shown in FIG.

The fabrication of the memory array including the set of EEPROMs shown in FIGS. 1-3 is now described in detail. For convenience of explanation, an n-channel EEPROM array will be used as an example. P-type single crystal silicon is used as a starting substrate. n
Depositing a CVD nitride thin film on the first oxide grown on the P-type substrate, as in conventional manufacturing of channel EEPROMs. Next, a photoresist pattern in the active region is formed on the nitride film, and the nitride outside the photoresist pattern is corroded and removed.

Next, P-type impurity boron is implanted into the region outside the photoresist pattern to increase the doping of the substrate outside the active region. This is done to increase the threshold voltage of the parasitic field device and improve the isolation between active regions. The photoresist pattern is stripped after boron implantation and a thick field oxide 20 is grown outside the active area. During field oxidation, active regions 25 and 225 are still protected by the nitride pattern and no oxide is generated. After the field oxide 20 has grown,
The initial oxide beneath the nitride in the active regions 25 and 225 is stripped, exposing the substrate only in the active regions.

Next, a high quality gate oxide 21 of 200A to 1000A is grown in the active regions 25 and 225, a photoresist pattern is formed and 3E11 to 3E12 / c are formed.
Exposing the EEPROM area for an m ² dose boron implant. After stripping the photoresist pattern, the first layers 30 and 90 of polysilicon are deposited and doped.

Next, oxide layers 39 and 99 are grown on the first layers 30 and 90 of polysilicon. Oxide 39
To have a gate 90 of the selection device having a floating gate 30 and oxide 99 having, a photoresist pattern, removing the polysilicon from the outer region of the photoresist pattern. FIGS. 4 and 5 show a cross section taken along line AA and a cross section taken along line BB after the photoresist pattern is removed.

Next, as shown in FIGS. 6 and 7, a seal nitride film 49 is deposited and oxidized. 8 and 9, an anisotropic etch is used to remove all of the nitride except the sealing nitride 48 on the sidewalls of the floating gate 30 and the gate 90 of the select device. next,
As shown in FIG. 10 and FIG.
6 is formed to expose the EEPROM region for the buried n + implant layer 10 at a dose of 5E13 to 5E15 / cm ² .

After removing the photoresist pattern ,
As shown in FIG. 2 and FIG. 13, a new photoresist pattern
A trench 29 is formed to expose the tunnel dielectric region of the drain of the EEPROM memory device. The oxide is etched away to expose the substrate 27. Next, the photoresist pattern
The tunnel is stripped to form a tunnel dielectric 28 as shown in FIGS. The sealing nitride on the sidewalls of the floating gate 30 and the gate 90 of the selection device is later removed with hot phosphoric acid.

As shown in FIGS. 16 and 17, an additional polysilicon layer 38 is deposited and doped. As shown in FIG. 18 and FIG.
An anisotropic polysilicon etch is used to remove any additional polysilicon except the additional polysilicon 31 on the sidewalls of the floating gate 30 and the additional polysilicon 91 on the select gate sidewalls to form the gate. The tunnel dielectric region 22 under the additional floating gate 31 becomes a new small tunnel dielectric region. The oxide layer 39 on the floating gate 30 and the oxide layer 99 on the select gate are then removed, and a high quality oxide layer 40 is grown on the floating gate 30 while simultaneously exposing the tunnel dielectric region exposing the oxide 23. To grow.

As shown in FIGS. 20 and 21, a high quality nitride film 41 is deposited and oxidized later. Next, a photoresist pattern is formed to protect the EEPROM region and the first polysilicon gate region during removal of the nitride 41 and oxide 23. Impurity implantation is performed to grow a high quality gate oxide for the second silicon device and adjust the threshold of the second polysilicon device.

Next, a second layer of polysilicon is deposited,
Dope. The control gate 50 and the second polysilicon gate pattern are patterned using a photoresist pattern . The control gate formation after removing the resist is shown in FIG.
23 and FIG. The rest of the manufacturing process is similar to that of a conventional n-channel EEPROM. After forming the second polysilicon pattern, a shallow source / drain junction 11 is implanted, a doped CVD oxide film is deposited, contacts are opened, a metal film is deposited and patterned.

FIGS. 24, 25 and 26 show a second preferred embodiment of a set of mirror image self-aligned EEPROMs. E consisting of the selection device 1 and the memory device 2
The EPROM is formed on a P-type substrate 9 made of single crystal silicon or the like. Memory device 2 is disposed above the channel region and the floating gate 30 is separated from the channel region by a gate oxide 21, electrically short-circuited to the floating gate 30 is disposed over the buried drain, and the tunnel Additional floating gate 3 separated from buried drain by dielectric 22
1. placed on the floating gate 30;
Control gate 50 and EEPRO separated from floating gate 30 by inter-gate dielectrics 40 and 41
M includes a buried n + junction 10 which serves as a buried source and a buried drain for M.

The buried source and the buried drain are located below the additional floating gate 31. Additional floating gate 31 is located on the side wall of control gate 50 and is insulated from control gate 50. The shallow junction 11 forms the source and drain of the peripheral transistor. The metal wiring 80 is connected to the EEPROM of the same row through the contact 70.
To the drains of all selected devices. Doped CVD oxide film 60 smooths sharp edges of metal wiring
Below the wiring . Thick field oxide 2
0 serves as a separator between different devices.

When an appropriate voltage is applied to the control gate 50 with the buried drain grounded, electrons tunnel from the buried drain to the additional floating gate 31 through the tunnel dielectric 22. Conversely, when a suitable voltage is applied to the buried drain with the control gate 50 grounded, electrons tunnel from the additional floating gate 31 to the buried drain via the tunnel dielectric 22.

Excess electrons in the floating gate 30 and additional floating gate 31 of the EEPROM memory device 2 increase the positive voltage required at the control gate 50 to conduct current through the EEPROM memory device 2. On the other hand, if the electrons in the floating gate 30 and the additional floating gate 31 of the memory device 2 of the EEPROM are insufficient, the EE
The positive voltage required at control gate 50 to conduct current through PROM memory device 2 is reduced. Therefore, whether or not a 1 or 0 is stored in the EEPROM memory device 2 can be indicated by the presence or absence of the current flowing through the EEPROM memory device 2 at the voltage applied to the control gate 50.

FIG. 24 further shows the situation of connecting the EEPROM to the memory array. Diffusion line 225 is the common source line for two adjacent columns of EEPROM, control gate 50 is the common control gate line for all EEPROMs in the same column, and gate 90 is the common source line for all EEPROMs in the same column. As a common gate, metal bit line 80 couples the drains of all selected devices in the same row via contacts 70. All EEPROMs are arranged as mirror images of one another, as shown in FIG.

EEPROM shown in FIGS. 24, 25 and 26
A method for fabricating a memory array including one set of For convenience of explanation, an n-channel EEPROM array will be used as an example. P-type single crystal silicon is used as a starting substrate. A CVD nitride thin film is deposited on the first oxide grown on the P-type substrate as in the conventional n-channel EEPROM manufacturing method.

Next, a photoresist pattern in the active region is formed on the nitride film, and the nitride outside the photoresist pattern is corroded and removed. Next, P-type impurity boron is implanted into a region outside the photoresist pattern to enhance substrate doping outside the active region. This is done to increase the threshold voltage of the parasitic field device so as to provide good isolation between the active regions. After the boron implantation, the photoresist pattern is stripped and a thick field oxide 20
Is grown outside the active region. During field oxidation
Active regions 25 and 225 are still protected by the nitride pattern and there is no oxide growth. Field oxide 2
After the 0 grows, the nitride in the active regions 25 and 225 and the initial oxide under the nitride are stripped to expose the substrate only in the active region.

Next, a high quality gate oxide 21 of 200A to 1000A is grown in the active regions 25 and 225, and a photoresist pattern is formed to form 3E11 to 3E12 / c.
Exposing EEPROM area for m ² dose boron implant. After stripping the photoresist pattern, a first layer of polysilicon 35 is deposited and doped. Next, the first polysilicon is patterned using a photoresist pattern. After stripping the photoresist pattern, high quality oxides 40 and 45 are grown on the first polysilicon, and then high quality nitride films 41 and 46 are deposited and oxidized.

Next, a photoresist pattern is formed to protect the EEPROM region and the first polysilicon region while removing the nitride 46 and oxide from the second silicon device region. A high quality gate oxide for the second polysilicon device is grown and an impurity implant is performed to adjust the threshold of the second polysilicon device. Next, a second layer of polysilicon is deposited and doped. The pattern of the control gate 50 and the second polysilicon gate is patterned using a photoresist pattern. After stripping the photoresist, an oxide layer 51 is applied to the second polysilicon control gate 5 as shown in FIGS.
Grow over 0 and other second polysilicon.

Next, the nitrided film 46 outside the second polysilicon control gate is removed by corrosion. 29, a photoresist pattern 56 is used to expose only the EEPROM.
Then, as shown in FIG. 30, the first polysilicon outside the second polysilicon control gate is corroded and removed. After the photoresist pattern is stripped, a seal nitride film 59 is deposited and oxidized as shown in FIGS. Anisotropic etching is used to remove all of the nitride except for the seal nitride 58 on the sidewalls of the floating gate 30.

Next, a photoresist pattern is formed and 5
E13 to 5E15 / cm ² dose buried n + implantation layer 1
Exposing the EEPROM area for 0. After exposing the photoresist pattern, a new photoresist pattern 69 is formed to expose the tunnel dielectric region of the drain of the EEPROM as shown in FIGS. 33 and 34, and the oxide is corroded and removed so as to expose the substrate 68. I do. The photoresist pattern is stripped again, and then the tunnel dielectric 2 is removed.
8 is formed.

Next, the sealing nitride on the side wall of the floating gate 30 is removed with hot phosphoric acid. An additional polysilicon layer is deposited and doped. Floating gate 30 for forming additional floating gate 31
An anisotropic polysilicon etch is used to remove all the additional polysilicon film except for the additional polysilicon 31 on the sidewalls of FIG. Additional floating gate 31
The resulting tunnel dielectric region 22 becomes a new small tunnel dielectric region.

As shown in FIGS. 35 and 36, the photoresist pattern 67 is used to remove additional polysilicon from the sidewalls of all other polysilicon patterns while removing the polysilicon.
Protect EPROM. After the photoresist pattern is stripped, the shallow source / drain junction 11 is implanted to form the EEPROM shown in FIGS. The other manufacturing steps are the same as those of the conventional n-channel EEPROM. An oxide is grown on the additional polysilicon and the exposed tunnel dielectric regions, a doped CVD oxide is deposited, contacts are opened, a metal film is deposited and patterned.

The invention has been described in terms of two advantageous embodiments. Various modifications of the advantageous embodiments disclosed herein can be made by those skilled in the art without departing from the scope and spirit of the invention in light of this disclosure. further,
Such improvements are considered to be within the scope of the following claims. The novel features of the invention are set forth in the following claims. The invention itself and other features, together with advantages thereof, will be more readily understood from the foregoing detailed description read in conjunction with the drawings.

[0039]

According to the present invention as described above, the tunnel dielectric region can be formed extremely small. The high power required for programming and erasing of the memory device can be reduced as the tunnel dielectric region is smaller, so that the area requirement can be sufficiently satisfied and the required high power can be reduced. Further, by tunnel dielectric region is small, the defect density is low, production, in addition to the yield is high, like that are self-aligned for the floating gate to solve the problems, it can electrically programmed and erased EE
This enables industrial mass production of PROM devices.

[Brief description of the drawings]

FIG. 1 is a plan view of a set of non-self-aligned EEPROM memory cells constructed according to a first embodiment of the present invention. FIG. 2 is a sectional view taken along line AA of FIG. FIG. 3 is a sectional view taken along line BB of FIG. FIG. 4 is a cross-sectional view corresponding to the line AA of FIG. 1, illustrating formation of a first polysilicon floating gate during a front end processing step according to the first embodiment of the present invention. FIG. 5 is a sectional view corresponding to line BB in FIG. FIG. 6 is a cross-sectional view corresponding to the line AA of FIG. 1, showing the deposition of a seal nitride after the formation of the first polysilicon floating gate according to the first embodiment of the present invention. FIG. 7 is a sectional view taken along the line BB of FIG. FIG. 8 shows the formation of a seal nitride on the side wall of the first polysilicon floating gate according to the first embodiment of the present invention.
Sectional drawing corresponding to the AA line of FIG. FIG. 9 is a sectional view corresponding to line BB of FIG. FIG. 10 is a cross-sectional view corresponding to the line AA of FIG. 1, showing impurity implantation for forming a buried source and a buried drain of the EEPROM according to the first embodiment of the present invention. FIG. 11 is a sectional view corresponding to the line BB of FIG. FIG. 12 is a cross-sectional view taken along the line AA of FIG. 1 showing oxide removal from the tunnel dielectric region according to the first embodiment of the present invention. FIG. 13 is a cross-sectional view corresponding to line BB of FIG. FIG. 14 is a cross-sectional view taken along the line AA of FIG. 1, illustrating formation of a tunnel dielectric according to the first embodiment of the present invention. FIG. 15 is a sectional view corresponding to line BB of FIG. FIG. 16 is a cross-sectional view corresponding to the line AA of FIG. 1 showing additional polysilicon deposition after removing the seal nitride from the first polysilicon floating gate sidewall according to the first embodiment of the present invention. FIG. 17 is a cross-sectional view corresponding to line BB of FIG. FIG. 18 illustrates additional polysilicon formation on the sidewalls of a first polysilicon floating gate to form a new floating gate according to a first embodiment of the present invention.
Sectional drawing corresponding to the AA line of FIG. 19 is a sectional view corresponding to the line BB of FIG. FIG. 20 is a cross-sectional view corresponding to the line AA of FIG. 1 showing formation of an inter-gate dielectric according to the first embodiment of the present invention. FIG. 21 is a sectional view corresponding to line BB of FIG. FIG. 22 is a cross-sectional view taken along the line AA of FIG. 1 showing a second polysilicon control formation according to the first embodiment of the present invention. FIG. 23 is a sectional view taken along the line BB of FIG. FIG. 24 is a plan view of a set of self-aligned EEPROM memory cells constructed according to a second embodiment of the present invention. FIG. 25 is a sectional view taken along line AA of FIG. FIG. 26 is a sectional view taken along line BB of FIG. FIG. 27 is a cross-sectional view corresponding to line AA of FIG. 24, illustrating oxidation after forming a second polysilicon control gate during a front end processing step according to the second embodiment of the present invention. FIG. 28 is a cross-sectional view corresponding to line BB of FIG. FIG. 29 is a cross-sectional view corresponding to the line AA of FIG. 24 showing a first polysilicon etching having a photoresist pattern for protecting the first polysilicon device according to the second embodiment of the present invention. FIG. 30 is a sectional view taken along the line BB of FIG. FIG. 31 is a cross-sectional view corresponding to the line AA of FIG. 24 showing seal nitride deposition after the formation of the first polysilicon floating gate according to the second embodiment of the present invention. FIG. 32 is a sectional view taken along the line BB of FIG. FIG. 33 is a cross-sectional view corresponding to the line AA of FIG. 24, illustrating oxide removal from the tunnel dielectric region according to the second embodiment of the present invention. FIG. 34 is a sectional view taken along line BB of FIG. 35. A new floating gate made of additional polysilicon on the first polysilicon nulling gate sidewall while removing all additional polysilicon on the sidewalls of all other polysilicon patterns according to the second embodiment of the present invention. FIG. 25 is a cross-sectional view taken along the line AA of FIG. FIG. 36 is a cross-sectional view corresponding to line BB of FIG. FIG. 37 is a sectional view taken along line AA of FIG. 24 showing a new floating gate made of additional polysilicon on the first polysilicon floating gate sidewall according to the first embodiment of the present invention. FIG. 38 is a sectional view taken along the line BB of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Selection device 2 Memory device 9 Substrate 10 n + junction 21 Gate oxide 22 Tunnel dielectric 30 Floating gate 31 Additional floating gate 50 Control gate

Claims (12)

(57) [Claims] 1. A method of forming a small tunnel dielectric region self-aligned with an electrically floating conductive gate, comprising: forming a first conductive floating gate on a dielectric layer over a semiconductor region; A second dielectric film is deposited on the gate, a second dielectric film for sealing is formed on the side wall of the first floating gate by anisotropic etching of the second dielectric film, and impurities are introduced into the semiconductor region. Forming a doping region, forming a tunnel dielectric on the buried doping region, removing the second dielectric film for sealing from the side wall of the first floating gate, and adding an additional material of the same material as the first floating gate. A conductive film is deposited on the tunnel dielectric and the floating gate, and the additional conductive film is anisotropically etched to form a second conductive film. A small tunnel dielectric region self-aligned with the electrically floating conductive gate, characterized in that an additional floating conductive gate electrically shorted to the first floating is formed on the side wall of the floating gate. How to form. Wherein said first process according to claim 1, wherein the conductive floating gate and said additional conductive film is a polysilicon film doped. 3. The method of claim 1, wherein said second dielectric film is a silicon nitride film. 4. A semiconductor material substrate having a channel region of a first conductivity type between a first and a second region of a second conductivity type, formed on a surface thereof, wherein said channel region is formed by said channel region. A first level having a semiconductor internal region between the first and second regions through which a current can flow and forming a floating gate;
A floating gate extending substantially over the channel region between the first and second regions and electrically insulated from the semiconductor substrate by the first layer of dielectric material. An electrically rewritable non-volatile, floating gate type electrically isolated from a second level patterned conductive material forming a control gate overlying the floating gate with a second layer of dielectric material in the memory device has a tunnel area partitioned into one surface of the first and second regions of the semiconductor substrate, the tunnel region in contact with one side thereof a portion of the length of the sidewall of the floating gate
Formed by a third layer of dielectric material that is thinner than the first layer of dielectric material, further comprising a side surface of a conductive material disposed along the portion of the sidewall length of the floating gate. having an additional floating gate,
Contact the bottom surface of additional floating gate side of the conductive material and the tunnel region covering the surface of the dielectric material of the third layer, the first level conductive said additional floating gate has the patterned constituting the floating gate An electrically rewritable non-volatile, floating gate type memory device characterized by being electrically coupled to the material along the entire circumference of the floating gate. 5. The method according to claim 1, wherein the thickness of the dielectric material of the third layer is 40 to 40.
5. The device of claim 4, which is 50 Angstroms. 6. The device of claim 4, wherein said additional floating gate and said patterned first level conductive material both comprise doped polysilicon. 7. The device of claim 4, wherein said second type conductivity is n-type. 8. The device of claim 4, wherein said first layer of dielectric material and said third layer of dielectric material are oxide layers. 9. The device of claim 6, wherein the conductivity of the second type is n-type and the polycrystalline silicon is doped n-type. 10. The method according to claim 1, wherein the thickness of the dielectric material of the first layer is 20.
6. The device of claim 5, wherein said device is between 0 and 1000 Angstroms. 11. The first device having a tunnel region on a surface thereof.
And a third region of the second type conductivity is released by the second channel region from one of the first electrically conductive second region,
5. The device of claim 4, comprising an access gate electrode overlapping said first channel and separated from said channel by a gate insulator. 12. A memory array comprising a plurality of electrically rewritable nonvolatile floating gate device type memory devices according to claim 11, wherein the devices are arranged in rows and columns of a matrix and word lines extending along each row. A memory array, wherein the access gate electrode of each memory device in one row is coupled to a word line in a corresponding row and to a bit line extending along each column.